Lines Matching full:host

12 Address space is handled via HDM (Host Managed Device Memory) decoders
14 range across multiple devices underneath a host-bridge or interleaved
15 across host-bridges.
25 multiple Host Bridges and endpoints while another may opt for fault tolerance
30 dictates which endpoints can participate in which Host Bridge decode regimes.
33 given range only decodes to 1 one Host Bridge, but that Host Bridge may in turn
39 module generates an emulated CXL topology of 2 Host Bridges each with 2 Root
50           "host":"cxl_host_bridge.1",
54               "host":"cxl_switch_uport.1",
58                   "host":"mem2",
65                     "host":"cxl_mem.1"
70                   "host":"mem6",
77                     "host":"cxl_mem.5"
84               "host":"cxl_switch_uport.3",
88                   "host":"mem8",
95                     "host":"cxl_mem.7"
100                   "host":"mem4",
107                     "host":"cxl_mem.3"
116           "host":"cxl_host_bridge.0",
120               "host":"cxl_switch_uport.0",
124                   "host":"mem1",
131                     "host":"cxl_mem.0"
136                   "host":"mem5",
143                     "host":"cxl_mem.4"
150               "host":"cxl_switch_uport.2",
154                   "host":"mem7",
161                     "host":"cxl_mem.6"
166                   "host":"mem3",
173                     "host":"cxl_mem.2"
244           "host":"cxl_mem.2"
254 Host Bridges, a PMEM interleave that targets a single Host Bridge, a Volatile
255 memory interleave that spans 2 Host Bridges, and a Volatile memory interleave
256 that only targets a single Host Bridge.
271             "host":"cxl_mem.0"
279             "host":"cxl_mem.4"
287             "host":"cxl_mem.6"
295             "host":"cxl_mem.2"