Lines Matching full:error
329 :c:func:`irq_clear` hook, which simply clears the interrupt and error flags
375 Error handling
393 midlayer. libata internal commands are used for initialization and error
466 pio_task invokes :c:func:`ata_qc_complete`. In error cases, packet_task may
493 code path is taken and very little error handling takes place. A qc is
499 :c:func:`ata_qc_complete` is invoked with error status, which in turn invokes
514 timeout and ATAPI error completion. This function will check if a qc is active
541 - Error representation is too crude. Currently any and all error
542 conditions are represented with ATA STATUS and ERROR registers.
544 errors by setting ATA_ERR bit. Better error descriptor which can
555 - Too weak error recovery. Devices / controllers causing HSM mismatch
557 state. Also, advanced error handling is necessary to support features
561 errors in pio_task. This is problematic for advanced error handling
564 First, advanced error handling often requires context and internal qc
567 Second, even a simple failure (say, CRC error) needs information
568 gathering and could trigger complex error handling (say, resetting &
575 its part of error handling. This can be error prone and painful.
603 This chapter tries to identify what error/exception conditions exist for
607 The term 'error' is used to describe conditions where either an explicit
608 error condition is reported from device or a command has timed out.
612 errors and non-error exceptional conditions. Where explicit distinction
613 between error and exception is necessary, the term 'non-error exception'
621 for error reporting, mapping those into categories described below
631 This error is indicated when STATUS value doesn't match HSM requirement
643 terminate the PACKET command with an error before the last byte of
644 the command packet has been written" in the error outputs description
649 error can be acquired from STATUS or ERROR register. IOW, this error can
656 ATA/ATAPI device error (non-NCQ / non-CHECK CONDITION)
660 device problems. For this type of errors, STATUS and ERROR register
661 values are valid and describe error condition. Note that some of ATA bus
683 `ATA bus error <#excatATAbusErr>`__.
685 CRC error during data transfer
686 This is indicated by ICRC bit in the ERROR register and means that
692 ABRT error during data transfer or on completion
706 This is indicated by UNC bit in the ERROR register. ATA devices
707 reports UNC error only after certain number of retries cannot
713 on error completion is indeterminate, so we cannot assume that
717 Media changed / media change requested error
720 Address error
721 This is indicated by IDNF bit in the ERROR register. Report to upper
725 This can be invalid command or parameter indicated by ABRT ERROR bit
726 or some other error condition. Note that ABRT bit can indicate a lot
729 Depending on commands, not all STATUS/ERROR bits are applicable. These
745 ATAPI device CHECK CONDITION error is indicated by set CHK bit (ERR bit)
753 bus error (e.g. Sense Key 04h HARDWARE ERROR && ASC/ASCQ 47h/00h SCSI
754 PARITY ERROR). In such cases, the error should be considered as an ATA
755 bus error and handled according to `ATA bus error <#excatATAbusErr>`__.
757 ATA device error (NCQ)
760 NCQ command error is indicated by cleared BSY and set ERR bit during NCQ
762 and ERROR registers will contain valid values describing the error, READ
763 LOG EXT is required to clear the error condition, determine which
767 register values describing the error. With this information the failed
768 command can be handled as a normal ATA command error as in
769 `ATA/ATAPI device error (non-NCQ / non-CHECK CONDITION) <#excatDevErr>`__
775 should be handled as described in `ATA bus error <#excatATAbusErr>`__.
781 ATA bus error
784 ATA bus error means that data corruption occurred during transmission
787 - ICRC or ABRT error as described in
788 `ATA/ATAPI device error (non-NCQ / non-CHECK CONDITION) <#excatDevErr>`__.
790 - Controller-specific error completion with error information
791 indicating transmission error.
794 mechanism to determine that the timeout is due to transmission error.
799 symptoms ranging from device ICRC error to random device lockup, and,
800 for many cases, there is no way to tell if an error condition is due to
801 transmission error or not; therefore, it's necessary to employ some kind
804 likely to indicate ATA bus error.
811 PCI bus error
815 system bus). For standard BMDMA, this is indicated by Error bit in the
824 the timed out command has completed successfully or with error. This is
828 Unknown error (timeout)
838 `ATA bus error <#excatATAbusErr>`__ for more details.
850 Clearing error condition
853 Many controllers require its error registers to be cleared by error
857 during error handling.
872 Resetting during EH might be a good idea regardless of error condition
912 Although EDD does reset devices, this doesn't suit error handling as
957 error rate. This can be mitigated by lowering transmission speed.