Lines Matching +full:16 +full:- +full:bits
1 .. SPDX-License-Identifier: GPL-2.0
7 -----------------------
12 .. note:: the memory long words are little-endian ('intel format').
21 .. code-block:: none
23 ivtvctl -O min=0x02000000,max=0x020000ff
26 register space :-).
35 .. code-block:: none
37 0x00000000-0x00ffffff Encoder memory space
38 0x00000000-0x0003ffff Encode.rom
39 ???-??? MPEG buffer(s)
40 ???-??? Raw video capture buffer(s)
41 ???-??? Raw audio capture buffer(s)
42 ???-??? Display buffers (6 or 9)
44 0x01000000-0x01ffffff Decoder memory space
45 0x01000000-0x0103ffff Decode.rom
46 ???-??? MPEG buffers(s)
47 0x0114b000-0x0115afff Audio.rom (deprecated?)
49 0x02000000-0x0200ffff Register Space
55 All of these registers are 32 bits wide.
57 .. code-block:: none
59 DMA Registers 0x000-0xff:
61 0x00 - Control:
63 0x04 - DMA status:
64 1=read busy, 2=write busy, 4=read error, 8=write error, 16=link list error
65 0x08 - pci DMA pointer for read link list
66 0x0c - pci DMA pointer for write link list
67 0x10 - read/write DMA enable:
69 0x14 - always 0xffffffff, if set any lower instability occurs, 0x00 crashes
70 0x18 - ??
71 0x1c - always 0x20 or 32, smaller values slow down DMA transactions
72 0x20 - always value of 0x780a010a
73 0x24-0x3c - usually just random values???
74 0x40 - Interrupt status
75 0x44 - Write a bit here and shows up in Interrupt status 0x40
76 0x48 - Interrupt Mask
77 0x4C - always value of 0xfffdffff,
79 0x50 - always 0xffffffff
80 0x54 - always 0xffffffff (0x4c, 0x50, 0x54 seem like interrupt masks, are
83 0x60-0x7C - random values
84 0x80 - first write linked list reg, for Encoder Memory addr
85 0x84 - first write linked list reg, for pci memory addr
86 0x88 - first write linked list reg, for length of buffer in memory addr
88 0x8c-0xdc - rest of write linked list reg, 8 sets of 3 total, DMA goes here
91 0xe0 - first (and only) read linked list reg, for pci memory addr
92 0xe4 - first (and only) read linked list reg, for Decoder memory addr
93 0xe8 - first (and only) read linked list reg, for length of buffer
94 0xec-0xff - Nothing seems to be in these registers, 0xec-f4 are 0x00000000.
96 Memory locations for Encoder Buffers 0x700-0x7ff:
101 - 0x07F8: Encoder SDRAM refresh
102 - 0x07FC: Encoder SDRAM pre-charge
104 Memory locations for Decoder Buffers 0x800-0x8ff:
109 - 0x08F8: Decoder SDRAM refresh
110 - 0x08FC: Decoder SDRAM pre-charge
114 - 0x2800: Video Display Module control
115 - 0x2D00: AO (audio output?) control
116 - 0x2D24: Bytes Flushed
117 - 0x7000: LSB I2C write clock bit (inverted)
118 - 0x7004: LSB I2C write data bit (inverted)
119 - 0x7008: LSB I2C read clock bit
120 - 0x700c: LSB I2C read data bit
121 - 0x9008: GPIO get input state
122 - 0x900c: GPIO set output state
123 - 0x9020: GPIO direction (Bit7 (GPIO 0..7) - 0:input, 1:output)
124 - 0x9050: SPU control
125 - 0x9054: Reset HW blocks
126 - 0x9058: VPU control
127 - 0xA018: Bit6: interrupt pending?
128 - 0xA064: APU command
134 The definition of the bits in the interrupt status register 0x0040, and the
138 - bit 31 Encoder Start Capture
139 - bit 30 Encoder EOS
140 - bit 29 Encoder VBI capture
141 - bit 28 Encoder Video Input Module reset event
142 - bit 27 Encoder DMA complete
143 - bit 24 Decoder audio mode change detection event (through event notification)
144 - bit 22 Decoder data request
145 - bit 20 Decoder DMA complete
146 - bit 19 Decoder VBI re-insertion
147 - bit 18 Decoder DMA err (linked-list bad)
150 ---------------------
152 - Encoder API post(?)
153 - Decoder API post(?)
154 - Decoder VTRACE event
158 ---------------------------
170 - Each firmware image is 256k bytes.
171 - The 1st 32-bit word of the Encoder image is 0x0000da7
172 - The 1st 32-bit word of the Decoder image is 0x00003a7
173 - The 2nd 32-bit word of both images is 0xaa55bb66
178 - Issue the FWapi command to stop the encoder if it is running. Wait for the
180 - Issue the FWapi command to stop the decoder if it is running. Wait for the
182 - Issue the I2C command to the digitizer to stop emitting VSYNC events.
183 - Issue the FWapi command to halt the encoder's firmware.
184 - Sleep for 10ms.
185 - Issue the FWapi command to halt the decoder's firmware.
186 - Sleep for 10ms.
187 - Write 0x00000000 to register 0x2800 to stop the Video Display Module.
188 - Write 0x00000005 to register 0x2D00 to stop the AO (audio output?).
189 - Write 0x00000000 to register 0xA064 to ping? the APU.
190 - Write 0xFFFFFFFE to register 0x9058 to stop the VPU.
191 - Write 0xFFFFFFFF to register 0x9054 to reset the HW blocks.
192 - Write 0x00000001 to register 0x9050 to stop the SPU.
193 - Sleep for 10ms.
194 - Write 0x0000001A to register 0x07FC to init the Encoder SDRAM's pre-charge.
195 - Write 0x80000640 to register 0x07F8 to init the Encoder SDRAM's refresh to 1us.
196 - Write 0x0000001A to register 0x08FC to init the Decoder SDRAM's pre-charge.
197 - Write 0x80000640 to register 0x08F8 to init the Decoder SDRAM's refresh to 1us.
198 - Sleep for 512ms. (600ms is recommended)
199 - Transfer the encoder's firmware image to offset 0 in Encoder memory space.
200 - Transfer the decoder's firmware image to offset 0 in Decoder memory space.
201 - Use a read-modify-write operation to Clear bit 0 of register 0x9050 to
202 re-enable the SPU.
203 - Sleep for 1 second.
204 - Use a read-modify-write operation to Clear bits 3 and 0 of register 0x9058
205 to re-enable the VPU.
206 - Sleep for 1 second.
207 - Issue status API commands to both firmware images to verify.
211 ----------------------------
214 mailboxes are basically a fixed length array that serves as the call-stack.
217 for a 16 byte signature. That signature will be located on a 256-byte boundary.
221 .. code-block:: none
226 The firmware implements 20 mailboxes of 20 32-bit words. The first 10 are
237 4-19 Parameter/Result
252 The command is a 32-bit enumerator. The API specifics may be found in this
255 The return value is a 32-bit enumerator. Only two values are currently defined:
257 - 0=success
258 - -1=command undefined.
260 There are 16 parameters/results 32-bit fields. The driver populates these fields
281 an interrupt. Only the 16 Results fields are used, the Flags, Command, Return
286 ----------------------------
328 1=16bit RGB 5:6:5
329 2=16bit ARGB 1:5:5:5
330 3=16bit ARGB 1:4:4:4
348 - 0=8bit index
349 - 1=16bit RGB 5:6:5
350 - 2=16bit ARGB 1:5:5:5
351 - 3=16bit ARGB 1:4:4:4
352 - 4=32bit ARGB 8:8:8:8
369 - Bit 0 0=off, 1=on
370 - Bits 1:2 alpha control
371 - Bits 3:5 pixel format
548 bits 0:7 global alpha
570 global alpha (8 bits)
648 .. code-block:: none
673 - '01' source_alpha
674 - '10' destination_alpha
675 - '11' source_alpha*destination_alpha+1
681 .. code-block:: none
689 (255 - source_alpha)*destination_pixel)/256
694 output_pixel = ((255 - destination_alpha)*source_pixel +
961 --------------------------------
992 - 0=MPEG
993 - 1=Raw
994 - 2=Raw passthrough
995 - 3=VBI
1003 - Bit 0 when set, captures YUV
1004 - Bit 1 when set, captures PCM audio
1005 - Bit 2 when set, captures VBI (same as param[0]=3)
1006 - Bit 3 when set, the capture destination is the decoder
1008 - Bit 4 when set, the capture destination is the host
1027 - 0=stop at end of GOP (generates IRQ)
1028 - 1=stop immediate (no IRQ)
1106 - 0=30fps
1107 - 1=25fps
1151 bitrate in bits per second
1156 peak bitrate in bits per second, divided by 400
1161 Mux bitrate in bits per second, divided by 400. May be 0 (default).
1199 For example: IBBPBBPBBPBB --> GOP size: 12, number of B frames: 2+1 = 3
1203 GOP size must be a multiple of (B-frames + 1).
1221 - '0000' forbidden
1222 - '0001' 1:1 square
1223 - '0010' 4:3
1224 - '0011' 16:9
1225 - '0100' 2.21:1
1226 - '0101' to '1111' reserved
1251 - 0=Disabled
1252 - 1=Horizontal
1253 - 2=Vertical
1254 - 3=Horiz/Vert
1255 - 4=Diagonal
1333 - 0=Off
1334 - 1=1D Horizontal
1335 - 2=1D Vertical
1336 - 3=2D H/V Separable (default)
1337 - 4=2D Symmetric non-separable
1344 - 0=Off
1345 - 1=1D Horizontal (default)
1362 - Bits 0:4 line number
1363 - Bit 31 0=top_field, 1=bottom_field
1364 - Bits 0:31 all set specifies "all lines"
1410 - 0=Program stream
1411 - 1=Transport stream
1412 - 2=MPEG1 stream
1413 - 3=PES A/V stream
1414 - 5=PES Video stream
1415 - 7=PES Audio stream
1416 - 10=DVD stream
1417 - 11=VCD stream
1418 - 12=SVCD stream
1419 - 13=DVD_S1 stream
1420 - 14=DVD_S2 stream
1434 (pvrusb and cx88-blackbird).
1439 - 0=Memory (default)
1440 - 1=Streaming
1441 - 2=Serial
1465 bits 2:3 which ISO docs define as:
1467 - '11' Layer I
1468 - '10' Layer II
1469 - '01' Layer III
1470 - '00' Undefined
1481 .. code-block:: none
1493 ------+-------------+------------
1513 and mode are allowed. See ISO11172-3 3-Annex B,
1514 Table 3-B.2
1528 '00' subbands 4-31 in intensity_stereo, bound==4
1529 '01' subbands 8-31 in intensity_stereo, bound==8
1530 '10' subbands 12-31 in intensity_stereo, bound==12
1531 '11' subbands 16-31 in intensity_stereo, bound==16
1547 16 Generation:
1580 - Bits 0:15 build
1581 - Bits 16:23 minor
1582 - Bits 24:31 major
1599 - 0=Open
1600 - 1=Closed
1641 .. code-block:: c
1647 u32 mask1; // Bits 0-2 are the type mask:
1666 - 0=No index capture
1667 - 1=I frames
1668 - 3=I,P frames
1669 - 7=I,P,B frames
1705 .. code-block:: none
1827 Status bits:
1828 - 0 read completed
1829 - 1 write completed
1830 - 2 DMA read error
1831 - 3 DMA write error
1832 - 4 Scatter-Gather array error
1842 Presentation Time Stamp bits 0..31
1920 - 0=Pause encoding
1921 - 1=Continue encoding
1951 - 0=Stream is not copyrighted
1952 - 1=Stream is copyrighted
1985 Mailbox slot, -1 if no mailbox required.
2004 - 0x00EF for SAA7114
2005 - 0x00F0 for SAA7115
2006 - 0x0105 for Micronas
2012 - 0x00EF for SAA7114
2013 - 0x00F0 for SAA7115
2014 - 0x0106 for Micronas
2031 - 0=extension & user data
2032 - 1=private packet with stream ID 0xBD
2107 .. code-block:: none
2113 16:23 U chrominance information
2131 - 0=audio not muted
2132 - 1=audio muted (produces silent mpeg audio stream)
2171 .. code-block:: none
2202 --------------------------------
2290 - Smooth: host transfers entire stream and firmware drops unused
2292 - Coarse: host drops frames based on indexing as required to achieve
2298 .. code-block:: none
2330 .. code-block:: none
2520 Enum: 16/0x10
2548 - Bits 0:15 build
2549 - Bits 16:23 minor
2550 - Bits 24:31 major
2589 Video PTS bits 0:31 by display order
2599 SCR bits 0:31 by display order
2622 0=Stereo, 1=Left, 2=Right, 3=Mono, 4=Swap, -1=Unchanged
2628 0=Stereo, 1=Left, 2=Right, 3=Mono, 4=Swap, -1=Unchanged
2647 - 0=Audio mode change between mono, (joint) stereo and dual channel.
2648 - 3=Decoder started
2649 - 4=Unknown: goes off 10-15 times per second while decoding.
2650 - 5=Some sync event: goes off once per frame.
2665 Mailbox slot, -1 if no mailbox required.
2763 PVR350 Video decoder registers 0x02002800 -> 0x02002B00
2764 -------------------------------------------------------
2787 .. code-block:: none
2789 --------------------------------------------------------------------------------
2795 --------------------------------------------------------------------------------
2797 bits 0:31
2799 ---------------
2801 bits 0:31
2803 ---------------
2805 bits 0:31
2807 ---------------
2809 bits 0:31
2811 ---------------
2813 bits 0:31
2815 ---------------
2817 bits 0:31
2825 To correctly program set the filter, this whole procedure must be done 16
2826 times. The actual register contents are copied from a lookup-table in the
2829 --------------------------------------------------------------------------------
2831 bits 0:31
2833 ---------------
2835 bits 0:31
2837 ---------------
2839 bits 0:31
2841 ---------------
2843 bits 0:31
2845 ---------------
2847 bits 0:31
2849 ---------------
2851 bits 0:31
2858 --------------------------------------------------------------------------------
2860 bits 0:15
2863 bits 16:31
2865 ---------------
2867 bits 0:15
2870 bits 16:31
2877 --------------------------------------------------------------------------------
2880 bits 0:31
2883 ---------------
2885 bits 0:31
2886 Decoder ?? unknown - horizontal scaling
2888 ---------------
2890 bits 0:31
2893 ---------------
2895 bits 0:31
2896 Decoder ?? unknown - horizontal scaling
2898 ---------------
2900 bits 0:31
2901 Decoder ?? unknown - Y plane
2903 ---------------
2905 bits 0:31
2906 Decoder ?? unknown - UV plane
2908 ---------------
2910 bits 0:31
2912 ---------------
2914 bits 0:31
2917 ---------------
2919 bits 0:31
2922 ---------------
2924 bits 0:31
2927 ---------------
2929 bits 0:31
2932 ---------------
2934 bits 0:31
2957 --------------------------------------------------------------------------------
2959 bits 0:15
2962 bits 15:31
2968 --------------------------------------------------------------------------------
2970 bits 0:15
2973 bits 16:31
2980 --------------------------------------------------------------------------------
2982 bits 0:1
2988 bits 4:5
2999 bit 16
3004 --------------------------------------------------------------------------------
3019 bits 3:4
3026 --------------------------------------------------------------------------------
3028 bits 0:10
3034 bits 11:31
3039 --------------------------------------------------------------------------------
3040 2880 -------- ?? unknown
3041 2884 -------- ?? unknown
3042 --------------------------------------------------------------------------------
3057 --------------------------------------------------------------------------------
3059 bits 0:15
3064 bits 16:31
3066 Same as bits 0:15
3068 --------------------------------------------------------------------------------
3070 bits 0:11
3079 --------------------------------------------------------------------------------
3081 bits 0:23
3086 --------------------------------------------------------------------------------
3088 bits 0:23
3113 --------------------------------------------------------------------------------
3115 bits 0:15
3118 bits 16:31
3124 --------------------------------------------------------------------------------
3126 bits 0:15
3129 bits 16:31
3135 --------------------------------------------------------------------------------
3137 bits 0:11
3140 Has a range of 0x770->0x7FF. With the exception of 0, any value outside of
3142 --------------------------------------------------------------------------------
3144 bits 0:15
3147 bits 16:31
3153 --------------------------------------------------------------------------------
3154 28AC -------- ?? unknown
3157 28BC -------- ?? unknown
3158 --------------------------------------------------------------------------------
3165 bits 16:31
3169 --------------------------------------------------------------------------------
3170 28C4 -------- ?? unknown
3173 28F8 -------- ?? unknown
3174 --------------------------------------------------------------------------------
3180 --------------------------------------------------------------------------------
3182 bits 0:31
3184 ---------------
3186 bits 0:31
3188 ---------------
3190 bits 0:31
3198 repeated 16 times to fully program the filter.
3199 --------------------------------------------------------------------------------
3201 bits 0:31
3203 ---------------
3205 bits 0:31
3207 ---------------
3209 bits 0:31
3214 --------------------------------------------------------------------------------
3216 bits 0:15
3219 bits 16:31
3221 ---------------
3223 bits 0:15
3226 bits 16:31
3234 --------------------------------------------------------------------------------
3236 bits 0:31
3239 ---------------
3241 bits 0:31
3244 ---------------
3246 bits 0:31
3250 ---------------
3252 bits 0:31
3255 ---------------
3257 bits 0:31
3259 ---------------
3261 bits 0:31
3262 Decoder ?? unknown - Y vertical scaling
3263 ---------------
3265 bits 0:31
3268 ---------------
3270 bits 0:31
3271 Decoder ?? unknown - Y vertical scaling
3272 ---------------
3274 bits 0:31
3278 ---------------
3280 bits 0:31
3281 Decoder ?? unknown - UV vertical scaling
3282 ---------------
3284 bits 0:31
3287 ---------------
3289 bits 0:31
3290 Decoder ?? unknown - UV vertical scaling
3309 --------------------------------------------------------------------------------
3311 bits 0:15
3314 bits 16:31
3316 --------------------------------------------------------------------------------
3318 bits 0:15
3321 bits 16:31
3323 --------------------------------------------------------------------------------
3325 bits 0:15
3328 bits 16:31
3330 --------------------------------------------------------------------------------
3332 bits 0:15
3335 bits 16:31
3337 --------------------------------------------------------------------------------
3339 bits 0:15
3342 bits 16:31
3344 --------------------------------------------------------------------------------
3346 bits 0:15
3349 bits 16:31
3354 --------------------------------------------------------------------------------
3356 bits 0:15
3359 bits 16:31
3364 --------------------------------------------------------------------------------
3366 bits 0:1
3372 bits 8:9
3377 --------------------------------------------------------------------------------
3384 bit 16
3389 --------------------------------------------------------------------------------
3390 2974 -------- ?? unknown
3393 29EF -------- ?? unknown
3394 --------------------------------------------------------------------------------
3396 bits 0:2
3399 001 = 16 bit (565)
3404 bits 4:5
3407 10 = 16 bit
3434 bits 16:31
3438 When the bits-per-pixel is set to 8, the colour mode is ignored and
3439 assumed to be 8 bit indexed. For 16 & 32 bits-per-pixel the colour depth
3443 select 16bpp with a 32 bit colour mode. This results in the pixel width
3448 colour key is always 16 bits wide. The colour to key on is set in Reg 2A18.
3451 bit indexed, local alpha is a per-pixel 256 step transparency, with 0 being
3452 transparent and 255 being solid. For the 16bpp modes 555 & 444, the unused
3454 fully transparent. There is no local alpha support for 16bit 565.
3460 --------------------------------------------------------------------------------
3462 bits 0:15
3465 bits 16:31
3467 ---------------
3469 bits 0:15
3472 bits 16:31
3480 --------------------------------------------------------------------------------
3482 bits 0:31
3487 --------------------------------------------------------------------------------
3489 bits 0:11
3494 --------------------------------------------------------------------------------
3496 bits 0:15
3499 bits 16:32
3502 --------------------------------------------------------------------------------
3504 bits 0:31
3508 --------------------------------------------------------------------------------
3510 bits 0:7
3513 Contains the global alpha value (equiv ivtvfbctl --alpha XX)
3514 --------------------------------------------------------------------------------
3515 2A20 -------- ?? unknown
3518 2A2C -------- ?? unknown
3519 --------------------------------------------------------------------------------
3521 bits 0:7
3523 ---------------
3525 bits 0:31
3530 so the index range is 0x00-0xFF
3531 --------------------------------------------------------------------------------
3532 2A38 -------- ?? unknown
3533 2A3C -------- ?? unknown
3534 --------------------------------------------------------------------------------
3536 bits 0:31
3540 --------------------------------------------------------------------------------
3542 bits 0:31
3546 --------------------------------------------------------------------------------
3548 bits 0:31
3552 --------------------------------------------------------------------------------
3554 bits 0:31
3558 --------------------------------------------------------------------------------
3560 bits 0:31
3564 --------------------------------------------------------------------------------
3566 bits 0:31
3570 --------------------------------------------------------------------------------
3571 2A58 -------- ?? unknown
3574 2AFC -------- ?? unknown
3575 --------------------------------------------------------------------------------
3582 bits 1:4
3585 --------------------------------------------------------------------------------
3588 ----------------------
3603 Therefore, it also supports a technique called "scatter-gather". The card can
3611 urged to choose a smaller block size and learn the scatter-gather technique.
3615 Note: the hardware expects little-endian data ('intel format').
3623 - The card raises the Encoder interrupt.
3624 - The driver reads the transfer type, offset and size from Mailbox #10.
3625 - The driver constructs the scatter-gather array from enough free dma buffers
3627 - The driver schedules the DMA transfer via the ScheduleDMAtoHost API call.
3628 - The card raises the DMA Complete interrupt.
3629 - The driver checks the DMA status register for any errors.
3630 - The driver post-processes the newly transferred buffers.
3640 - Name: Mailbox #10
3641 - Results[0]: Type: 0: MPEG.
3642 - Results[1]: Offset: The position relative to the card's memory space.
3643 - Results[2]: Size: The exact number of bytes to transfer.
3649 Scatter-Gather Array
3652 The scatter-gather array is a contiguously allocated block of memory that
3653 tells the card the source and destination of each data-block to transfer.
3657 Each S-G array element is a struct of three 32-bit words. The first word is
3659 entire 32 bits. The lowest 18 bits of the third word is the transfer byte
3660 count. The high-bit of the third word is the "last" flag. The last-flag tells
3671 - 32-bit Source Address
3672 - 32-bit Destination Address
3673 - 14-bit reserved (high bit is the last flag)
3674 - 18-bit byte count
3681 - bit 0: read completed
3682 - bit 1: write completed
3683 - bit 2: DMA read error
3684 - bit 3: DMA write error
3685 - bit 4: Scatter-Gather array error