Lines Matching +full:frame +full:- +full:buffer
1 .. SPDX-License-Identifier: GPL-2.0
3 PXA-Camera Host Driver
9 -----------
18 ---------------------
22 When a buffer is queued, start_streaming is called and the QCI starts.
27 smoothly captured one frame after the other.
29 Once a buffer is filled in the QCI interface, it is marked as "DONE" and
33 Once the last buffer is filled in, the QCI interface stops.
37 .. code-block:: none
39 +----+ +---+ +----+
42 +-----------+ +------------------------+
44 +-----------+ Q +------------------------+
45 +-> | QCI: stop | ------------------> | QCI: run | <------------+
47 | +-----------+ +-----> +------------------------+ |
49 | / +---+ +----+ | |
52 | +--------------------+ +----------------------+ |
54 | +--------------------+ +----------------------+ |
55 | | QCI: run | +-----> | QCI: run | <-+ |
57 | +--------------------+ / +----------------------+ | Other |
62 | +----------------------+ +----------------------+ | |
64 | +----------------------+ +----------------------+ | |
65 +-- | QCI: run | | QCI: run | --+ |
67 +----------------------+ +----------------------+ |
71 +--------------------+ / +----------------------+ |
72 | Frame completed | / | Frame overran | |
73 +--------------------+ <-----+ +----------------------+ restart frame |
74 | QCI: run | | QCI: stop | --------------+
76 +--------------------+ +----------------------+
78 Legend: - each box is a FSM state
79 - each arrow is the condition to transition to another state
80 - an arrow with a comment is a mandatory transition (no condition)
81 - arrow "Q" means : a buffer was enqueued
82 - arrow "DQ" means : a buffer was dequeued
83 - "QCI: stop" means the QCI interface is not enabled
84 - "DMA: stop" means all 3 DMA channels are stopped
85 - "DMA: run" means at least 1 DMA channel is still running
88 ---------
91 - first buffer queued for capture
92 Once a first buffer is queued for capture, the QCI is started, but data
93 transfer is not started. On "End Of Frame" interrupt, the irq handler
95 - capture of one videobuffer
98 - finishing one videobuffer
102 - finishing the last videobuffer
105 b) DMA prepared buffer will have this structure
107 .. code-block:: none
109 +------------+-----+---------------+-----------------+
110 | desc-sg[0] | ... | desc-sg[last] | finisher/linker |
111 +------------+-----+---------------+-----------------+
113 This structure is pointed by dma->sg_cpu.
116 - desc-sg[i]: i-th descriptor, transferring the i-th sg
117 element to the video buffer scatter gather
118 - finisher: has ddadr=DADDR_STOP, dcmd=ENDIRQEN
119 - linker: has ddadr= desc-sg[0] of next video buffer, dcmd=0
121 For the next schema, let's assume d0=desc-sg[0] .. dN=desc-sg[N],
125 .. code-block:: none
128 +---------+----+---+ +----+----+----+---+
130 +---------+----+-|-+ ^----+----+----+---+
132 +----+
136 .. code-block:: none
139 +---------+----+---+ +----+----+----+---+ +----+----+----+---+
141 +---------+----+-|-+ ^----+----+----+-|-+ ^----+----+----+---+
143 +----+ +----+
152 - DMA chain is Videobuffer1 + Videobuffer2
153 - pxa_videobuf_queue() is called to queue Videobuffer3
154 - DMA controller finishes Videobuffer2, and DMA stops
156 .. code-block:: none
160 +---------+----+---+ +----+----+----+---+
162 +---------+----+-|-+ ^----+----+----+-^-+
164 +----+ +-- DMA DDADR loads DDADR_STOP
166 - pxa_dma_add_tail_buf() is called, the Videobuffer2 "finisher" is
168 - pxa_videobuf_queue() finishes
169 - the DMA irq handler is called, which terminates Videobuffer2
170 - Videobuffer3 capture is not scheduled on DMA chain (as it stopped !!!)
172 .. code-block:: none
175 +---------+----+---+ +----+----+----+---+ +----+----+----+---+
177 +---------+----+-|-+ ^----+----+----+-|-+ ^----+----+----+---+
179 +----+ +----+
183 - pxa_camera_check_link_miss() is called
184 This checks if the DMA is finished and a buffer is still on the
185 pcdev->capture list. If that's the case, the capture will be restarted,
187 - the DMA irq handler finishes
193 when the DMA will finish the buffer, and pxa_camera_check_link_miss() will