Lines Matching +full:send +full:- +full:not +full:- +full:empty
10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
21 -- Pipe attributes
22 -- Host never reads from the FPGA
23 -- Channels, pipes, and the message channel
24 -- Data streaming
25 -- Data granularity
26 -- Probing
27 -- Buffer allocation
28 -- The "nonempty" message (supporting poll)
35 ----------
45 (hence not justifying the development of an ASIC).
49 focus on their specific project, and not reinvent the wheel over and over
50 again, pre-designed building blocks, IP cores, are often used. These are the
59 low-level bus protocol and the somewhat higher-level interface with the host
61 function is a well-known one (e.g. a video adapter card, or a NIC), it can
63 A special driver is then written to present the FPGA as a well-known interface
67 It's however common that the desired data communication doesn't fit any well-
73 interface logic for the FPGA, and write a simple ad-hoc driver for the kernel.
76 -----------------
79 elementary data transport between an FPGA and the host, providing pipe-like
80 data streams with a straightforward user interface. It's intended as a low-
81 effort solution for mixed FPGA-host projects, for which it makes sense to
82 have the project-specific part of the driver running in a user-space program.
93 the data. This is contrary to a common method of communicating through fixed-
104 The data structure just mentioned should not be confused with PCI's
111 --------------
117 corresponds to the hardware FIFO you want to send data or receive data from,
125 possibly pressing CTRL-C as some stage, even though the xillybus_* pipes have
126 the capability to send an EOF (but may not use it).
130 * Supporting non-blocking I/O (by setting O_NONBLOCK on open() ).
142 ---------------
170 --------------
184 ------------------------
194 which execute the DMA-related operations on the bus.
197 ---------------
204 * is_writebuf: The pipe's direction. A non-zero value means it's an FPGA to
212 * allowpartial: A non-zero value means that a read() or write() (whichever
214 choice is a non-zero value, to match standard UNIX behavior.
216 * synchronous: A non-zero value means that the pipe is synchronous. See
223 * exclusive_open: A non-zero value forces exclusive opening of the associated
227 * seekable: A non-zero value indicates that the pipe is seekable. See
230 * supports_nonempty: A non-zero value (which is typical) indicates that the
231 hardware will send the messages that are necessary to support select() and
235 ------------------------------
253 This mechanism is used on non-PCIe buses as well for the sake of uniformity.
257 ----------------------------------------
261 and pipes is necessary only because of channel 0, which is used for interrupt-
265 --------------
267 Even though a non-segmented data stream is presented to the user at both
279 This is not good enough for creating a TCP/IP-like stream: If the data flow
281 that the partial data in buffer will arrive anyhow, despite the buffer not
283 XILLYMSG_OPCODE_RELEASEBUF message, through which the FPGA informs not just
300 and yet enjoy a stream-like interface.
307 ----------------
314 will also work, but the driver can't send partially completed words to the
325 -------
342 -----------------
346 it must not cross a 4kB boundary. Otherwise, it must be 4kB aligned. The
367 ----------------------------------------
371 buffer with some data, but not submitted that buffer. If the host waited for
374 host has not received any notification about this. This is solved with
376 completely empty to containing some data.
379 be configured not to send them for a slight reduction of bandwidth.