Lines Matching +full:hardware +full:- +full:accelerated
7 - Enno Luebbers <enno.luebbers@intel.com>
8 - Xiao Guangrong <guangrong.xiao@linux.intel.com>
9 - Wu Hao <hao.wu@intel.com>
10 - Xu Yilun <yilun.xu@intel.com>
13 this framework) hides the very details of low layer hardware and provides
25 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
29 +----------+ +-->+----------+ +-->+----------+ +-->+----------+
32 +----------+ | | Feature | | | Feature | | | Feature |
33 | Next_DFH |--+ +----------+ | +----------+ | +----------+
34 +----------+ | Next_DFH |--+ | Next_DFH |--+ | Next_DFH |--> NULL
35 | ID | +----------+ +----------+ +----------+
36 +----------+ | ID | | ID | | ID |
37 | Next_AFU |--+ +----------+ +----------+ +----------+
38 +----------+ | | Feature | | Feature | | Feature |
41 | Set | | +----------+ +----------+ +----------+
42 +----------+ | Header
43 +-->+----------+
46 +----------+
47 | Next_DFH |--> NULL
48 +----------+
50 +----------+
54 +----------+
60 Accelerated Function Unit (AFU) represents an FPGA programmable region and
78 Device Feature Header - Version 0
81 All multi-byte quantities in DFHv0 are little-endian.
84 +-----------------------------------------------------------------------+
86 +-----------------------------------------------------------------------+
88 +-----------------------------------------------------------------------+
90 +-----------------------------------------------------------------------+
92 - Offset 0x00
94 * Type - The type of DFH (e.g. FME, AFU, or private feature).
95 * DFH VER - The version of the DFH.
96 * Rsvd - Currently unused.
97 * EOL - Set if the DFH is the end of the Device Feature List (DFL).
98 * Next - The offset in bytes of the next DFH in the DFL from the DFH start,
101 * REV - The revision of the feature associated with this header.
102 * ID - The feature ID if Type is private feature.
104 - Offset 0x08
106 * GUID_L - Least significant 64 bits of a 128-bit Globally Unique Identifier
109 - Offset 0x10
111 * GUID_H - Most significant 64 bits of a 128-bit Globally Unique Identifier
115 Device Feature Header - Version 1
124 All multi-byte quantities in DFHv1 are little-endian.
127 +-----------------------------------------------------------------------+
129 +-----------------------------------------------------------------------+
131 +-----------------------------------------------------------------------+
133 +-----------------------------------------------------------------------+
135 +-----------------------------------------------------------------------+
137 +-----------------------------------------------------------------------+
139 +-----------------------------------------------------------------------+
141 +-----------------------------------------------------------------------+
145 +-----------------------------------------------------------------------+
147 +-----------------------------------------------------------------------+
149 +-----------------------------------------------------------------------+
151 - Offset 0x00
153 * Type - The type of DFH (e.g. FME, AFU, or private feature).
154 * DFH VER - The version of the DFH.
155 * Rsvd - Currently unused.
156 * EOL - Set if the DFH is the end of the Device Feature List (DFL).
157 * Next - The offset in bytes of the next DFH in the DFL from the DFH start,
160 * REV - The revision of the feature associated with this header.
161 * ID - The feature ID if Type is private feature.
163 - Offset 0x08
165 * GUID_L - Least significant 64 bits of a 128-bit Globally Unique Identifier.
167 - Offset 0x10
169 * GUID_H - Most significant 64 bits of a 128-bit Globally Unique Identifier.
171 - Offset 0x18
173 * Reg Address/Offset - If Rel bit is set, then the value is the high 63 bits
174 of a 16-bit aligned absolute address of the feature's registers. Otherwise
177 - Offset 0x20
179 * Reg Size - Size of feature's register set in bytes.
180 * Params - Set if DFH has a list of parameter blocks.
181 * Group - Id of group if feature is part of a group.
182 * Instance - Id of feature instance within a group.
184 - Offset 0x28 if feature has parameters
186 * Next - Offset to the next parameter block in 8 byte words. If EOP set,
188 * Param Version - Version of Param ID.
189 * Param ID - ID of parameter.
191 - Offset 0x30
193 * Parameter Data - Parameter data whose size and format is defined by
197 FIU - FME (FPGA Management Engine)
202 User-space applications can acquire exclusive access to the FME using open(),
207 - Get driver API version (DFL_FPGA_GET_API_VERSION)
208 - Check for extensions (DFL_FPGA_CHECK_EXTENSION)
209 - Program bitstream (DFL_FPGA_FME_PORT_PR)
210 - Assign port to PF (DFL_FPGA_FME_PORT_ASSIGN)
211 - Release port from PF (DFL_FPGA_FME_PORT_RELEASE)
212 - Get number of irqs of FME global error (DFL_FPGA_FME_ERR_GET_IRQ_NUM)
213 - Set interrupt trigger for FME error (DFL_FPGA_FME_ERR_SET_IRQ)
216 (/sys/class/fpga_region/regionX/dfl-fme.n/):
231 hardware, and clear the logged errors.
249 FIU - PORT
260 used for accelerator-specific control registers.
262 User-space applications can acquire exclusive access to an AFU attached to a
267 - Get driver API version (DFL_FPGA_GET_API_VERSION)
268 - Check for extensions (DFL_FPGA_CHECK_EXTENSION)
269 - Get port info (DFL_FPGA_PORT_GET_INFO)
270 - Get MMIO region info (DFL_FPGA_PORT_GET_REGION_INFO)
271 - Map DMA buffer (DFL_FPGA_PORT_DMA_MAP)
272 - Unmap DMA buffer (DFL_FPGA_PORT_DMA_UNMAP)
273 - Reset AFU (DFL_FPGA_PORT_RESET)
274 - Get number of irqs of port error (DFL_FPGA_PORT_ERR_GET_IRQ_NUM)
275 - Set interrupt trigger for port error (DFL_FPGA_PORT_ERR_SET_IRQ)
276 - Get number of irqs of UINT (DFL_FPGA_PORT_UINT_GET_IRQ_NUM)
277 - Set interrupt trigger for UINT (DFL_FPGA_PORT_UINT_SET_IRQ)
285 User-space applications can also mmap() accelerator MMIO regions.
288 (/sys/class/fpga_region/<regionX>/<dfl-port.m>/):
295 detected by the hardware, and clear the logged errors.
303 +----------+ +--------+ +--------+ +--------+
306 +----------+ +--------+ +--------+ +--------+
307 +-----------------------+
310 +-----------------------+
311 ------------------------------------------------------------------
312 +----------------------------+
315 +----------------------------+
316 +------------------------+
317 | FPGA Hardware Device |
318 +------------------------+
327 The FPGA DFL Device could be different hardware, e.g. PCIe device, platform
348 Similar to the FME driver, the FPGA Accelerated Function Unit (AFU) driver is
372 FPGA virtualization - PCIe SRIOV
383 +-------------------------------+ +-------------+
385 +-------------------------------+ +-------------+
388 +-----|------------|---------|--------------|-------+
390 | +-----+ +-------+ +-------+ +-------+ |
392 | +-----+ +-------+ +-------+ +-------+ |
395 | +-------+ +------+ +-------+ |
397 | +-------+ +------+ +-------+ |
400 +---------------------------------------------------+
412 +-------++------++------+ |
416 +-------++------++------+ |
417 +-----------------------+ +--------+ | +--------+
420 +-----------------------+ +--------+ | +--------+
421 +-----------------------+ | +-----------------------+
424 +-----------------------+ | +-----------------------+
425 +------------------+ | +------------------+
427 +------------------+ Host | Machine +------------------+
428 -------------------------------------- | ------------------------------
429 +---------------+ | +---------------+
431 +---------------+ | +---------------+
483 (e.g. "dfl-port.n" or "dfl-fme.m" is found), then it's the base
488 /sys/class/fpga_region/region0/dfl-fme.0
489 /sys/class/fpga_region/region0/dfl-port.0
490 /sys/class/fpga_region/region0/dfl-port.1
493 /sys/class/fpga_region/region3/dfl-fme.1
494 /sys/class/fpga_region/region3/dfl-port.2
495 /sys/class/fpga_region/region3/dfl-port.3
500 /sys/class/fpga_region/<regionX>/<dfl-fme.n>/
501 /sys/class/fpga_region/<regionX>/<dfl-port.m>/
508 /sys/class/fpga_region/<regionX>/<dfl-fme.n>/dev
509 /sys/class/fpga_region/<regionX>/<dfl-port.n>/dev
515 supports several independent, system-wide, device counter sets in hardware to
521 Different FPGA devices may have different counter sets, depending on hardware
523 use "perf list" to check which perf events are supported by target hardware.
551 $# perf stat -a -e dfl_fme0/fab_mmio_read/ <command>
553 $# perf stat -a -e dfl_fme0/event=0x06,evtype=0x02,portid=0xff/ <command>
555 $# perf stat -a -e dfl_fme0/config=0xff2006/ <command>
563 $# perf stat -a -e dfl_fme0/fab_port_mmio_read,portid=0x0/ <command>
565 $# perf stat -a -e dfl_fme0/event=0x06,evtype=0x02,portid=0x0/ <command>
567 $# perf stat -a -e dfl_fme0/config=0x2006/ <command>
570 events (fab_port_*) actually share one set of counters in hardware, so it can't
574 $# perf stat -e dfl_fme0/fab_mmio_read/,dfl_fme0/fab_port_mmio_write,\
586 since they are system-wide counters on FPGA device.
621 FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)
626 https://github.com/OPAE/dfl-feature-id
644 +----------------------------+
646 +----------------------------+
648 +----------------------------+
650 +----------------------------+
652 +----------------------------+
661 The purpose of an FPGA is to be reprogrammed with newly developed hardware
662 components. New hardware can instantiate a new private feature in the DFL, and
666 * Users may need to run some diagnostic test for their hardware.
668 * Some hardware is designed for specific purposes and does not fit into one of
676 has no irq in hardware. So the interrupt handling is not added in this driver.