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6 (DCN) works, we need to start with an overview of the hardware pipeline. Below
8 generic diagram, and we have variations per ASIC.
12 Based on this diagram, we can pass through each block and briefly describe
58 setup or ignored accordingly with userspace demands. For example, if we
77 From DCHUB to MPC, we have a representation called dc_plane; from MPC to OPTC,
78 we have dc_stream, and the output (DIO) is handled by dc_link. Keep in mind
100 a one-to-one mapping of the link encoder to PHY, but we can configure the DCN
123 depth format), bit-depth reduction/dithering would kick in. In OPP, we would
125 Eventually, we output data in integer format at DIO.
131 overloaded with multiple meanings, so it is important to define what we mean
132 when we say **pipeline**. In the DCN driver, we use the term **hardware
135 core treats DCN blocks as individual resources, meaning we can build a pipeline
137 In actuality, we can't connect an arbitrary block from one pipe to a block from
139 arbitrarily assigned as needed. We have this pipeline concept for trying to
158 The first thing to notice from the diagram and DTN log it is the fact that we
160 we have just a single **pipeline** where the data flows from DCHUB to DIO, as
161 we intuitively expect. Nonetheless, DCN is flexible, as mentioned before, and
162 we can split this single pipe differently, as described in the below diagram:
166 Now, if we inspect the DTN log again we can see some interesting changes::
178 From the above example, we now split the display pipeline into two vertical
179 parts of 1920x2160 (i.e., 3440x2160), and as a result, we could reduce the
212 independent of the VSync signal we use VUPDATE to signal the VSync event as it