Lines Matching +full:data +full:- +full:independent

10 .. kernel-figure:: dc_pipeline_overview.svg
16   Data Port (SDP) and DCN. This component has multiple features, such as memory
19 * **Display Pipe and Plane (DPP)**: This block provides pre-blend pixel
20   processing such as color space conversion, linearization of pixel data, tone
24   multiple planes, using global or per-pixel alpha.
38 * **Multi-Media HUB (MMHUBBUB)**: Memory controller interface for DMCUB and DWB
43   the Display Micro-Controller Unit - version B (DMCUB), which is handled via
53 pipeline is connected to the Scalable Data Port (SDP) via DCHUB; you can see
54 the SDP as the element from our Data Fabric that feeds the display pipe.
66 1. Pixel data interface (red): Represents the pixel data flow;
76 All of these components are represented by a data structure named dc_state.
84 ----------------------
100 a one-to-one mapping of the link encoder to PHY, but we can configure the DCN
102 is to change, blend and compose pixel data, while BE's job is to frame a
105 Data Flow
106 ---------
108 Initially, data is passed in from VRAM through Data Fabric (DF) in native pixel
109 formats. Such data format stays through till HUBP in DCHUB, where HUBP unpacks
113 The Converter and Cursor (CNVC) in DPP would then normalize the data
114 representation and convert them to a DCN specific floating-point format (i.e.,
115 different from the IEEE floating-point format). In the process, CNVC also
116 applies a degamma function to transform the data from non-linear to linear
117 space to relax the floating-point calculations following. Data would stay in
118 this floating-point format from DPP to OPP.
123 depth format), bit-depth reduction/dithering would kick in. In OPP, we would
125 Eventually, we output data in integer format at DIO.
128 ---------------------
142 .. kernel-figure:: pipeline_4k_no_split.svg
145 'Documentation/gpu/amdgpu/display/dc-debug.rst' for more information) since
146 this log can help us to see part of this pipeline behavior in real-time::
160 we have just a single **pipeline** where the data flows from DCHUB to DIO, as
164 .. kernel-figure:: pipeline_4k_split.svg
187 -----------
203 calculated by the Display Mode Library - DML (drivers/gpu/drm/amd/display/dc/dml)
206 The global sync signals always happen during VBlank, are independent from the
212 independent of the VSync signal we use VUPDATE to signal the VSync event as it
215 Since DCN hardware is double-buffered the DC driver is able to program the
220 .. kernel-figure:: global_sync_vblank.svg
226 updates, i.e. it allows for multiple re-configurations between VUpdate
230 .. kernel-figure:: config_example.svg