Lines Matching +full:addr +full:- +full:mode

40                 read mode.
44 Addr  (7 bits)  I2C 7 bit address. Note that this can be expanded to
62   S Addr Rd/Wr [A] P
77   S Addr Rd [A] [Data] NA P
92   S Addr Wr [A] Data [A] P
105   S Addr Wr [A] Comm [A] Sr Addr Rd [A] [Data] NA P
119   S Addr Wr [A] Comm [A] Sr Addr Rd [A] [DataLow] A [DataHigh] NA P
139   S Addr Wr [A] Comm [A] Data [A] P
153   S Addr Wr [A] Comm [A] DataLow [A] DataHigh [A] P
168   S Addr Wr [A] Comm [A] DataLow [A] DataHigh [A]
169                               Sr Addr Rd [A] [DataLow] A [DataHigh] NA P
185   S Addr Wr [A] Comm [A]
186             Sr Addr Rd [A] [Count] A [Data] A [Data] A ... A [Data] NA P
202   S Addr Wr [A] Comm [A] Count [A] Data [A] Data [A] ... [A] Data [A] P
207 SMBus Block Write - Block Read Process Call
210 SMBus Block Write - Block Read Process Call was introduced in
216   S Addr Wr [A] Comm [A] Count [A] Data [A] ...
217                               Sr Addr Rd [A] [Count] A [Data] ... A P
241   client->irq assigned to a Host Notify IRQ if no one else specified another.
251 PEC adds a CRC-8 error-checking byte to transfers using it, immediately
259 the specification. It is a higher-layer protocol which uses the
304   S Addr Wr [A] Comm [A]
305             Sr Addr Rd [A] [Data] A [Data] A ... A [Data] NA P
322   S Addr Wr [A] Comm [A] Data [A] Data [A] ... [A] Data [A] P