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4 OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface (TC6) Framework Support
29 The MAC-PHY solution integrates an IEEE Clause 4 MAC and a 10BASE-T1x PHY
32 to existing low-end microcontrollers which do not integrate a MAC
38 The MAC-PHY is specified to carry both data (Ethernet frames) and control
54 low to the MAC-PHY and ends with the deassertion of CSn high. In between
78 10BASE-T1x MAC-PHY Serial Interface Specification,
88 | | | MAC-PHY |
90 | SPI Host | | | SPI Slave | | MAC | | PHY | |
107 | MAC Driver |<--->| OPEN Alliance TC6 Framework |
121 | 10BASE-T1x MAC-PHY Device |
127 MAC Driver
132 - Initializes OA TC6 framework for the MAC-PHY.
143 - Registers mac-phy interrupt.
145 - Performs mac-phy register read/write operation using the control
146 transaction protocol specified in the OPEN Alliance 10BASE-T1x MAC-PHY
150 for Ethernet frames specified in the OPEN Alliance 10BASE-T1x MAC-PHY
153 - Forwards the received Ethernet frame from 10Base-T1x MAC-PHY to n/w
160 the MAC-PHY will be converted into multiple transmit data chunks. Each
182 even/odd transmit data chunk sequence to the MAC-PHY.
185 the MAC-PHY from conveying RX data on the MISO for the
194 If the MAC-PHY does not implement these bits, the host
199 (DV = 1) or not (DV = 0). When ‘0’, the MAC-PHY ignores the
238 The number of buffers available in the MAC-PHY to store the incoming
240 available transmit credits in the MAC-PHY can be read either from the
242 received from the MAC-PHY. The SPI host should not write more data chunks
248 chunks, the MAC-PHY interrupt is asserted to SPI host. On reception of the
253 The Ethernet frames that are typically transferred from MAC-PHY to SPI
273 HDRB (Bit 30) - Received Header Bad. When set, indicates that the MAC-PHY
278 register (see Table 12). A zero indicates that the MAC-PHY
289 pending in the MAC-PHY’s buffer for reading.
292 If not implemented, the MAC-PHY shall set these bits to
295 DV (Bit 21) - Data Valid flag. The MAC-PHY uses this bit to indicate
300 SV (Bit 20) - Start Valid flag. The MAC-PHY sets this bit when the current
314 FD (Bit 15) - Frame Drop. When set, this bit indicates that the MAC has
320 EV (Bit 14) - End Valid flag. The MAC-PHY sets this bit when the end of a
331 received Ethernet frame. The MAC-PHY shall set this bit to
337 MAC-PHY shall set this bit to zero when RTSA = 0.
348 chunks available in the MAC-PHY which is provided in the receive chunk
351 case there are valid Ethernet frames to transmit to the MAC-PHY. The
352 receive chunks available in MAC-PHY can be read either from the Buffer
357 MAC-PHY interrupt is asserted to SPI host. On reception of the first data
361 MAC-PHY Interrupt
364 The MAC-PHY interrupt is asserted when the following conditions are met.
392 HDRB (Bit 30) - Received Header Bad. When set by the MAC-PHY, indicates
394 host should always clear this bit. The MAC-PHY ignores the
424 MAC-PHY. Each control commands are composed of a 4 bytes control command
427 The MAC-PHY ignores the final 4 bytes of data from the SPI host at the end
429 from the MAC-PHY back to the SPI host to identify which register write
435 written, the address is automatically post-incremented by the MAC-PHY.
439 The MAC-PHY ignores all data from the SPI host following the control
441 command is also echoed from the MAC-PHY back to the SPI host to identify
448 MAC-PHY. Reading any unimplemented or undefined registers shall return
468 Write a single register in the MAC-PHY.
473 Writing multiple consecutive registers starting from @address in the MAC-PHY.
479 Read a single register in the MAC-PHY.
484 Reading multiple consecutive registers starting from @address in the MAC-PHY.
491 the MAC-PHY.