Lines Matching +full:loss +full:- +full:of +full:- +full:signal
8 Most network devices consist of set of registers which provide an interface
11 partner on the other side of the network connection (typically, an ethernet
18 amounts of redundant code. Also, on embedded systems with multiple (and
20 management bus, it is difficult to ensure safe use of the bus.
26 #. Increase code-reuse
27 #. Increase overall code-maintainability
37 Most network devices are connected to a PHY by means of a management bus.
39 In order to take advantage of the PAL, each bus interface needs to be
49 time, so it is safe for them to block, waiting for an interrupt to signal
57 mdiobus_register. Similarly, there's a remove function to undo all of
67 for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/")
72 The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin
73 electrical signal interface using a synchronous 125Mhz clock signal and several
77 PHY library offers different types of PHY_INTERFACE_MODE_RGMII* values to let
79 values of phy_interface_t must be understood from the perspective of the PHY
84 or the PCB traces insert the correct 1.5-2ns delay
97 * PHY devices may offer sub-nanosecond granularity in how they allow a
101 * PHY devices are typically qualified for a large range of applications
109 For cases where the PHY is not capable of providing this delay, but the
110 Ethernet MAC driver is capable of doing so, the correct phy_interface_t value
113 side delay from the perspective of the PHY device. Conversely, if the Ethernet
115 PHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays are
118 In case neither the Ethernet MAC, nor the PHY are capable of providing the
122 * Some SoCs may offer a pin pad/mux/controller capable of configuring a given
123 set of pins' strength, delays, and voltage; and it may be a suitable
130 -----------------------------------------
134 the PHY or MAC take a snapshot of these signals to translate them into logical
139 packet loss observed
165 #. The PAL serves only as a library of functions, with the network device
180 Next, you need to know the device name of the PHY connected to this device.
197 PHY-specific flags should be set in phydev->dev_flags prior to the call
201 the PHY/controller, of which the PHY needs to be aware.
208 Now just make sure that phydev->supported and phydev->advertising have any
218 PHY to connect to the network. If the MAC interrupt of your network driver
219 also handles PHY status changes, just set phydev->irq to PHY_MAC_INTERRUPT
221 driver. If you don't want to use interrupts, set phydev->irq to PHY_POLL.
232 The PHY interface mode supplied in the phy_connect() family of functions
233 defines the initial operating mode of the PHY interface. This is not
238 Some of the interface modes are described below:
246 This defines the 1000BASE-X single-lane serdes link as defined by the
247 802.3 standard section 36. The link operates at a fixed bit rate of
249 data rate of 1Gbps. Embedded in the data stream is a 16-bit control
251 remote end. This does not include "up-clocked" variants such as 2.5Gbps
255 This defines a variant of 1000BASE-X which is clocked 2.5 times as fast
256 as the 802.3 standard, giving a fixed bit rate of 3.125Gbaud.
259 This is used for Cisco SGMII, which is a modification of 1000BASE-X
260 as defined by the 802.3 standard. The SGMII link consists of a single
261 serdes lane running at a fixed bit rate of 1.25Gbaud with 10B/8B
262 encoding. The underlying data rate is 1Gbps, with the slower speeds of
263 100Mbps and 10Mbps being achieved through replication of each data symbol.
264 The 802.3 control word is re-purposed to send the negotiated speed and
266 receipt. This does not include "up-clocked" variants such as 2.5Gbps
269 Note: mismatched SGMII vs 1000BASE-X configuration on a link can
270 successfully pass data in some circumstances, but the 16-bit control
276 This is the IEEE 802.3 Clause 129 defined 5GBASE-R protocol. It is
277 identical to the 10GBASE-R protocol defined in Clause 49, with the
282 This is the IEEE 802.3 Clause 49 defined 10GBASE-R protocol used with
284 definition of this.
286 Note: 10GBASE-R is just one protocol that can be used with XFI and SFI.
288 also defines the electrical characteristics of the signals with a host
293 This is the IEEE 802.3 Clause 49 defined 10GBASE-R with Clause 73
297 Note: due to legacy usage, some 10GBASE-R usage incorrectly makes
298 use of this definition.
301 This is the IEEE 802.3 PCS Clause 107 defined 25GBASE-R protocol.
302 The PCS is identical to 10GBASE-R, i.e. 64B/66B encoded
303 running 2.5 as fast, giving a fixed bit rate of 25.78125 Gbaud.
308 rate of 125Mpbs using a 4B/5B encoding scheme, resulting in an underlying
309 data rate of 100Mpbs.
312 This defines the Cisco the Quad USGMII mode, which is the Quad variant of
314 a Packet Control Header (PCH) instead of the 7 bytes preamble to carry not
315 only the port id, but also so-called "extensions". The only documented
316 extension so-far in the specification is the inclusion of timestamps, for
317 PTP-enabled PHYs. This mode isn't compatible with QSGMII, but offers the
318 same capabilities in terms of link speed and negotiation.
321 This is 1000BASE-X as defined by IEEE 802.3 Clause 36 with Clause 73
323 contrast with the 1000BASE-X phy mode used for Clause 38 and 39 PMDs, this
331 Represents the 10G-QXGMII PHY-MAC interface as defined by the Cisco USXGMII
333 SerDes lane, each port having speeds of 2.5G / 1G / 100M / 10M achieved
344 of properly indicating advertisement and support for such features by setting
346 either before or after phy_connect() and/or as a result of implementing the
353 It is possible that the PAL's built-in state machine needs a little help to
361 Currently there are no examples of how to use this functionality, and testing
368 There's a remote chance that the PAL's built-in state machine cannot track
371 phy_prepare_link(). This will mean that phydev->state is entirely yours to
372 handle (phy_start and phy_stop toggle between some of the states, so you
376 accessed without the state-machine running, and most of these functions are
377 descended from functions which did not interact with a complex state-machine.
381 Here is a brief rundown of the functions::
416 Fills the phydev structure with up-to-date information about the current
439 many PHYs require a little hand-holding to get up-and-running.
442 ------------------
447 do all of the work.
450 --------------------
471 Each driver consists of a number of function pointers, documented
474 Of these, only config_aneg and read_status are required to be
476 preferred to use the generic phy driver's versions of these two
485 not been tested as of this writing).
493 An example of such usage is for Energy Efficient Ethernet support,
498 the Micrel driver in drivers/net/phy/ for an example of how this
512 field) and the bus identifier (contained in phydev->dev.bus_id). Both must
517 with the fixup. This function is passed a pointer to the phy_device of
526 Or using one of the two stubs, phy_register_fixup_for_uid() and
534 The stubs set one of the two matching criteria, and set the other one to
541 Call one of following function before unloading module::
551 http://standards.ieee.org/getieee802/download/802.3-2008_section2.pdf