Lines Matching +full:rockchip +full:- +full:display
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Analogix DP (Display port) core register interface driver.
31 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
33 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
35 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
37 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
45 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_stop_video()
47 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_stop_video()
61 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP); in analogix_dp_lane_swap()
69 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1); in analogix_dp_init_analog_param()
72 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2); in analogix_dp_init_analog_param()
74 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) { in analogix_dp_init_analog_param()
76 if (dp->plat_data->dev_type == RK3288_DP) in analogix_dp_init_analog_param()
79 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1); in analogix_dp_init_analog_param()
80 writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2); in analogix_dp_init_analog_param()
81 writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3); in analogix_dp_init_analog_param()
82 writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4); in analogix_dp_init_analog_param()
83 writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5); in analogix_dp_init_analog_param()
87 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3); in analogix_dp_init_analog_param()
91 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_FILTER_CTL_1); in analogix_dp_init_analog_param()
95 writel(reg, dp->reg_base + ANALOGIX_DP_TX_AMP_TUNING_CTL); in analogix_dp_init_analog_param()
101 writel(INT_POL1 | INT_POL0, dp->reg_base + ANALOGIX_DP_INT_CTL); in analogix_dp_init_interrupt()
104 writel(0xff, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); in analogix_dp_init_interrupt()
105 writel(0x4f, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_2); in analogix_dp_init_interrupt()
106 writel(0xe0, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_3); in analogix_dp_init_interrupt()
107 writel(0xe7, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); in analogix_dp_init_interrupt()
108 writel(0x63, dp->reg_base + ANALOGIX_DP_INT_STA); in analogix_dp_init_interrupt()
111 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1); in analogix_dp_init_interrupt()
112 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2); in analogix_dp_init_interrupt()
113 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3); in analogix_dp_init_interrupt()
114 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); in analogix_dp_init_interrupt()
115 writel(0x00, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); in analogix_dp_init_interrupt()
125 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) in analogix_dp_reset()
133 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); in analogix_dp_reset()
138 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); in analogix_dp_reset()
144 writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); in analogix_dp_reset()
145 writel(0x40, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); in analogix_dp_reset()
146 writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); in analogix_dp_reset()
147 writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); in analogix_dp_reset()
149 writel(0x0, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); in analogix_dp_reset()
150 writel(0x0, dp->reg_base + ANALOGIX_DP_HDCP_CTL); in analogix_dp_reset()
152 writel(0x5e, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_L); in analogix_dp_reset()
153 writel(0x1a, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_H); in analogix_dp_reset()
155 writel(0x10, dp->reg_base + ANALOGIX_DP_LINK_DEBUG_CTL); in analogix_dp_reset()
157 writel(0x0, dp->reg_base + ANALOGIX_DP_PHY_TEST); in analogix_dp_reset()
159 writel(0x0, dp->reg_base + ANALOGIX_DP_VIDEO_FIFO_THRD); in analogix_dp_reset()
160 writel(0x20, dp->reg_base + ANALOGIX_DP_AUDIO_MARGIN); in analogix_dp_reset()
162 writel(0x4, dp->reg_base + ANALOGIX_DP_M_VID_GEN_FILTER_TH); in analogix_dp_reset()
163 writel(0x2, dp->reg_base + ANALOGIX_DP_M_AUD_GEN_FILTER_TH); in analogix_dp_reset()
165 writel(0x00000101, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); in analogix_dp_reset()
170 writel(RESET_DP_TX, dp->reg_base + ANALOGIX_DP_TX_SW_RESET); in analogix_dp_swreset()
179 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1); in analogix_dp_config_interrupt()
182 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2); in analogix_dp_config_interrupt()
185 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3); in analogix_dp_config_interrupt()
188 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); in analogix_dp_config_interrupt()
191 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); in analogix_dp_config_interrupt()
199 reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); in analogix_dp_mute_hpd_interrupt()
201 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); in analogix_dp_mute_hpd_interrupt()
203 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA_MASK); in analogix_dp_mute_hpd_interrupt()
205 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); in analogix_dp_mute_hpd_interrupt()
214 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); in analogix_dp_unmute_hpd_interrupt()
217 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); in analogix_dp_unmute_hpd_interrupt()
224 return readl_poll_timeout(dp->reg_base + ANALOGIX_DP_DEBUG_CTL, val, in analogix_dp_wait_pll_locked()
235 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) { in analogix_dp_set_pll_power_down()
240 reg = readl(dp->reg_base + pd_addr); in analogix_dp_set_pll_power_down()
245 writel(reg, dp->reg_base + pd_addr); in analogix_dp_set_pll_power_down()
256 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) in analogix_dp_set_analog_power_down()
261 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) in analogix_dp_set_analog_power_down()
266 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
271 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
275 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
281 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
285 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
291 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
295 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
301 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
305 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
311 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
317 * Rockchip in analogix_dp_set_analog_power_down()
319 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) in analogix_dp_set_analog_power_down()
324 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
330 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
331 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) in analogix_dp_set_analog_power_down()
337 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
340 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
343 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
346 writel(0x00, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
361 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); in analogix_dp_init_analog_func()
363 reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL); in analogix_dp_init_analog_func()
365 writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL); in analogix_dp_init_analog_func()
371 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); in analogix_dp_init_analog_func()
374 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); in analogix_dp_init_analog_func()
382 if (dp->hpd_gpiod) in analogix_dp_clear_hotplug_interrupts()
386 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); in analogix_dp_clear_hotplug_interrupts()
389 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA); in analogix_dp_clear_hotplug_interrupts()
396 if (dp->hpd_gpiod) in analogix_dp_init_hpd()
401 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); in analogix_dp_init_hpd()
403 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); in analogix_dp_init_hpd()
410 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); in analogix_dp_force_hpd()
412 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); in analogix_dp_force_hpd()
419 if (dp->hpd_gpiod) { in analogix_dp_get_irq_type()
420 reg = gpiod_get_value(dp->hpd_gpiod); in analogix_dp_get_irq_type()
427 reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); in analogix_dp_get_irq_type()
447 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); in analogix_dp_reset_aux()
449 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); in analogix_dp_reset_aux()
458 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA); in analogix_dp_init_aux()
466 /* AUX_BIT_PERIOD_EXPECTED_DELAY doesn't apply to Rockchip IP */ in analogix_dp_init_aux()
467 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) in analogix_dp_init_aux()
476 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL); in analogix_dp_init_aux()
480 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_DEFER_CTL); in analogix_dp_init_aux()
483 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); in analogix_dp_init_aux()
485 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); in analogix_dp_init_aux()
492 if (dp->hpd_gpiod) { in analogix_dp_get_plug_in_status()
493 if (gpiod_get_value(dp->hpd_gpiod)) in analogix_dp_get_plug_in_status()
496 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); in analogix_dp_get_plug_in_status()
501 return -EINVAL; in analogix_dp_get_plug_in_status()
508 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1); in analogix_dp_enable_sw_function()
510 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); in analogix_dp_enable_sw_function()
519 writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET); in analogix_dp_set_link_bandwidth()
526 reg = readl(dp->reg_base + ANALOGIX_DP_LINK_BW_SET); in analogix_dp_get_link_bandwidth()
535 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET); in analogix_dp_set_lane_count()
542 reg = readl(dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET); in analogix_dp_get_lane_count()
550 for (lane = 0; lane < dp->link_train.lane_count; lane++) in analogix_dp_set_lane_link_training()
551 writel(dp->link_train.training_lane[lane], in analogix_dp_set_lane_link_training()
552 dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane); in analogix_dp_set_lane_link_training()
557 return readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane); in analogix_dp_get_lane_link_training()
566 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); in analogix_dp_enable_enhanced_mode()
568 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); in analogix_dp_enable_enhanced_mode()
570 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); in analogix_dp_enable_enhanced_mode()
572 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); in analogix_dp_enable_enhanced_mode()
584 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); in analogix_dp_set_training_pattern()
588 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); in analogix_dp_set_training_pattern()
592 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); in analogix_dp_set_training_pattern()
596 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); in analogix_dp_set_training_pattern()
602 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); in analogix_dp_set_training_pattern()
613 reg = readl(dp->reg_base + ANALOGIX_DP_PHY_TEST); in analogix_dp_reset_macro()
615 writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST); in analogix_dp_reset_macro()
621 writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST); in analogix_dp_reset_macro()
629 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); in analogix_dp_init_video()
632 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); in analogix_dp_init_video()
635 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); in analogix_dp_init_video()
638 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); in analogix_dp_init_video()
641 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_8); in analogix_dp_init_video()
649 reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) | in analogix_dp_set_video_color_format()
650 (dp->video_info.color_depth << IN_BPC_SHIFT) | in analogix_dp_set_video_color_format()
651 (dp->video_info.color_space << IN_COLOR_F_SHIFT); in analogix_dp_set_video_color_format()
652 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2); in analogix_dp_set_video_color_format()
655 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); in analogix_dp_set_video_color_format()
657 if (dp->video_info.ycbcr_coeff) in analogix_dp_set_video_color_format()
661 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); in analogix_dp_set_video_color_format()
668 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1); in analogix_dp_is_slave_video_stream_clock_on()
669 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); in analogix_dp_is_slave_video_stream_clock_on()
671 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1); in analogix_dp_is_slave_video_stream_clock_on()
674 dev_dbg(dp->dev, "Input stream clock not detected.\n"); in analogix_dp_is_slave_video_stream_clock_on()
675 return -EINVAL; in analogix_dp_is_slave_video_stream_clock_on()
678 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2); in analogix_dp_is_slave_video_stream_clock_on()
679 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); in analogix_dp_is_slave_video_stream_clock_on()
681 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2); in analogix_dp_is_slave_video_stream_clock_on()
682 dev_dbg(dp->dev, "wait SYS_CTL_2.\n"); in analogix_dp_is_slave_video_stream_clock_on()
685 dev_dbg(dp->dev, "Input stream clk is changing\n"); in analogix_dp_is_slave_video_stream_clock_on()
686 return -EINVAL; in analogix_dp_is_slave_video_stream_clock_on()
699 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); in analogix_dp_set_video_cr_mn()
701 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); in analogix_dp_set_video_cr_mn()
703 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_0); in analogix_dp_set_video_cr_mn()
705 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_1); in analogix_dp_set_video_cr_mn()
707 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_2); in analogix_dp_set_video_cr_mn()
710 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_0); in analogix_dp_set_video_cr_mn()
712 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_1); in analogix_dp_set_video_cr_mn()
714 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_2); in analogix_dp_set_video_cr_mn()
716 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); in analogix_dp_set_video_cr_mn()
718 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); in analogix_dp_set_video_cr_mn()
720 writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_0); in analogix_dp_set_video_cr_mn()
721 writel(0x80, dp->reg_base + ANALOGIX_DP_N_VID_1); in analogix_dp_set_video_cr_mn()
722 writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_2); in analogix_dp_set_video_cr_mn()
731 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); in analogix_dp_set_video_timing_mode()
733 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); in analogix_dp_set_video_timing_mode()
735 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); in analogix_dp_set_video_timing_mode()
737 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); in analogix_dp_set_video_timing_mode()
746 reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); in analogix_dp_enable_video_master()
749 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); in analogix_dp_enable_video_master()
751 reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); in analogix_dp_enable_video_master()
754 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); in analogix_dp_enable_video_master()
762 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_start_video()
764 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_start_video()
771 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); in analogix_dp_is_video_stream_on()
772 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); in analogix_dp_is_video_stream_on()
774 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); in analogix_dp_is_video_stream_on()
776 dev_dbg(dp->dev, "Input video stream is not detected.\n"); in analogix_dp_is_video_stream_on()
777 return -EINVAL; in analogix_dp_is_video_stream_on()
787 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1); in analogix_dp_config_video_slave_mode()
788 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) { in analogix_dp_config_video_slave_mode()
794 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); in analogix_dp_config_video_slave_mode()
796 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); in analogix_dp_config_video_slave_mode()
798 reg |= (dp->video_info.interlaced << 2); in analogix_dp_config_video_slave_mode()
799 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); in analogix_dp_config_video_slave_mode()
801 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); in analogix_dp_config_video_slave_mode()
803 reg |= (dp->video_info.v_sync_polarity << 1); in analogix_dp_config_video_slave_mode()
804 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); in analogix_dp_config_video_slave_mode()
806 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); in analogix_dp_config_video_slave_mode()
808 reg |= (dp->video_info.h_sync_polarity << 0); in analogix_dp_config_video_slave_mode()
809 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); in analogix_dp_config_video_slave_mode()
812 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); in analogix_dp_config_video_slave_mode()
819 reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); in analogix_dp_enable_scrambling()
821 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); in analogix_dp_enable_scrambling()
828 reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); in analogix_dp_disable_scrambling()
830 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); in analogix_dp_disable_scrambling()
835 writel(PSR_VID_CRC_ENABLE, dp->reg_base + ANALOGIX_DP_CRC_CON); in analogix_dp_enable_psr_crc()
843 val = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &status); in analogix_dp_get_psr_status()
845 dev_err(dp->dev, "PSR_STATUS read failed ret=%zd", val); in analogix_dp_get_psr_status()
859 val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); in analogix_dp_send_psr_spd()
861 writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); in analogix_dp_send_psr_spd()
865 dp->reg_base + ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL); in analogix_dp_send_psr_spd()
868 writel(vsc->sdp_header.HB0, dp->reg_base + ANALOGIX_DP_SPD_HB0); in analogix_dp_send_psr_spd()
869 writel(vsc->sdp_header.HB1, dp->reg_base + ANALOGIX_DP_SPD_HB1); in analogix_dp_send_psr_spd()
870 writel(vsc->sdp_header.HB2, dp->reg_base + ANALOGIX_DP_SPD_HB2); in analogix_dp_send_psr_spd()
871 writel(vsc->sdp_header.HB3, dp->reg_base + ANALOGIX_DP_SPD_HB3); in analogix_dp_send_psr_spd()
874 writel(0x00, dp->reg_base + ANALOGIX_DP_SPD_PB0); in analogix_dp_send_psr_spd()
875 writel(0x16, dp->reg_base + ANALOGIX_DP_SPD_PB1); in analogix_dp_send_psr_spd()
876 writel(0xCE, dp->reg_base + ANALOGIX_DP_SPD_PB2); in analogix_dp_send_psr_spd()
877 writel(0x5D, dp->reg_base + ANALOGIX_DP_SPD_PB3); in analogix_dp_send_psr_spd()
880 writel(vsc->db[0], dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB0); in analogix_dp_send_psr_spd()
881 writel(vsc->db[1], dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB1); in analogix_dp_send_psr_spd()
884 val = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); in analogix_dp_send_psr_spd()
886 writel(val, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); in analogix_dp_send_psr_spd()
889 val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); in analogix_dp_send_psr_spd()
891 writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); in analogix_dp_send_psr_spd()
894 val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); in analogix_dp_send_psr_spd()
896 writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); in analogix_dp_send_psr_spd()
904 * (a) ACTIVE_RESYNC - the sink "must display the in analogix_dp_send_psr_spd()
907 * re-synchronizing; or in analogix_dp_send_psr_spd()
908 * (b) INACTIVE - the transition is fully complete. in analogix_dp_send_psr_spd()
912 ((vsc->db[1] && psr_status == DP_PSR_SINK_ACTIVE_RFB) || in analogix_dp_send_psr_spd()
913 (!vsc->db[1] && (psr_status == DP_PSR_SINK_ACTIVE_RESYNC || in analogix_dp_send_psr_spd()
917 dev_warn(dp->dev, "Failed to apply PSR %d\n", ret); in analogix_dp_send_psr_spd()
927 u8 *buffer = msg->buffer; in analogix_dp_transfer()
932 if (WARN_ON(msg->size > 16)) in analogix_dp_transfer()
933 return -E2BIG; in analogix_dp_transfer()
937 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); in analogix_dp_transfer()
939 switch (msg->request & ~DP_AUX_I2C_MOT) { in analogix_dp_transfer()
942 if (msg->request & DP_AUX_I2C_MOT) in analogix_dp_transfer()
948 if (msg->request & DP_AUX_I2C_MOT) in analogix_dp_transfer()
961 return -EINVAL; in analogix_dp_transfer()
964 reg |= AUX_LENGTH(msg->size); in analogix_dp_transfer()
965 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); in analogix_dp_transfer()
968 reg = AUX_ADDR_7_0(msg->address); in analogix_dp_transfer()
969 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); in analogix_dp_transfer()
970 reg = AUX_ADDR_15_8(msg->address); in analogix_dp_transfer()
971 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); in analogix_dp_transfer()
972 reg = AUX_ADDR_19_16(msg->address); in analogix_dp_transfer()
973 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); in analogix_dp_transfer()
975 if (!(msg->request & DP_AUX_I2C_READ)) { in analogix_dp_transfer()
976 for (i = 0; i < msg->size; i++) { in analogix_dp_transfer()
978 writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0 + in analogix_dp_transfer()
986 /* Zero-sized messages specify address-only transactions. */ in analogix_dp_transfer()
987 if (msg->size < 1) in analogix_dp_transfer()
990 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); in analogix_dp_transfer()
992 ret = readx_poll_timeout(readl, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2, in analogix_dp_transfer()
995 dev_err(dp->dev, "AUX CH enable timeout!\n"); in analogix_dp_transfer()
1001 ret = readx_poll_timeout(readl, dp->reg_base + ANALOGIX_DP_INT_STA, in analogix_dp_transfer()
1004 dev_err(dp->dev, "AUX CH cmd reply timeout!\n"); in analogix_dp_transfer()
1009 writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA); in analogix_dp_transfer()
1012 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); in analogix_dp_transfer()
1014 u32 aux_status = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA) & in analogix_dp_transfer()
1017 writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA); in analogix_dp_transfer()
1020 return -ETIMEDOUT; in analogix_dp_transfer()
1022 dev_warn(dp->dev, "AUX CH error happened: %#x (%d)\n", in analogix_dp_transfer()
1027 if (msg->request & DP_AUX_I2C_READ) { in analogix_dp_transfer()
1028 for (i = 0; i < msg->size; i++) { in analogix_dp_transfer()
1029 reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0 + in analogix_dp_transfer()
1036 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM); in analogix_dp_transfer()
1038 msg->reply = DP_AUX_NATIVE_REPLY_DEFER; in analogix_dp_transfer()
1040 msg->reply = DP_AUX_I2C_REPLY_DEFER; in analogix_dp_transfer()
1041 else if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE || in analogix_dp_transfer()
1042 (msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_READ) in analogix_dp_transfer()
1043 msg->reply = DP_AUX_I2C_REPLY_ACK; in analogix_dp_transfer()
1044 else if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE || in analogix_dp_transfer()
1045 (msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_READ) in analogix_dp_transfer()
1046 msg->reply = DP_AUX_NATIVE_REPLY_ACK; in analogix_dp_transfer()
1048 return msg->size; in analogix_dp_transfer()
1054 return -EREMOTEIO; in analogix_dp_transfer()