Lines Matching +full:test +full:- +full:rules
1 // SPDX-License-Identifier: GPL-2.0+
76 /* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45
77 * is set, they cannot be accessed by C45-over-C22.
125 struct device *dev = &phydev->mdio.dev; in rtl821x_probe()
127 u32 phy_id = phydev->drv->phy_id; in rtl821x_probe()
132 return -ENOMEM; in rtl821x_probe()
134 priv->clk = devm_clk_get_optional_enabled(dev, NULL); in rtl821x_probe()
135 if (IS_ERR(priv->clk)) in rtl821x_probe()
136 return dev_err_probe(dev, PTR_ERR(priv->clk), in rtl821x_probe()
143 priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF); in rtl821x_probe()
144 if (of_property_read_bool(dev->of_node, "realtek,aldps-enable")) in rtl821x_probe()
145 priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF; in rtl821x_probe()
147 priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID); in rtl821x_probe()
148 if (priv->has_phycr2) { in rtl821x_probe()
153 priv->phycr2 = ret & RTL8211F_CLKOUT_EN; in rtl821x_probe()
154 if (of_property_read_bool(dev->of_node, "realtek,clkout-disable")) in rtl821x_probe()
155 priv->phycr2 &= ~RTL8211F_CLKOUT_EN; in rtl821x_probe()
158 phydev->priv = priv; in rtl821x_probe()
195 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in rtl8201_config_intr()
218 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in rtl8211b_config_intr()
240 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in rtl8211e_config_intr()
263 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in rtl8211f_config_intr()
353 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) { in rtl8211_config_aneg()
373 struct rtl821x_priv *priv = phydev->priv; in rtl8211f_config_init()
374 struct device *dev = &phydev->mdio.dev; in rtl8211f_config_init()
380 priv->phycr1); in rtl8211f_config_init()
387 switch (phydev->interface) { in rtl8211f_config_init()
419 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", in rtl8211f_config_init()
423 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", in rtl8211f_config_init()
434 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", in rtl8211f_config_init()
438 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", in rtl8211f_config_init()
442 if (priv->has_phycr2) { in rtl8211f_config_init()
444 RTL8211F_CLKOUT_EN, priv->phycr2); in rtl8211f_config_init()
459 struct rtl821x_priv *priv = phydev->priv; in rtl821x_suspend()
462 if (!phydev->wol_enabled) { in rtl821x_suspend()
468 clk_disable_unprepare(priv->clk); in rtl821x_suspend()
476 struct rtl821x_priv *priv = phydev->priv; in rtl821x_resume()
479 if (!phydev->wol_enabled) in rtl821x_resume()
480 clk_prepare_enable(priv->clk); in rtl821x_resume()
492 unsigned long rules) in rtl8211f_led_hw_is_supported() argument
501 * - Link: Configurable subset of 10/100/1000 link rates in rtl8211f_led_hw_is_supported()
502 * - Active: Blink on activity, RX or TX is not differentiated in rtl8211f_led_hw_is_supported()
504 * - A: Link and Active indication at configurable, but matching, in rtl8211f_led_hw_is_supported()
506 * - B: Link indication at configurable subset of 10/100/1000 link in rtl8211f_led_hw_is_supported()
513 return -EINVAL; in rtl8211f_led_hw_is_supported()
516 if (rules & ~mask) in rtl8211f_led_hw_is_supported()
517 return -EOPNOTSUPP; in rtl8211f_led_hw_is_supported()
520 if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX))) in rtl8211f_led_hw_is_supported()
521 return -EOPNOTSUPP; in rtl8211f_led_hw_is_supported()
527 unsigned long *rules) in rtl8211f_led_hw_control_get() argument
532 return -EINVAL; in rtl8211f_led_hw_control_get()
542 set_bit(TRIGGER_NETDEV_LINK_10, rules); in rtl8211f_led_hw_control_get()
545 set_bit(TRIGGER_NETDEV_LINK_100, rules); in rtl8211f_led_hw_control_get()
548 set_bit(TRIGGER_NETDEV_LINK_1000, rules); in rtl8211f_led_hw_control_get()
551 set_bit(TRIGGER_NETDEV_RX, rules); in rtl8211f_led_hw_control_get()
552 set_bit(TRIGGER_NETDEV_TX, rules); in rtl8211f_led_hw_control_get()
559 unsigned long rules) in rtl8211f_led_hw_control_set() argument
565 return -EINVAL; in rtl8211f_led_hw_control_set()
567 if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) in rtl8211f_led_hw_control_set()
570 if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) in rtl8211f_led_hw_control_set()
573 if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) in rtl8211f_led_hw_control_set()
576 if (test_bit(TRIGGER_NETDEV_RX, &rules) || in rtl8211f_led_hw_control_set()
577 test_bit(TRIGGER_NETDEV_TX, &rules)) { in rtl8211f_led_hw_control_set()
592 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ in rtl8211e_config_init()
593 switch (phydev->interface) { in rtl8211e_config_init()
617 * 10:0 = Test && debug settings reserved by realtek in rtl8211e_config_init()
656 dev_err(&phydev->mdio.dev, in rtl8366rb_config_init()
668 phydev->speed = SPEED_10; in rtlgen_decode_speed()
671 phydev->speed = SPEED_100; in rtlgen_decode_speed()
674 phydev->speed = SPEED_1000; in rtlgen_decode_speed()
677 phydev->speed = SPEED_10000; in rtlgen_decode_speed()
680 phydev->speed = SPEED_2500; in rtlgen_decode_speed()
683 phydev->speed = SPEED_5000; in rtlgen_decode_speed()
698 if (!phydev->link) in rtlgen_read_status()
727 ret = -EOPNOTSUPP; in rtlgen_read_mmd()
743 ret = -EOPNOTSUPP; in rtlgen_write_mmd()
753 if (ret != -EOPNOTSUPP) in rtl822x_read_mmd()
778 if (ret != -EOPNOTSUPP) in rtl822x_write_mmd()
797 phydev->host_interfaces) || in rtl822xb_config_init()
798 phydev->interface == PHY_INTERFACE_MODE_2500BASEX; in rtl822xb_config_init()
801 phydev->host_interfaces) || in rtl822xb_config_init()
802 phydev->interface == PHY_INTERFACE_MODE_SGMII; in rtl822xb_config_init()
805 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces, in rtl822xb_config_init()
807 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces, in rtl822xb_config_init()
816 phydev->rate_matching = RATE_MATCH_PAUSE; in rtl822xb_config_init()
819 phydev->rate_matching = RATE_MATCH_NONE; in rtl822xb_config_init()
852 /* Only rate matching at 2500base-x */ in rtl822xb_get_rate_matching()
877 phydev->supported, val & MDIO_PMA_SPEED_2_5G); in rtl822x_get_features()
879 phydev->supported, val & MDIO_PMA_SPEED_5G); in rtl822x_get_features()
881 phydev->supported, val & MDIO_SPEED_10G); in rtl822x_get_features()
890 if (phydev->autoneg == AUTONEG_ENABLE) { in rtl822x_config_aneg()
891 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); in rtl822x_config_aneg()
908 if (!phydev->link) in rtl822xb_update_interface()
918 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; in rtl822xb_update_interface()
921 phydev->interface = PHY_INTERFACE_MODE_SGMII; in rtl822xb_update_interface()
928 if (phydev->autoneg == AUTONEG_ENABLE) { in rtl822x_read_status()
934 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, in rtl822x_read_status()
957 phydev->supported); in rtl822x_c45_get_features()
967 if (phydev->autoneg == AUTONEG_DISABLE) in rtl822x_c45_config_aneg()
976 val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); in rtl822x_c45_config_aneg()
998 if (phydev->autoneg == AUTONEG_ENABLE) { in rtl822x_c45_read_status()
1004 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); in rtl822x_c45_read_status()
1007 if (!phydev->link) in rtl822x_c45_read_status()
1045 * Check a MMD register which is known to be non-zero.
1063 return phydev->phy_id == RTL_GENERIC_PHYID && in rtlgen_match_phy_device()
1069 return phydev->phy_id == RTL_GENERIC_PHYID && in rtl8226_match_phy_device()
1077 if (phydev->is_c45) in rtlgen_is_c45_match()
1078 return is_c45 && (id == phydev->c45_ids.device_ids[1]); in rtlgen_is_c45_match()
1080 return !is_c45 && (id == phydev->phy_id); in rtlgen_is_c45_match()
1085 return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev); in rtl8221b_match_phy_device()
1110 if (phydev->is_c45) in rtl_internal_nbaset_match_phy_device()
1113 switch (phydev->phy_id) { in rtl_internal_nbaset_match_phy_device()
1152 phydev->autoneg = AUTONEG_DISABLE; in rtl9000a_config_init()
1153 phydev->speed = SPEED_100; in rtl9000a_config_init()
1154 phydev->duplex = DUPLEX_FULL; in rtl9000a_config_init()
1164 switch (phydev->master_slave_set) { in rtl9000a_config_aneg()
1175 return -EOPNOTSUPP; in rtl9000a_config_aneg()
1189 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; in rtl9000a_read_status()
1190 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; in rtl9000a_read_status()
1200 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; in rtl9000a_read_status()
1202 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; in rtl9000a_read_status()
1208 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; in rtl9000a_read_status()
1210 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; in rtl9000a_read_status()
1229 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in rtl9000a_config_intr()
1354 .name = "RTL8211F-VD Gigabit Ethernet",
1366 .name = "Generic FE-GE Realtek PHY",
1399 .name = "RTL8226-CG 2.5Gbps PHY",
1409 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
1421 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)",
1433 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)",
1443 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)",
1455 .name = "RTL8221B-VN-CG 2.5Gbps PHY (C45)",
1475 .name = "Realtek Internal NBASE-T PHY",
1522 .name = "RTL8365MB-VC Gigabit Ethernet",