1 /*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25
26 #ifndef __INTEL_DISPLAY_TYPES_H__
27 #define __INTEL_DISPLAY_TYPES_H__
28
29 #include <linux/i2c.h>
30 #include <linux/pm_qos.h>
31 #include <linux/pwm.h>
32 #include <linux/sched/clock.h>
33
34 #include <drm/display/drm_dp_dual_mode_helper.h>
35 #include <drm/display/drm_dp_mst_helper.h>
36 #include <drm/display/drm_dp_tunnel.h>
37 #include <drm/display/drm_dsc.h>
38 #include <drm/drm_atomic.h>
39 #include <drm/drm_crtc.h>
40 #include <drm/drm_encoder.h>
41 #include <drm/drm_fourcc.h>
42 #include <drm/drm_framebuffer.h>
43 #include <drm/drm_probe_helper.h>
44 #include <drm/drm_rect.h>
45 #include <drm/drm_vblank.h>
46 #include <drm/drm_vblank_work.h>
47 #include <drm/intel/i915_hdcp_interface.h>
48 #include <media/cec-notifier.h>
49
50 #include "gem/i915_gem_object_types.h" /* for to_intel_bo() */
51 #include "i915_vma.h"
52 #include "i915_vma_types.h"
53 #include "intel_bios.h"
54 #include "intel_display.h"
55 #include "intel_display_limits.h"
56 #include "intel_display_power.h"
57 #include "intel_dpll_mgr.h"
58 #include "intel_wm_types.h"
59
60 struct drm_printer;
61 struct __intel_global_objs_state;
62 struct intel_ddi_buf_trans;
63 struct intel_fbc;
64 struct intel_connector;
65 struct intel_tc_port;
66
67 /*
68 * Display related stuff
69 */
70
71 /* these are outputs from the chip - integrated only
72 external chips are via DVO or SDVO output */
73 enum intel_output_type {
74 INTEL_OUTPUT_UNUSED = 0,
75 INTEL_OUTPUT_ANALOG = 1,
76 INTEL_OUTPUT_DVO = 2,
77 INTEL_OUTPUT_SDVO = 3,
78 INTEL_OUTPUT_LVDS = 4,
79 INTEL_OUTPUT_TVOUT = 5,
80 INTEL_OUTPUT_HDMI = 6,
81 INTEL_OUTPUT_DP = 7,
82 INTEL_OUTPUT_EDP = 8,
83 INTEL_OUTPUT_DSI = 9,
84 INTEL_OUTPUT_DDI = 10,
85 INTEL_OUTPUT_DP_MST = 11,
86 };
87
88 enum hdmi_force_audio {
89 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
90 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
91 HDMI_AUDIO_AUTO, /* trust EDID */
92 HDMI_AUDIO_ON, /* force turn on HDMI audio */
93 };
94
95 /* "Broadcast RGB" property */
96 enum intel_broadcast_rgb {
97 INTEL_BROADCAST_RGB_AUTO,
98 INTEL_BROADCAST_RGB_FULL,
99 INTEL_BROADCAST_RGB_LIMITED,
100 };
101
102 struct intel_fb_view {
103 /*
104 * The remap information used in the remapped and rotated views to
105 * create the DMA scatter-gather list for each FB color plane. This sg
106 * list is created along with the view type (gtt.type) specific
107 * i915_vma object and contains the list of FB object pages (reordered
108 * in the rotated view) that are visible in the view.
109 * In the normal view the FB object's backing store sg list is used
110 * directly and hence the remap information here is not used.
111 */
112 struct i915_gtt_view gtt;
113
114 /*
115 * The GTT view (gtt.type) specific information for each FB color
116 * plane. In the normal GTT view all formats (up to 4 color planes),
117 * in the rotated and remapped GTT view all no-CCS formats (up to 2
118 * color planes) are supported.
119 *
120 * The view information shared by all FB color planes in the FB,
121 * like dst x/y and src/dst width, is stored separately in
122 * intel_plane_state.
123 */
124 struct i915_color_plane_view {
125 u32 offset;
126 unsigned int x, y;
127 /*
128 * Plane stride in:
129 * bytes for 0/180 degree rotation
130 * pixels for 90/270 degree rotation
131 */
132 unsigned int mapping_stride;
133 unsigned int scanout_stride;
134 } color_plane[4];
135 };
136
137 struct intel_framebuffer {
138 struct drm_framebuffer base;
139 struct intel_frontbuffer *frontbuffer;
140
141 /* Params to remap the FB pages and program the plane registers in each view. */
142 struct intel_fb_view normal_view;
143 union {
144 struct intel_fb_view rotated_view;
145 struct intel_fb_view remapped_view;
146 };
147
148 struct i915_address_space *dpt_vm;
149
150 unsigned int min_alignment;
151 };
152
153 enum intel_hotplug_state {
154 INTEL_HOTPLUG_UNCHANGED,
155 INTEL_HOTPLUG_CHANGED,
156 INTEL_HOTPLUG_RETRY,
157 };
158
159 struct intel_encoder {
160 struct drm_encoder base;
161
162 enum intel_output_type type;
163 enum port port;
164 u16 cloneable;
165 u8 pipe_mask;
166
167 /* Check and recover a bad link state. */
168 struct delayed_work link_check_work;
169 void (*link_check)(struct intel_encoder *encoder);
170
171 enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder,
172 struct intel_connector *connector);
173 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
174 struct intel_crtc_state *,
175 struct drm_connector_state *);
176 int (*compute_config)(struct intel_encoder *,
177 struct intel_crtc_state *,
178 struct drm_connector_state *);
179 int (*compute_config_late)(struct intel_encoder *,
180 struct intel_crtc_state *,
181 struct drm_connector_state *);
182 void (*pre_pll_enable)(struct intel_atomic_state *,
183 struct intel_encoder *,
184 const struct intel_crtc_state *,
185 const struct drm_connector_state *);
186 void (*pre_enable)(struct intel_atomic_state *,
187 struct intel_encoder *,
188 const struct intel_crtc_state *,
189 const struct drm_connector_state *);
190 void (*enable)(struct intel_atomic_state *,
191 struct intel_encoder *,
192 const struct intel_crtc_state *,
193 const struct drm_connector_state *);
194 void (*disable)(struct intel_atomic_state *,
195 struct intel_encoder *,
196 const struct intel_crtc_state *,
197 const struct drm_connector_state *);
198 void (*post_disable)(struct intel_atomic_state *,
199 struct intel_encoder *,
200 const struct intel_crtc_state *,
201 const struct drm_connector_state *);
202 void (*post_pll_disable)(struct intel_atomic_state *,
203 struct intel_encoder *,
204 const struct intel_crtc_state *,
205 const struct drm_connector_state *);
206 void (*update_pipe)(struct intel_atomic_state *,
207 struct intel_encoder *,
208 const struct intel_crtc_state *,
209 const struct drm_connector_state *);
210 void (*audio_enable)(struct intel_encoder *encoder,
211 const struct intel_crtc_state *crtc_state,
212 const struct drm_connector_state *conn_state);
213 void (*audio_disable)(struct intel_encoder *encoder,
214 const struct intel_crtc_state *old_crtc_state,
215 const struct drm_connector_state *old_conn_state);
216 /* Read out the current hw state of this connector, returning true if
217 * the encoder is active. If the encoder is enabled it also set the pipe
218 * it is connected to in the pipe parameter. */
219 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
220 /* Reconstructs the equivalent mode flags for the current hardware
221 * state. This must be called _after_ display->get_pipe_config has
222 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
223 * be set correctly before calling this function. */
224 void (*get_config)(struct intel_encoder *,
225 struct intel_crtc_state *pipe_config);
226
227 /*
228 * Optional hook called during init/resume to sync any state
229 * stored in the encoder (eg. DP link parameters) wrt. the HW state.
230 */
231 void (*sync_state)(struct intel_encoder *encoder,
232 const struct intel_crtc_state *crtc_state);
233
234 /*
235 * Optional hook, returning true if this encoder allows a fastset
236 * during the initial commit, false otherwise.
237 */
238 bool (*initial_fastset_check)(struct intel_encoder *encoder,
239 struct intel_crtc_state *crtc_state);
240
241 /*
242 * Acquires the power domains needed for an active encoder during
243 * hardware state readout.
244 */
245 void (*get_power_domains)(struct intel_encoder *encoder,
246 struct intel_crtc_state *crtc_state);
247 /*
248 * Called during system suspend after all pending requests for the
249 * encoder are flushed (for example for DP AUX transactions) and
250 * device interrupts are disabled.
251 * All modeset locks are held while the hook is called.
252 */
253 void (*suspend)(struct intel_encoder *);
254 /*
255 * Called without the modeset locks held after the suspend() hook for
256 * all encoders have been called.
257 */
258 void (*suspend_complete)(struct intel_encoder *encoder);
259 /*
260 * Called during system reboot/shutdown after all the
261 * encoders have been disabled and suspended.
262 * All modeset locks are held while the hook is called.
263 */
264 void (*shutdown)(struct intel_encoder *encoder);
265 /*
266 * Called without the modeset locks held after the shutdown() hook for
267 * all encoders have been called.
268 */
269 void (*shutdown_complete)(struct intel_encoder *encoder);
270 /*
271 * Enable/disable the clock to the port.
272 */
273 void (*enable_clock)(struct intel_encoder *encoder,
274 const struct intel_crtc_state *crtc_state);
275 void (*disable_clock)(struct intel_encoder *encoder);
276 /*
277 * Returns whether the port clock is enabled or not.
278 */
279 bool (*is_clock_enabled)(struct intel_encoder *encoder);
280 /*
281 * Returns the PLL type the port uses.
282 */
283 enum icl_port_dpll_id (*port_pll_type)(struct intel_encoder *encoder,
284 const struct intel_crtc_state *crtc_state);
285 const struct intel_ddi_buf_trans *(*get_buf_trans)(struct intel_encoder *encoder,
286 const struct intel_crtc_state *crtc_state,
287 int *n_entries);
288 void (*set_signal_levels)(struct intel_encoder *encoder,
289 const struct intel_crtc_state *crtc_state);
290
291 enum hpd_pin hpd_pin;
292 enum intel_display_power_domain power_domain;
293
294 /* VBT information for this encoder (may be NULL for older platforms) */
295 const struct intel_bios_encoder_data *devdata;
296 };
297
298 struct intel_panel_bl_funcs {
299 /* Connector and platform specific backlight functions */
300 int (*setup)(struct intel_connector *connector, enum pipe pipe);
301 u32 (*get)(struct intel_connector *connector, enum pipe pipe);
302 void (*set)(const struct drm_connector_state *conn_state, u32 level);
303 void (*disable)(const struct drm_connector_state *conn_state, u32 level);
304 void (*enable)(const struct intel_crtc_state *crtc_state,
305 const struct drm_connector_state *conn_state, u32 level);
306 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
307 };
308
309 enum drrs_type {
310 DRRS_TYPE_NONE,
311 DRRS_TYPE_STATIC,
312 DRRS_TYPE_SEAMLESS,
313 };
314
315 struct intel_vbt_panel_data {
316 struct drm_display_mode *lfp_vbt_mode; /* if any */
317 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
318
319 /* Feature bits */
320 int panel_type;
321 unsigned int lvds_dither:1;
322 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
323
324 bool vrr;
325
326 u8 seamless_drrs_min_refresh_rate;
327 enum drrs_type drrs_type;
328
329 struct {
330 int max_link_rate;
331 int rate;
332 int lanes;
333 int preemphasis;
334 int vswing;
335 int bpp;
336 struct edp_power_seq pps;
337 u8 drrs_msa_timing_delay;
338 bool low_vswing;
339 bool hobl;
340 bool dsc_disable;
341 } edp;
342
343 struct {
344 bool enable;
345 bool full_link;
346 bool require_aux_wakeup;
347 int idle_frames;
348 int tp1_wakeup_time_us;
349 int tp2_tp3_wakeup_time_us;
350 int psr2_tp2_tp3_wakeup_time_us;
351 } psr;
352
353 struct {
354 u16 pwm_freq_hz;
355 u16 brightness_precision_bits;
356 u16 hdr_dpcd_refresh_timeout;
357 bool present;
358 bool active_low_pwm;
359 u8 min_brightness; /* min_brightness/255 of max */
360 s8 controller; /* brightness controller number */
361 enum intel_backlight_type type;
362 } backlight;
363
364 /* MIPI DSI */
365 struct {
366 u16 panel_id;
367 struct mipi_config *config;
368 struct mipi_pps_data *pps;
369 u16 bl_ports;
370 u16 cabc_ports;
371 u8 seq_version;
372 u32 size;
373 u8 *data;
374 const u8 *sequence[MIPI_SEQ_MAX];
375 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
376 enum drm_panel_orientation orientation;
377 } dsi;
378 };
379
380 struct intel_panel {
381 /* Fixed EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
382 const struct drm_edid *fixed_edid;
383
384 struct list_head fixed_modes;
385
386 /* backlight */
387 struct {
388 bool present;
389 u32 level;
390 u32 min;
391 u32 max;
392 bool enabled;
393 bool combination_mode; /* gen 2/4 only */
394 bool active_low_pwm;
395 bool alternate_pwm_increment; /* lpt+ */
396
397 /* PWM chip */
398 u32 pwm_level_min;
399 u32 pwm_level_max;
400 bool pwm_enabled;
401 bool util_pin_active_low; /* bxt+ */
402 u8 controller; /* bxt+ only */
403 struct pwm_device *pwm;
404 struct pwm_state pwm_state;
405
406 /* DPCD backlight */
407 union {
408 struct {
409 struct drm_edp_backlight_info info;
410 } vesa;
411 struct {
412 bool sdr_uses_aux;
413 bool supports_2084_decode;
414 bool supports_2020_gamut;
415 bool supports_segmented_backlight;
416 bool supports_sdp_colorimetry;
417 bool supports_tone_mapping;
418 } intel_cap;
419 } edp;
420
421 struct backlight_device *device;
422
423 const struct intel_panel_bl_funcs *funcs;
424 const struct intel_panel_bl_funcs *pwm_funcs;
425 void (*power)(struct intel_connector *, bool enable);
426 } backlight;
427
428 struct intel_vbt_panel_data vbt;
429 };
430
431 struct intel_digital_port;
432
433 enum check_link_response {
434 HDCP_LINK_PROTECTED = 0,
435 HDCP_TOPOLOGY_CHANGE,
436 HDCP_LINK_INTEGRITY_FAILURE,
437 HDCP_REAUTH_REQUEST
438 };
439
440 /*
441 * This structure serves as a translation layer between the generic HDCP code
442 * and the bus-specific code. What that means is that HDCP over HDMI differs
443 * from HDCP over DP, so to account for these differences, we need to
444 * communicate with the receiver through this shim.
445 *
446 * For completeness, the 2 buses differ in the following ways:
447 * - DP AUX vs. DDC
448 * HDCP registers on the receiver are set via DP AUX for DP, and
449 * they are set via DDC for HDMI.
450 * - Receiver register offsets
451 * The offsets of the registers are different for DP vs. HDMI
452 * - Receiver register masks/offsets
453 * For instance, the ready bit for the KSV fifo is in a different
454 * place on DP vs HDMI
455 * - Receiver register names
456 * Seriously. In the DP spec, the 16-bit register containing
457 * downstream information is called BINFO, on HDMI it's called
458 * BSTATUS. To confuse matters further, DP has a BSTATUS register
459 * with a completely different definition.
460 * - KSV FIFO
461 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
462 * be read 3 keys at a time
463 * - Aksv output
464 * Since Aksv is hidden in hardware, there's different procedures
465 * to send it over DP AUX vs DDC
466 */
467 struct intel_hdcp_shim {
468 /* Outputs the transmitter's An and Aksv values to the receiver. */
469 int (*write_an_aksv)(struct intel_digital_port *dig_port, u8 *an);
470
471 /* Reads the receiver's key selection vector */
472 int (*read_bksv)(struct intel_digital_port *dig_port, u8 *bksv);
473
474 /*
475 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
476 * definitions are the same in the respective specs, but the names are
477 * different. Call it BSTATUS since that's the name the HDMI spec
478 * uses and it was there first.
479 */
480 int (*read_bstatus)(struct intel_digital_port *dig_port,
481 u8 *bstatus);
482
483 /* Determines whether a repeater is present downstream */
484 int (*repeater_present)(struct intel_digital_port *dig_port,
485 bool *repeater_present);
486
487 /* Reads the receiver's Ri' value */
488 int (*read_ri_prime)(struct intel_digital_port *dig_port, u8 *ri);
489
490 /* Determines if the receiver's KSV FIFO is ready for consumption */
491 int (*read_ksv_ready)(struct intel_digital_port *dig_port,
492 bool *ksv_ready);
493
494 /* Reads the ksv fifo for num_downstream devices */
495 int (*read_ksv_fifo)(struct intel_digital_port *dig_port,
496 int num_downstream, u8 *ksv_fifo);
497
498 /* Reads a 32-bit part of V' from the receiver */
499 int (*read_v_prime_part)(struct intel_digital_port *dig_port,
500 int i, u32 *part);
501
502 /* Enables HDCP signalling on the port */
503 int (*toggle_signalling)(struct intel_digital_port *dig_port,
504 enum transcoder cpu_transcoder,
505 bool enable);
506
507 /* Enable/Disable stream encryption on DP MST Transport Link */
508 int (*stream_encryption)(struct intel_connector *connector,
509 bool enable);
510
511 /* Ensures the link is still protected */
512 bool (*check_link)(struct intel_digital_port *dig_port,
513 struct intel_connector *connector);
514
515 /* Detects panel's hdcp capability. This is optional for HDMI. */
516 int (*hdcp_get_capability)(struct intel_digital_port *dig_port,
517 bool *hdcp_capable);
518
519 /* HDCP adaptation(DP/HDMI) required on the port */
520 enum hdcp_wired_protocol protocol;
521
522 /* Detects whether sink is HDCP2.2 capable */
523 int (*hdcp_2_2_get_capability)(struct intel_connector *connector,
524 bool *capable);
525
526 /* Write HDCP2.2 messages */
527 int (*write_2_2_msg)(struct intel_connector *connector,
528 void *buf, size_t size);
529
530 /* Read HDCP2.2 messages */
531 int (*read_2_2_msg)(struct intel_connector *connector,
532 u8 msg_id, void *buf, size_t size);
533
534 /*
535 * Implementation of DP HDCP2.2 Errata for the communication of stream
536 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
537 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
538 */
539 int (*config_stream_type)(struct intel_connector *connector,
540 bool is_repeater, u8 type);
541
542 /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
543 int (*stream_2_2_encryption)(struct intel_connector *connector,
544 bool enable);
545
546 /* HDCP2.2 Link Integrity Check */
547 int (*check_2_2_link)(struct intel_digital_port *dig_port,
548 struct intel_connector *connector);
549
550 /* HDCP remote sink cap */
551 int (*get_remote_hdcp_capability)(struct intel_connector *connector,
552 bool *hdcp_capable, bool *hdcp2_capable);
553 };
554
555 struct intel_hdcp {
556 const struct intel_hdcp_shim *shim;
557 /* Mutex for hdcp state of the connector */
558 struct mutex mutex;
559 u64 value;
560 struct delayed_work check_work;
561 struct work_struct prop_work;
562
563 /* HDCP1.4 Encryption status */
564 bool hdcp_encrypted;
565
566 /* HDCP2.2 related definitions */
567 /* Flag indicates whether this connector supports HDCP2.2 or not. */
568 bool hdcp2_supported;
569
570 /* HDCP2.2 Encryption status */
571 bool hdcp2_encrypted;
572
573 /*
574 * Content Stream Type defined by content owner. TYPE0(0x0) content can
575 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
576 * content can flow only through a link protected by HDCP2.2.
577 */
578 u8 content_type;
579
580 bool is_paired;
581 bool is_repeater;
582
583 /*
584 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
585 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
586 * When it rolls over re-auth has to be triggered.
587 */
588 u32 seq_num_v;
589
590 /*
591 * Count of RepeaterAuth_Stream_Manage msg propagated.
592 * Initialized to 0 on AKE_INIT. Incremented after every successful
593 * transmission of RepeaterAuth_Stream_Manage message. When it rolls
594 * over re-Auth has to be triggered.
595 */
596 u32 seq_num_m;
597
598 /*
599 * Work queue to signal the CP_IRQ. Used for the waiters to read the
600 * available information from HDCP DP sink.
601 */
602 wait_queue_head_t cp_irq_queue;
603 atomic_t cp_irq_count;
604 int cp_irq_count_cached;
605
606 /*
607 * HDCP register access for gen12+ need the transcoder associated.
608 * Transcoder attached to the connector could be changed at modeset.
609 * Hence caching the transcoder here.
610 */
611 enum transcoder cpu_transcoder;
612 /* Only used for DP MST stream encryption */
613 enum transcoder stream_transcoder;
614 };
615
616 struct intel_connector {
617 struct drm_connector base;
618 /*
619 * The fixed encoder this connector is connected to.
620 */
621 struct intel_encoder *encoder;
622
623 /* ACPI device id for ACPI and driver cooperation */
624 u32 acpi_device_id;
625
626 /* Reads out the current hw, returning true if the connector is enabled
627 * and active (i.e. dpms ON state). */
628 bool (*get_hw_state)(struct intel_connector *);
629
630 /*
631 * Optional hook called during init/resume to sync any state
632 * stored in the connector (eg. DSC state) wrt. the HW state.
633 */
634 void (*sync_state)(struct intel_connector *connector,
635 const struct intel_crtc_state *crtc_state);
636
637 /* Panel info for eDP and LVDS */
638 struct intel_panel panel;
639
640 /* Cached EDID for detect. */
641 const struct drm_edid *detect_edid;
642
643 /* Number of times hotplug detection was tried after an HPD interrupt */
644 int hotplug_retries;
645
646 /* since POLL and HPD connectors may use the same HPD line keep the native
647 state of connector->polled in case hotplug storm detection changes it */
648 u8 polled;
649
650 struct drm_dp_mst_port *port;
651
652 struct intel_dp *mst_port;
653
654 bool force_bigjoiner_enable;
655
656 struct {
657 struct drm_dp_aux *dsc_decompression_aux;
658 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
659 u8 fec_capability;
660
661 u8 dsc_hblank_expansion_quirk:1;
662 u8 dsc_decompression_enabled:1;
663 } dp;
664
665 /* Work struct to schedule a uevent on link train failure */
666 struct work_struct modeset_retry_work;
667
668 struct intel_hdcp hdcp;
669 };
670
671 struct intel_digital_connector_state {
672 struct drm_connector_state base;
673
674 enum hdmi_force_audio force_audio;
675 int broadcast_rgb;
676 };
677
678 #define to_intel_digital_connector_state(conn_state) \
679 container_of_const((conn_state), struct intel_digital_connector_state, base)
680
681 struct dpll {
682 /* given values */
683 int n;
684 int m1, m2;
685 int p1, p2;
686 /* derived values */
687 int dot;
688 int vco;
689 int m;
690 int p;
691 };
692
693 struct intel_atomic_state {
694 struct drm_atomic_state base;
695
696 intel_wakeref_t wakeref;
697
698 struct __intel_global_objs_state *global_objs;
699 int num_global_objs;
700
701 /* Internal commit, as opposed to userspace/client initiated one */
702 bool internal;
703
704 bool dpll_set, modeset;
705
706 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
707
708 struct intel_dp_tunnel_inherited_state *inherited_dp_tunnels;
709
710 /*
711 * Current watermarks can't be trusted during hardware readout, so
712 * don't bother calculating intermediate watermarks.
713 */
714 bool skip_intermediate_wm;
715
716 bool rps_interactive;
717 };
718
719 struct intel_plane_state {
720 struct drm_plane_state uapi;
721
722 /*
723 * actual hardware state, the state we program to the hardware.
724 * The following members are used to verify the hardware state:
725 * During initial hw readout, they need to be copied from uapi.
726 */
727 struct {
728 struct drm_crtc *crtc;
729 struct drm_framebuffer *fb;
730
731 u16 alpha;
732 u16 pixel_blend_mode;
733 unsigned int rotation;
734 enum drm_color_encoding color_encoding;
735 enum drm_color_range color_range;
736 enum drm_scaling_filter scaling_filter;
737 } hw;
738
739 struct i915_vma *ggtt_vma;
740 struct i915_vma *dpt_vma;
741 unsigned long flags;
742 #define PLANE_HAS_FENCE BIT(0)
743
744 struct intel_fb_view view;
745 u32 phys_dma_addr; /* for cursor_needs_physical */
746
747 /* for legacy cursor fb unpin */
748 struct drm_vblank_work unpin_work;
749
750 /* Plane pxp decryption state */
751 bool decrypt;
752
753 /* Plane state to display black pixels when pxp is borked */
754 bool force_black;
755
756 /* plane control register */
757 u32 ctl;
758
759 /* plane color control register */
760 u32 color_ctl;
761
762 /* chroma upsampler control register */
763 u32 cus_ctl;
764
765 /*
766 * scaler_id
767 * = -1 : not using a scaler
768 * >= 0 : using a scalers
769 *
770 * plane requiring a scaler:
771 * - During check_plane, its bit is set in
772 * crtc_state->scaler_state.scaler_users by calling helper function
773 * update_scaler_plane.
774 * - scaler_id indicates the scaler it got assigned.
775 *
776 * plane doesn't require a scaler:
777 * - this can happen when scaling is no more required or plane simply
778 * got disabled.
779 * - During check_plane, corresponding bit is reset in
780 * crtc_state->scaler_state.scaler_users by calling helper function
781 * update_scaler_plane.
782 */
783 int scaler_id;
784
785 /*
786 * planar_linked_plane:
787 *
788 * ICL planar formats require 2 planes that are updated as pairs.
789 * This member is used to make sure the other plane is also updated
790 * when required, and for update_slave() to find the correct
791 * plane_state to pass as argument.
792 */
793 struct intel_plane *planar_linked_plane;
794
795 /*
796 * planar_slave:
797 * If set don't update use the linked plane's state for updating
798 * this plane during atomic commit with the update_slave() callback.
799 *
800 * It's also used by the watermark code to ignore wm calculations on
801 * this plane. They're calculated by the linked plane's wm code.
802 */
803 u32 planar_slave;
804
805 struct drm_intel_sprite_colorkey ckey;
806
807 struct drm_rect psr2_sel_fetch_area;
808
809 /* Clear Color Value */
810 u64 ccval;
811
812 const char *no_fbc_reason;
813 };
814
815 struct intel_initial_plane_config {
816 struct intel_framebuffer *fb;
817 struct intel_memory_region *mem;
818 resource_size_t phys_base;
819 struct i915_vma *vma;
820 unsigned int tiling;
821 int size;
822 u32 base;
823 u8 rotation;
824 };
825
826 struct intel_scaler {
827 int in_use;
828 u32 mode;
829 };
830
831 struct intel_crtc_scaler_state {
832 #define SKL_NUM_SCALERS 2
833 struct intel_scaler scalers[SKL_NUM_SCALERS];
834
835 /*
836 * scaler_users: keeps track of users requesting scalers on this crtc.
837 *
838 * If a bit is set, a user is using a scaler.
839 * Here user can be a plane or crtc as defined below:
840 * bits 0-30 - plane (bit position is index from drm_plane_index)
841 * bit 31 - crtc
842 *
843 * Instead of creating a new index to cover planes and crtc, using
844 * existing drm_plane_index for planes which is well less than 31
845 * planes and bit 31 for crtc. This should be fine to cover all
846 * our platforms.
847 *
848 * intel_atomic_setup_scalers will setup available scalers to users
849 * requesting scalers. It will gracefully fail if request exceeds
850 * avilability.
851 */
852 #define SKL_CRTC_INDEX 31
853 unsigned scaler_users;
854
855 /* scaler used by crtc for panel fitting purpose */
856 int scaler_id;
857 };
858
859 /* {crtc,crtc_state}->mode_flags */
860 /* Flag to get scanline using frame time stamps */
861 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
862 /* Flag to use the scanline counter instead of the pixel counter */
863 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
864 /*
865 * TE0 or TE1 flag is set if the crtc has a DSI encoder which
866 * is operating in command mode.
867 * Flag to use TE from DSI0 instead of VBI in command mode
868 */
869 #define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
870 /* Flag to use TE from DSI1 instead of VBI in command mode */
871 #define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
872 /* Flag to indicate mipi dsi periodic command mode where we do not get TE */
873 #define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
874 /* Do tricks to make vblank timestamps sane with VRR? */
875 #define I915_MODE_FLAG_VRR (1<<6)
876
877 struct intel_wm_level {
878 bool enable;
879 u32 pri_val;
880 u32 spr_val;
881 u32 cur_val;
882 u32 fbc_val;
883 };
884
885 struct intel_pipe_wm {
886 struct intel_wm_level wm[5];
887 bool fbc_wm_enabled;
888 bool pipe_enabled;
889 bool sprites_enabled;
890 bool sprites_scaled;
891 };
892
893 struct skl_wm_level {
894 u16 min_ddb_alloc;
895 u16 blocks;
896 u8 lines;
897 bool enable;
898 bool ignore_lines;
899 bool can_sagv;
900 };
901
902 struct skl_plane_wm {
903 struct skl_wm_level wm[8];
904 struct skl_wm_level uv_wm[8];
905 struct skl_wm_level trans_wm;
906 struct {
907 struct skl_wm_level wm0;
908 struct skl_wm_level trans_wm;
909 } sagv;
910 bool is_planar;
911 };
912
913 struct skl_pipe_wm {
914 struct skl_plane_wm planes[I915_MAX_PLANES];
915 bool use_sagv_wm;
916 };
917
918 enum vlv_wm_level {
919 VLV_WM_LEVEL_PM2,
920 VLV_WM_LEVEL_PM5,
921 VLV_WM_LEVEL_DDR_DVFS,
922 NUM_VLV_WM_LEVELS,
923 };
924
925 struct vlv_wm_state {
926 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
927 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
928 u8 num_levels;
929 bool cxsr;
930 };
931
932 struct vlv_fifo_state {
933 u16 plane[I915_MAX_PLANES];
934 };
935
936 enum g4x_wm_level {
937 G4X_WM_LEVEL_NORMAL,
938 G4X_WM_LEVEL_SR,
939 G4X_WM_LEVEL_HPLL,
940 NUM_G4X_WM_LEVELS,
941 };
942
943 struct g4x_wm_state {
944 struct g4x_pipe_wm wm;
945 struct g4x_sr_wm sr;
946 struct g4x_sr_wm hpll;
947 bool cxsr;
948 bool hpll_en;
949 bool fbc_en;
950 };
951
952 struct intel_crtc_wm_state {
953 union {
954 /*
955 * raw:
956 * The "raw" watermark values produced by the formula
957 * given the plane's current state. They do not consider
958 * how much FIFO is actually allocated for each plane.
959 *
960 * optimal:
961 * The "optimal" watermark values given the current
962 * state of the planes and the amount of FIFO
963 * allocated to each, ignoring any previous state
964 * of the planes.
965 *
966 * intermediate:
967 * The "intermediate" watermark values when transitioning
968 * between the old and new "optimal" values. Used when
969 * the watermark registers are single buffered and hence
970 * their state changes asynchronously with regards to the
971 * actual plane registers. These are essentially the
972 * worst case combination of the old and new "optimal"
973 * watermarks, which are therefore safe to use when the
974 * plane is in either its old or new state.
975 */
976 struct {
977 struct intel_pipe_wm intermediate;
978 struct intel_pipe_wm optimal;
979 } ilk;
980
981 struct {
982 struct skl_pipe_wm raw;
983 /* gen9+ only needs 1-step wm programming */
984 struct skl_pipe_wm optimal;
985 struct skl_ddb_entry ddb;
986 /*
987 * pre-icl: for packed/planar CbCr
988 * icl+: for everything
989 */
990 struct skl_ddb_entry plane_ddb[I915_MAX_PLANES];
991 /* pre-icl: for planar Y */
992 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
993 } skl;
994
995 struct {
996 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; /* not inverted */
997 struct vlv_wm_state intermediate; /* inverted */
998 struct vlv_wm_state optimal; /* inverted */
999 struct vlv_fifo_state fifo_state;
1000 } vlv;
1001
1002 struct {
1003 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
1004 struct g4x_wm_state intermediate;
1005 struct g4x_wm_state optimal;
1006 } g4x;
1007 };
1008
1009 /*
1010 * Platforms with two-step watermark programming will need to
1011 * update watermark programming post-vblank to switch from the
1012 * safe intermediate watermarks to the optimal final
1013 * watermarks.
1014 */
1015 bool need_postvbl_update;
1016 };
1017
1018 enum intel_output_format {
1019 INTEL_OUTPUT_FORMAT_RGB,
1020 INTEL_OUTPUT_FORMAT_YCBCR420,
1021 INTEL_OUTPUT_FORMAT_YCBCR444,
1022 };
1023
1024 /* Used by dp and fdi links */
1025 struct intel_link_m_n {
1026 u32 tu;
1027 u32 data_m;
1028 u32 data_n;
1029 u32 link_m;
1030 u32 link_n;
1031 };
1032
1033 struct intel_csc_matrix {
1034 u16 coeff[9];
1035 u16 preoff[3];
1036 u16 postoff[3];
1037 };
1038
1039 void intel_io_mmio_fw_write(void *ctx, i915_reg_t reg, u32 val);
1040
1041 typedef void (*intel_io_reg_write)(void *ctx, i915_reg_t reg, u32 val);
1042
1043 struct intel_crtc_state {
1044 /*
1045 * uapi (drm) state. This is the software state shown to userspace.
1046 * In particular, the following members are used for bookkeeping:
1047 * - crtc
1048 * - state
1049 * - *_changed
1050 * - event
1051 * - commit
1052 * - mode_blob
1053 */
1054 struct drm_crtc_state uapi;
1055
1056 /*
1057 * actual hardware state, the state we program to the hardware.
1058 * The following members are used to verify the hardware state:
1059 * - enable
1060 * - active
1061 * - mode / pipe_mode / adjusted_mode
1062 * - color property blobs.
1063 *
1064 * During initial hw readout, they need to be copied to uapi.
1065 *
1066 * Joiner will allow a transcoder mode that spans 2 pipes;
1067 * Use the pipe_mode for calculations like watermarks, pipe
1068 * scaler, and bandwidth.
1069 *
1070 * Use adjusted_mode for things that need to know the full
1071 * mode on the transcoder, which spans all pipes.
1072 */
1073 struct {
1074 bool active, enable;
1075 /* logical state of LUTs */
1076 struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
1077 struct drm_display_mode mode, pipe_mode, adjusted_mode;
1078 enum drm_scaling_filter scaling_filter;
1079 } hw;
1080
1081 /* actual state of LUTs */
1082 struct drm_property_blob *pre_csc_lut, *post_csc_lut;
1083
1084 struct intel_csc_matrix csc, output_csc;
1085
1086 /**
1087 * quirks - bitfield with hw state readout quirks
1088 *
1089 * For various reasons the hw state readout code might not be able to
1090 * completely faithfully read out the current state. These cases are
1091 * tracked with quirk flags so that fastboot and state checker can act
1092 * accordingly.
1093 */
1094 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
1095 unsigned long quirks;
1096
1097 unsigned fb_bits; /* framebuffers to flip */
1098 bool update_pipe; /* can a fast modeset be performed? */
1099 bool update_m_n; /* update M/N seamlessly during fastset? */
1100 bool update_lrr; /* update TRANS_VTOTAL/etc. during fastset? */
1101 bool disable_cxsr;
1102 bool update_wm_pre, update_wm_post; /* watermarks are updated */
1103 bool fifo_changed; /* FIFO split is changed */
1104 bool preload_luts;
1105 bool inherited; /* state inherited from BIOS? */
1106
1107 /* Ask the hardware to actually async flip? */
1108 bool do_async_flip;
1109
1110 /* Pipe source size (ie. panel fitter input size)
1111 * All planes will be positioned inside this space,
1112 * and get clipped at the edges. */
1113 struct drm_rect pipe_src;
1114
1115 /*
1116 * Pipe pixel rate, adjusted for
1117 * panel fitter/pipe scaler downscaling.
1118 */
1119 unsigned int pixel_rate;
1120
1121 /* Whether to set up the PCH/FDI. Note that we never allow sharing
1122 * between pch encoders and cpu encoders. */
1123 bool has_pch_encoder;
1124
1125 /* Are we sending infoframes on the attached port */
1126 bool has_infoframe;
1127
1128 /* CPU Transcoder for the pipe. Currently this can only differ from the
1129 * pipe on Haswell and later (where we have a special eDP transcoder)
1130 * and Broxton (where we have special DSI transcoders). */
1131 enum transcoder cpu_transcoder;
1132
1133 /*
1134 * Use reduced/limited/broadcast rbg range, compressing from the full
1135 * range fed into the crtcs.
1136 */
1137 bool limited_color_range;
1138
1139 /* Bitmask of encoder types (enum intel_output_type)
1140 * driven by the pipe.
1141 */
1142 unsigned int output_types;
1143
1144 /* Whether we should send NULL infoframes. Required for audio. */
1145 bool has_hdmi_sink;
1146
1147 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
1148 * has_dp_encoder is set. */
1149 bool has_audio;
1150
1151 /*
1152 * Enable dithering, used when the selected pipe bpp doesn't match the
1153 * plane bpp.
1154 */
1155 bool dither;
1156
1157 /*
1158 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
1159 * compliance video pattern tests.
1160 * Disable dither only if it is a compliance test request for
1161 * 18bpp.
1162 */
1163 bool dither_force_disable;
1164
1165 /* Controls for the clock computation, to override various stages. */
1166 bool clock_set;
1167
1168 /* SDVO TV has a bunch of special case. To make multifunction encoders
1169 * work correctly, we need to track this at runtime.*/
1170 bool sdvo_tv_clock;
1171
1172 /*
1173 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
1174 * required. This is set in the 2nd loop of calling encoder's
1175 * ->compute_config if the first pick doesn't work out.
1176 */
1177 bool bw_constrained;
1178
1179 /* Settings for the intel dpll used on pretty much everything but
1180 * haswell. */
1181 struct dpll dpll;
1182
1183 /* Selected dpll when shared or NULL. */
1184 struct intel_shared_dpll *shared_dpll;
1185
1186 /* Actual register state of the dpll, for shared dpll cross-checking. */
1187 struct intel_dpll_hw_state dpll_hw_state;
1188
1189 /*
1190 * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by
1191 * setting shared_dpll and dpll_hw_state to one of these reserved ones.
1192 */
1193 struct icl_port_dpll {
1194 struct intel_shared_dpll *pll;
1195 struct intel_dpll_hw_state hw_state;
1196 } icl_port_dplls[ICL_PORT_DPLL_COUNT];
1197
1198 /* DSI PLL registers */
1199 struct {
1200 u32 ctrl, div;
1201 } dsi_pll;
1202
1203 int max_link_bpp_x16; /* in 1/16 bpp units */
1204 int pipe_bpp; /* in 1 bpp units */
1205 struct intel_link_m_n dp_m_n;
1206
1207 /* m2_n2 for eDP downclock */
1208 struct intel_link_m_n dp_m2_n2;
1209 bool has_drrs;
1210
1211 /* PSR is supported but might not be enabled due the lack of enabled planes */
1212 bool has_psr;
1213 bool has_sel_update;
1214 bool enable_psr2_sel_fetch;
1215 bool enable_psr2_su_region_et;
1216 bool req_psr2_sdp_prior_scanline;
1217 bool has_panel_replay;
1218 bool wm_level_disabled;
1219 u32 dc3co_exitline;
1220 u16 su_y_granularity;
1221
1222 /*
1223 * Frequence the dpll for the port should run at. Differs from the
1224 * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also
1225 * already multiplied by pixel_multiplier.
1226 */
1227 int port_clock;
1228
1229 /* Used by SDVO (and if we ever fix it, HDMI). */
1230 unsigned pixel_multiplier;
1231
1232 /* I915_MODE_FLAG_* */
1233 u8 mode_flags;
1234
1235 u8 lane_count;
1236
1237 /*
1238 * Used by platforms having DP/HDMI PHY with programmable lane
1239 * latency optimization.
1240 */
1241 u8 lane_lat_optim_mask;
1242
1243 /* minimum acceptable voltage level */
1244 u8 min_voltage_level;
1245
1246 /* Panel fitter controls for gen2-gen4 + VLV */
1247 struct {
1248 u32 control;
1249 u32 pgm_ratios;
1250 u32 lvds_border_bits;
1251 } gmch_pfit;
1252
1253 /* Panel fitter placement and size for Ironlake+ */
1254 struct {
1255 struct drm_rect dst;
1256 bool enabled;
1257 bool force_thru;
1258 } pch_pfit;
1259
1260 /* FDI configuration, only valid if has_pch_encoder is set. */
1261 int fdi_lanes;
1262 struct intel_link_m_n fdi_m_n;
1263
1264 bool ips_enabled;
1265
1266 bool crc_enabled;
1267
1268 bool double_wide;
1269
1270 int pbn;
1271
1272 struct intel_crtc_scaler_state scaler_state;
1273
1274 /* w/a for waiting 2 vblanks during crtc enable */
1275 enum pipe hsw_workaround_pipe;
1276
1277 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
1278 bool disable_lp_wm;
1279
1280 struct intel_crtc_wm_state wm;
1281
1282 int min_cdclk[I915_MAX_PLANES];
1283
1284 /* for packed/planar CbCr */
1285 u32 data_rate[I915_MAX_PLANES];
1286 /* for planar Y */
1287 u32 data_rate_y[I915_MAX_PLANES];
1288
1289 /* FIXME unify with data_rate[]? */
1290 u64 rel_data_rate[I915_MAX_PLANES];
1291 u64 rel_data_rate_y[I915_MAX_PLANES];
1292
1293 /* Gamma mode programmed on the pipe */
1294 u32 gamma_mode;
1295
1296 union {
1297 /* CSC mode programmed on the pipe */
1298 u32 csc_mode;
1299
1300 /* CHV CGM mode */
1301 u32 cgm_mode;
1302 };
1303
1304 /* bitmask of logically enabled planes (enum plane_id) */
1305 u8 enabled_planes;
1306
1307 /* bitmask of actually visible planes (enum plane_id) */
1308 u8 active_planes;
1309 u8 scaled_planes;
1310 u8 nv12_planes;
1311 u8 c8_planes;
1312
1313 /* bitmask of planes that will be updated during the commit */
1314 u8 update_planes;
1315
1316 /* bitmask of planes with async flip active */
1317 u8 async_flip_planes;
1318
1319 u8 framestart_delay; /* 1-4 */
1320 u8 msa_timing_delay; /* 0-3 */
1321
1322 struct {
1323 u32 enable;
1324 u32 gcp;
1325 union hdmi_infoframe avi;
1326 union hdmi_infoframe spd;
1327 union hdmi_infoframe hdmi;
1328 union hdmi_infoframe drm;
1329 struct drm_dp_vsc_sdp vsc;
1330 struct drm_dp_as_sdp as_sdp;
1331 } infoframes;
1332
1333 u8 eld[MAX_ELD_BYTES];
1334
1335 /* HDMI scrambling status */
1336 bool hdmi_scrambling;
1337
1338 /* HDMI High TMDS char rate ratio */
1339 bool hdmi_high_tmds_clock_ratio;
1340
1341 /*
1342 * Output format RGB/YCBCR etc., that is coming out
1343 * at the end of the pipe.
1344 */
1345 enum intel_output_format output_format;
1346
1347 /*
1348 * Sink output format RGB/YCBCR etc., that is going
1349 * into the sink.
1350 */
1351 enum intel_output_format sink_format;
1352
1353 /* enable pipe gamma? */
1354 bool gamma_enable;
1355
1356 /* enable pipe csc? */
1357 bool csc_enable;
1358
1359 /* enable vlv/chv wgc csc? */
1360 bool wgc_enable;
1361
1362 /* joiner pipe bitmask */
1363 u8 joiner_pipes;
1364
1365 /* Display Stream compression state */
1366 struct {
1367 bool compression_enable;
1368 bool dsc_split;
1369 /* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */
1370 u16 compressed_bpp_x16;
1371 u8 slice_count;
1372 struct drm_dsc_config config;
1373 } dsc;
1374
1375 /* DP tunnel used for BW allocation. */
1376 struct drm_dp_tunnel_ref dp_tunnel_ref;
1377
1378 /* HSW+ linetime watermarks */
1379 u16 linetime;
1380 u16 ips_linetime;
1381
1382 bool enhanced_framing;
1383
1384 /*
1385 * Forward Error Correction.
1386 *
1387 * Note: This will be false for 128b/132b, which will always have FEC
1388 * enabled automatically.
1389 */
1390 bool fec_enable;
1391
1392 bool sdp_split_enable;
1393
1394 /* Pointer to master transcoder in case of tiled displays */
1395 enum transcoder master_transcoder;
1396
1397 /* Bitmask to indicate slaves attached */
1398 u8 sync_mode_slaves_mask;
1399
1400 /* Only valid on TGL+ */
1401 enum transcoder mst_master_transcoder;
1402
1403 /* For DSB based color LUT updates */
1404 struct intel_dsb *dsb_color_vblank, *dsb_color_commit;
1405
1406 u32 psr2_man_track_ctl;
1407
1408 u32 pipe_srcsz_early_tpt;
1409
1410 struct drm_rect psr2_su_area;
1411
1412 /* Variable Refresh Rate state */
1413 struct {
1414 bool enable, in_range;
1415 u8 pipeline_full;
1416 u16 flipline, vmin, vmax, guardband;
1417 u32 vsync_end, vsync_start;
1418 } vrr;
1419
1420 /* Content Match Refresh Rate state */
1421 struct {
1422 bool enable;
1423 u64 cmrr_n, cmrr_m;
1424 } cmrr;
1425
1426 /* Stream Splitter for eDP MSO */
1427 struct {
1428 bool enable;
1429 u8 link_count;
1430 u8 pixel_overlap;
1431 } splitter;
1432
1433 /* for loading single buffered registers during vblank */
1434 struct drm_vblank_work vblank_work;
1435
1436 /* LOBF flag */
1437 bool has_lobf;
1438 };
1439
1440 enum intel_pipe_crc_source {
1441 INTEL_PIPE_CRC_SOURCE_NONE,
1442 INTEL_PIPE_CRC_SOURCE_PLANE1,
1443 INTEL_PIPE_CRC_SOURCE_PLANE2,
1444 INTEL_PIPE_CRC_SOURCE_PLANE3,
1445 INTEL_PIPE_CRC_SOURCE_PLANE4,
1446 INTEL_PIPE_CRC_SOURCE_PLANE5,
1447 INTEL_PIPE_CRC_SOURCE_PLANE6,
1448 INTEL_PIPE_CRC_SOURCE_PLANE7,
1449 INTEL_PIPE_CRC_SOURCE_PIPE,
1450 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1451 INTEL_PIPE_CRC_SOURCE_TV,
1452 INTEL_PIPE_CRC_SOURCE_DP_B,
1453 INTEL_PIPE_CRC_SOURCE_DP_C,
1454 INTEL_PIPE_CRC_SOURCE_DP_D,
1455 INTEL_PIPE_CRC_SOURCE_AUTO,
1456 INTEL_PIPE_CRC_SOURCE_MAX,
1457 };
1458
1459 enum drrs_refresh_rate {
1460 DRRS_REFRESH_RATE_HIGH,
1461 DRRS_REFRESH_RATE_LOW,
1462 };
1463
1464 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1465 struct intel_pipe_crc {
1466 spinlock_t lock;
1467 int skipped;
1468 enum intel_pipe_crc_source source;
1469 };
1470
1471 struct intel_crtc {
1472 struct drm_crtc base;
1473 enum pipe pipe;
1474 /*
1475 * Whether the crtc and the connected output pipeline is active. Implies
1476 * that crtc->enabled is set, i.e. the current mode configuration has
1477 * some outputs connected to this crtc.
1478 */
1479 bool active;
1480 u8 plane_ids_mask;
1481
1482 /* I915_MODE_FLAG_* */
1483 u8 mode_flags;
1484
1485 u16 vmax_vblank_start;
1486
1487 struct intel_display_power_domain_set enabled_power_domains;
1488 struct intel_display_power_domain_set hw_readout_power_domains;
1489 struct intel_overlay *overlay;
1490
1491 struct intel_crtc_state *config;
1492
1493 /* armed event for async flip */
1494 struct drm_pending_vblank_event *flip_done_event;
1495
1496 /* Access to these should be protected by dev_priv->irq_lock. */
1497 bool cpu_fifo_underrun_disabled;
1498 bool pch_fifo_underrun_disabled;
1499
1500 /* per-pipe watermark state */
1501 struct {
1502 /* watermarks currently being used */
1503 union {
1504 struct intel_pipe_wm ilk;
1505 struct vlv_wm_state vlv;
1506 struct g4x_wm_state g4x;
1507 } active;
1508 } wm;
1509
1510 struct {
1511 struct mutex mutex;
1512 struct delayed_work work;
1513 enum drrs_refresh_rate refresh_rate;
1514 unsigned int frontbuffer_bits;
1515 unsigned int busy_frontbuffer_bits;
1516 enum transcoder cpu_transcoder;
1517 struct intel_link_m_n m_n, m2_n2;
1518 } drrs;
1519
1520 int scanline_offset;
1521
1522 struct {
1523 unsigned start_vbl_count;
1524 ktime_t start_vbl_time;
1525 int min_vbl, max_vbl;
1526 int scanline_start;
1527 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
1528 struct {
1529 u64 min;
1530 u64 max;
1531 u64 sum;
1532 unsigned int over;
1533 unsigned int times[17]; /* [1us, 16ms] */
1534 } vbl;
1535 #endif
1536 } debug;
1537
1538 /* scalers available on this crtc */
1539 int num_scalers;
1540
1541 /* for loading single buffered registers during vblank */
1542 struct pm_qos_request vblank_pm_qos;
1543
1544 #ifdef CONFIG_DEBUG_FS
1545 struct intel_pipe_crc pipe_crc;
1546 #endif
1547 };
1548
1549 struct intel_plane {
1550 struct drm_plane base;
1551 enum i9xx_plane_id i9xx_plane;
1552 enum plane_id id;
1553 enum pipe pipe;
1554 bool need_async_flip_toggle_wa;
1555 u32 frontbuffer_bit;
1556
1557 struct {
1558 u32 base, cntl, size;
1559 } cursor;
1560
1561 struct intel_fbc *fbc;
1562
1563 /*
1564 * NOTE: Do not place new plane state fields here (e.g., when adding
1565 * new plane properties). New runtime state should now be placed in
1566 * the intel_plane_state structure and accessed via plane_state.
1567 */
1568
1569 int (*min_width)(const struct drm_framebuffer *fb,
1570 int color_plane,
1571 unsigned int rotation);
1572 int (*max_width)(const struct drm_framebuffer *fb,
1573 int color_plane,
1574 unsigned int rotation);
1575 int (*max_height)(const struct drm_framebuffer *fb,
1576 int color_plane,
1577 unsigned int rotation);
1578 unsigned int (*min_alignment)(struct intel_plane *plane,
1579 const struct drm_framebuffer *fb,
1580 int color_plane);
1581 unsigned int (*max_stride)(struct intel_plane *plane,
1582 u32 pixel_format, u64 modifier,
1583 unsigned int rotation);
1584 /* Write all non-self arming plane registers */
1585 void (*update_noarm)(struct intel_dsb *dsb,
1586 struct intel_plane *plane,
1587 const struct intel_crtc_state *crtc_state,
1588 const struct intel_plane_state *plane_state);
1589 /* Write all self-arming plane registers */
1590 void (*update_arm)(struct intel_dsb *dsb,
1591 struct intel_plane *plane,
1592 const struct intel_crtc_state *crtc_state,
1593 const struct intel_plane_state *plane_state);
1594 /* Disable the plane, must arm */
1595 void (*disable_arm)(struct intel_dsb *dsb,
1596 struct intel_plane *plane,
1597 const struct intel_crtc_state *crtc_state);
1598 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1599 int (*check_plane)(struct intel_crtc_state *crtc_state,
1600 struct intel_plane_state *plane_state);
1601 int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
1602 const struct intel_plane_state *plane_state);
1603 void (*async_flip)(struct intel_dsb *dsb,
1604 struct intel_plane *plane,
1605 const struct intel_crtc_state *crtc_state,
1606 const struct intel_plane_state *plane_state,
1607 bool async_flip);
1608 void (*enable_flip_done)(struct intel_plane *plane);
1609 void (*disable_flip_done)(struct intel_plane *plane);
1610 };
1611
1612 struct intel_watermark_params {
1613 u16 fifo_size;
1614 u16 max_wm;
1615 u8 default_wm;
1616 u8 guard_size;
1617 u8 cacheline_size;
1618 };
1619
1620 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1621 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1622 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1623 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1624 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1625
1626 #define to_intel_crtc_state(crtc_state) \
1627 container_of_const((crtc_state), struct intel_crtc_state, uapi)
1628 #define to_intel_plane_state(plane_state) \
1629 container_of_const((plane_state), struct intel_plane_state, uapi)
1630 #define to_intel_framebuffer(fb) \
1631 container_of_const((fb), struct intel_framebuffer, base)
1632
1633 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1634
1635 struct intel_hdmi {
1636 i915_reg_t hdmi_reg;
1637 struct {
1638 enum drm_dp_dual_mode_type type;
1639 int max_tmds_clock;
1640 } dp_dual_mode;
1641 struct intel_connector *attached_connector;
1642 struct cec_notifier *cec_notifier;
1643 };
1644
1645 struct intel_dp_mst_encoder;
1646
1647 struct intel_dp_compliance_data {
1648 unsigned long edid;
1649 u8 video_pattern;
1650 u16 hdisplay, vdisplay;
1651 u8 bpc;
1652 struct drm_dp_phy_test_params phytest;
1653 };
1654
1655 struct intel_dp_compliance {
1656 unsigned long test_type;
1657 struct intel_dp_compliance_data test_data;
1658 bool test_active;
1659 int test_link_rate;
1660 u8 test_lane_count;
1661 };
1662
1663 struct intel_dp_pcon_frl {
1664 bool is_trained;
1665 int trained_rate_gbps;
1666 };
1667
1668 struct intel_pps {
1669 int panel_power_up_delay;
1670 int panel_power_down_delay;
1671 int panel_power_cycle_delay;
1672 int backlight_on_delay;
1673 int backlight_off_delay;
1674 struct delayed_work panel_vdd_work;
1675 bool want_panel_vdd;
1676 bool initializing;
1677 unsigned long last_power_on;
1678 unsigned long last_backlight_off;
1679 ktime_t panel_power_off_time;
1680 intel_wakeref_t vdd_wakeref;
1681
1682 union {
1683 /*
1684 * Pipe whose power sequencer is currently locked into
1685 * this port. Only relevant on VLV/CHV.
1686 */
1687 enum pipe pps_pipe;
1688
1689 /*
1690 * Power sequencer index. Only relevant on BXT+.
1691 */
1692 int pps_idx;
1693 };
1694
1695 /*
1696 * Pipe currently driving the port. Used for preventing
1697 * the use of the PPS for any pipe currentrly driving
1698 * external DP as that will mess things up on VLV.
1699 */
1700 enum pipe active_pipe;
1701 /*
1702 * Set if the sequencer may be reset due to a power transition,
1703 * requiring a reinitialization. Only relevant on BXT+.
1704 */
1705 bool pps_reset;
1706 struct edp_power_seq pps_delays;
1707 struct edp_power_seq bios_pps_delays;
1708 };
1709
1710 struct intel_psr {
1711 /* Mutex for PSR state of the transcoder */
1712 struct mutex lock;
1713
1714 #define I915_PSR_DEBUG_MODE_MASK 0x0f
1715 #define I915_PSR_DEBUG_DEFAULT 0x00
1716 #define I915_PSR_DEBUG_DISABLE 0x01
1717 #define I915_PSR_DEBUG_ENABLE 0x02
1718 #define I915_PSR_DEBUG_FORCE_PSR1 0x03
1719 #define I915_PSR_DEBUG_ENABLE_SEL_FETCH 0x4
1720 #define I915_PSR_DEBUG_IRQ 0x10
1721 #define I915_PSR_DEBUG_SU_REGION_ET_DISABLE 0x20
1722 #define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
1723
1724 u32 debug;
1725 bool sink_support;
1726 bool source_support;
1727 bool enabled;
1728 bool paused;
1729 enum pipe pipe;
1730 enum transcoder transcoder;
1731 bool active;
1732 struct work_struct work;
1733 unsigned int busy_frontbuffer_bits;
1734 bool sink_psr2_support;
1735 bool link_standby;
1736 bool sel_update_enabled;
1737 bool psr2_sel_fetch_enabled;
1738 bool psr2_sel_fetch_cff_enabled;
1739 bool su_region_et_enabled;
1740 bool req_psr2_sdp_prior_scanline;
1741 u8 sink_sync_latency;
1742 ktime_t last_entry_attempt;
1743 ktime_t last_exit;
1744 bool sink_not_reliable;
1745 bool irq_aux_error;
1746 u16 su_w_granularity;
1747 u16 su_y_granularity;
1748 bool source_panel_replay_support;
1749 bool sink_panel_replay_support;
1750 bool sink_panel_replay_su_support;
1751 bool panel_replay_enabled;
1752 u32 dc3co_exitline;
1753 u32 dc3co_exit_delay;
1754 struct delayed_work dc3co_work;
1755 u8 entry_setup_frames;
1756 };
1757
1758 struct intel_dp {
1759 i915_reg_t output_reg;
1760 u32 DP;
1761 int link_rate;
1762 u8 lane_count;
1763 u8 sink_count;
1764 bool link_trained;
1765 bool needs_modeset_retry;
1766 bool use_max_params;
1767 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1768 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1769 u8 pr_dpcd;
1770 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1771 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1772 u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
1773 u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
1774 u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
1775 /* source rates */
1776 int num_source_rates;
1777 const int *source_rates;
1778 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1779 int num_sink_rates;
1780 int sink_rates[DP_MAX_SUPPORTED_RATES];
1781 bool use_rate_select;
1782 /* Max sink lane count as reported by DP_MAX_LANE_COUNT */
1783 int max_sink_lane_count;
1784 /* intersection of source and sink rates */
1785 int num_common_rates;
1786 int common_rates[DP_MAX_SUPPORTED_RATES];
1787 struct {
1788 /* TODO: move the rest of link specific fields to here */
1789 /* common rate,lane_count configs in bw order */
1790 int num_configs;
1791 #define INTEL_DP_MAX_LANE_COUNT 4
1792 #define INTEL_DP_MAX_SUPPORTED_LANE_CONFIGS (ilog2(INTEL_DP_MAX_LANE_COUNT) + 1)
1793 #define INTEL_DP_LANE_COUNT_EXP_BITS order_base_2(INTEL_DP_MAX_SUPPORTED_LANE_CONFIGS)
1794 #define INTEL_DP_LINK_RATE_IDX_BITS (BITS_PER_TYPE(u8) - INTEL_DP_LANE_COUNT_EXP_BITS)
1795 #define INTEL_DP_MAX_LINK_CONFIGS (DP_MAX_SUPPORTED_RATES * \
1796 INTEL_DP_MAX_SUPPORTED_LANE_CONFIGS)
1797 struct intel_dp_link_config {
1798 u8 link_rate_idx:INTEL_DP_LINK_RATE_IDX_BITS;
1799 u8 lane_count_exp:INTEL_DP_LANE_COUNT_EXP_BITS;
1800 } configs[INTEL_DP_MAX_LINK_CONFIGS];
1801 /* Max lane count for the current link */
1802 int max_lane_count;
1803 /* Max rate for the current link */
1804 int max_rate;
1805 /*
1806 * Link parameters for which the MST topology was probed.
1807 * Tracking these ensures that the MST path resources are
1808 * re-enumerated whenever the link is retrained with new link
1809 * parameters, as required by the DP standard.
1810 */
1811 int mst_probed_lane_count;
1812 int mst_probed_rate;
1813 int force_lane_count;
1814 int force_rate;
1815 bool retrain_disabled;
1816 /* Sequential link training failures after a passing LT */
1817 int seq_train_failures;
1818 int force_train_failure;
1819 bool force_retrain;
1820 } link;
1821 bool reset_link_params;
1822 int mso_link_count;
1823 int mso_pixel_overlap;
1824 /* sink or branch descriptor */
1825 struct drm_dp_desc desc;
1826 struct drm_dp_aux aux;
1827 u32 aux_busy_last_status;
1828 u8 train_set[4];
1829
1830 struct intel_pps pps;
1831
1832 bool is_mst;
1833 int active_mst_links;
1834 enum drm_dp_mst_mode mst_detect;
1835
1836 /* connector directly attached - won't be use for modeset in mst world */
1837 struct intel_connector *attached_connector;
1838 bool as_sdp_supported;
1839
1840 struct drm_dp_tunnel *tunnel;
1841 bool tunnel_suspended:1;
1842
1843 /* mst connector list */
1844 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1845 struct drm_dp_mst_topology_mgr mst_mgr;
1846
1847 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1848 /*
1849 * This function returns the value we have to program the AUX_CTL
1850 * register with to kick off an AUX transaction.
1851 */
1852 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1853 u32 aux_clock_divider);
1854
1855 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1856 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1857
1858 /* This is called before a link training is starterd */
1859 void (*prepare_link_retrain)(struct intel_dp *intel_dp,
1860 const struct intel_crtc_state *crtc_state);
1861 void (*set_link_train)(struct intel_dp *intel_dp,
1862 const struct intel_crtc_state *crtc_state,
1863 u8 dp_train_pat);
1864 void (*set_idle_link_train)(struct intel_dp *intel_dp,
1865 const struct intel_crtc_state *crtc_state);
1866
1867 u8 (*preemph_max)(struct intel_dp *intel_dp);
1868 u8 (*voltage_max)(struct intel_dp *intel_dp,
1869 const struct intel_crtc_state *crtc_state);
1870
1871 /* Displayport compliance testing */
1872 struct intel_dp_compliance compliance;
1873
1874 /* Downstream facing port caps */
1875 struct {
1876 int min_tmds_clock, max_tmds_clock;
1877 int max_dotclock;
1878 int pcon_max_frl_bw;
1879 u8 max_bpc;
1880 bool ycbcr_444_to_420;
1881 bool ycbcr420_passthrough;
1882 bool rgb_to_ycbcr;
1883 } dfp;
1884
1885 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1886 struct pm_qos_request pm_qos;
1887
1888 /* Display stream compression testing */
1889 bool force_dsc_en;
1890 int force_dsc_output_format;
1891 bool force_dsc_fractional_bpp_en;
1892 int force_dsc_bpc;
1893
1894 bool hobl_failed;
1895 bool hobl_active;
1896
1897 struct intel_dp_pcon_frl frl;
1898
1899 struct intel_psr psr;
1900
1901 /* When we last wrote the OUI for eDP */
1902 unsigned long last_oui_write;
1903
1904 bool colorimetry_support;
1905
1906 struct {
1907 u8 io_wake_lines;
1908 u8 fast_wake_lines;
1909
1910 /* LNL and beyond */
1911 u8 check_entry_lines;
1912 u8 aux_less_wake_lines;
1913 u8 silence_period_sym_clocks;
1914 u8 lfps_half_cycle_num_of_syms;
1915 } alpm_parameters;
1916
1917 u8 alpm_dpcd;
1918
1919 struct {
1920 unsigned long mask;
1921 } quirks;
1922 };
1923
1924 enum lspcon_vendor {
1925 LSPCON_VENDOR_MCA,
1926 LSPCON_VENDOR_PARADE
1927 };
1928
1929 struct intel_lspcon {
1930 bool active;
1931 bool hdr_supported;
1932 enum drm_lspcon_mode mode;
1933 enum lspcon_vendor vendor;
1934 };
1935
1936 struct intel_digital_port {
1937 struct intel_encoder base;
1938 u32 saved_port_bits;
1939 struct intel_dp dp;
1940 struct intel_hdmi hdmi;
1941 struct intel_lspcon lspcon;
1942 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1943 bool release_cl2_override;
1944 u8 max_lanes;
1945 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1946 enum aux_ch aux_ch;
1947 enum intel_display_power_domain ddi_io_power_domain;
1948 intel_wakeref_t ddi_io_wakeref;
1949 intel_wakeref_t aux_wakeref;
1950
1951 struct intel_tc_port *tc;
1952
1953 /* protects num_hdcp_streams reference count, hdcp_port_data and hdcp_auth_status */
1954 struct mutex hdcp_mutex;
1955 /* the number of pipes using HDCP signalling out of this port */
1956 unsigned int num_hdcp_streams;
1957 /* port HDCP auth status */
1958 bool hdcp_auth_status;
1959 /* HDCP port data need to pass to security f/w */
1960 struct hdcp_port_data hdcp_port_data;
1961 /* Whether the MST topology supports HDCP Type 1 Content */
1962 bool hdcp_mst_type1_capable;
1963
1964 void (*write_infoframe)(struct intel_encoder *encoder,
1965 const struct intel_crtc_state *crtc_state,
1966 unsigned int type,
1967 const void *frame, ssize_t len);
1968 void (*read_infoframe)(struct intel_encoder *encoder,
1969 const struct intel_crtc_state *crtc_state,
1970 unsigned int type,
1971 void *frame, ssize_t len);
1972 void (*set_infoframes)(struct intel_encoder *encoder,
1973 bool enable,
1974 const struct intel_crtc_state *crtc_state,
1975 const struct drm_connector_state *conn_state);
1976 u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1977 const struct intel_crtc_state *pipe_config);
1978 bool (*connected)(struct intel_encoder *encoder);
1979
1980 void (*lock)(struct intel_digital_port *dig_port);
1981 void (*unlock)(struct intel_digital_port *dig_port);
1982 };
1983
1984 struct intel_dp_mst_encoder {
1985 struct intel_encoder base;
1986 enum pipe pipe;
1987 struct intel_digital_port *primary;
1988 struct intel_connector *connector;
1989 };
1990
1991 static inline struct intel_encoder *
intel_attached_encoder(struct intel_connector * connector)1992 intel_attached_encoder(struct intel_connector *connector)
1993 {
1994 return connector->encoder;
1995 }
1996
intel_encoder_is_dig_port(struct intel_encoder * encoder)1997 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1998 {
1999 switch (encoder->type) {
2000 case INTEL_OUTPUT_DDI:
2001 case INTEL_OUTPUT_DP:
2002 case INTEL_OUTPUT_EDP:
2003 case INTEL_OUTPUT_HDMI:
2004 return true;
2005 default:
2006 return false;
2007 }
2008 }
2009
intel_encoder_is_mst(struct intel_encoder * encoder)2010 static inline bool intel_encoder_is_mst(struct intel_encoder *encoder)
2011 {
2012 return encoder->type == INTEL_OUTPUT_DP_MST;
2013 }
2014
2015 static inline struct intel_dp_mst_encoder *
enc_to_mst(struct intel_encoder * encoder)2016 enc_to_mst(struct intel_encoder *encoder)
2017 {
2018 return container_of(&encoder->base, struct intel_dp_mst_encoder,
2019 base.base);
2020 }
2021
2022 static inline struct intel_digital_port *
enc_to_dig_port(struct intel_encoder * encoder)2023 enc_to_dig_port(struct intel_encoder *encoder)
2024 {
2025 struct intel_encoder *intel_encoder = encoder;
2026
2027 if (intel_encoder_is_dig_port(intel_encoder))
2028 return container_of(&encoder->base, struct intel_digital_port,
2029 base.base);
2030 else if (intel_encoder_is_mst(intel_encoder))
2031 return enc_to_mst(encoder)->primary;
2032 else
2033 return NULL;
2034 }
2035
2036 static inline struct intel_digital_port *
intel_attached_dig_port(struct intel_connector * connector)2037 intel_attached_dig_port(struct intel_connector *connector)
2038 {
2039 return enc_to_dig_port(intel_attached_encoder(connector));
2040 }
2041
2042 static inline struct intel_hdmi *
enc_to_intel_hdmi(struct intel_encoder * encoder)2043 enc_to_intel_hdmi(struct intel_encoder *encoder)
2044 {
2045 return &enc_to_dig_port(encoder)->hdmi;
2046 }
2047
2048 static inline struct intel_hdmi *
intel_attached_hdmi(struct intel_connector * connector)2049 intel_attached_hdmi(struct intel_connector *connector)
2050 {
2051 return enc_to_intel_hdmi(intel_attached_encoder(connector));
2052 }
2053
enc_to_intel_dp(struct intel_encoder * encoder)2054 static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder)
2055 {
2056 return &enc_to_dig_port(encoder)->dp;
2057 }
2058
intel_attached_dp(struct intel_connector * connector)2059 static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector)
2060 {
2061 return enc_to_intel_dp(intel_attached_encoder(connector));
2062 }
2063
intel_encoder_is_dp(struct intel_encoder * encoder)2064 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
2065 {
2066 switch (encoder->type) {
2067 case INTEL_OUTPUT_DP:
2068 case INTEL_OUTPUT_EDP:
2069 return true;
2070 case INTEL_OUTPUT_DDI:
2071 /* Skip pure HDMI/DVI DDI encoders */
2072 return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg);
2073 default:
2074 return false;
2075 }
2076 }
2077
intel_encoder_is_hdmi(struct intel_encoder * encoder)2078 static inline bool intel_encoder_is_hdmi(struct intel_encoder *encoder)
2079 {
2080 switch (encoder->type) {
2081 case INTEL_OUTPUT_HDMI:
2082 return true;
2083 case INTEL_OUTPUT_DDI:
2084 /* See if the HDMI encoder is valid. */
2085 return i915_mmio_reg_valid(enc_to_intel_hdmi(encoder)->hdmi_reg);
2086 default:
2087 return false;
2088 }
2089 }
2090
2091 static inline struct intel_lspcon *
enc_to_intel_lspcon(struct intel_encoder * encoder)2092 enc_to_intel_lspcon(struct intel_encoder *encoder)
2093 {
2094 return &enc_to_dig_port(encoder)->lspcon;
2095 }
2096
2097 static inline struct intel_digital_port *
dp_to_dig_port(struct intel_dp * intel_dp)2098 dp_to_dig_port(struct intel_dp *intel_dp)
2099 {
2100 return container_of(intel_dp, struct intel_digital_port, dp);
2101 }
2102
2103 static inline struct intel_lspcon *
dp_to_lspcon(struct intel_dp * intel_dp)2104 dp_to_lspcon(struct intel_dp *intel_dp)
2105 {
2106 return &dp_to_dig_port(intel_dp)->lspcon;
2107 }
2108
2109 static inline struct intel_digital_port *
hdmi_to_dig_port(struct intel_hdmi * intel_hdmi)2110 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
2111 {
2112 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
2113 }
2114
2115 static inline struct intel_plane_state *
intel_atomic_get_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)2116 intel_atomic_get_plane_state(struct intel_atomic_state *state,
2117 struct intel_plane *plane)
2118 {
2119 struct drm_plane_state *ret =
2120 drm_atomic_get_plane_state(&state->base, &plane->base);
2121
2122 if (IS_ERR(ret))
2123 return ERR_CAST(ret);
2124
2125 return to_intel_plane_state(ret);
2126 }
2127
2128 static inline struct intel_plane_state *
intel_atomic_get_old_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)2129 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
2130 struct intel_plane *plane)
2131 {
2132 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
2133 &plane->base));
2134 }
2135
2136 static inline struct intel_plane_state *
intel_atomic_get_new_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)2137 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
2138 struct intel_plane *plane)
2139 {
2140 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
2141 &plane->base));
2142 }
2143
2144 static inline struct intel_crtc_state *
intel_atomic_get_old_crtc_state(struct intel_atomic_state * state,struct intel_crtc * crtc)2145 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
2146 struct intel_crtc *crtc)
2147 {
2148 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
2149 &crtc->base));
2150 }
2151
2152 static inline struct intel_crtc_state *
intel_atomic_get_new_crtc_state(struct intel_atomic_state * state,struct intel_crtc * crtc)2153 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
2154 struct intel_crtc *crtc)
2155 {
2156 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
2157 &crtc->base));
2158 }
2159
2160 static inline struct intel_digital_connector_state *
intel_atomic_get_new_connector_state(struct intel_atomic_state * state,struct intel_connector * connector)2161 intel_atomic_get_new_connector_state(struct intel_atomic_state *state,
2162 struct intel_connector *connector)
2163 {
2164 return to_intel_digital_connector_state(
2165 drm_atomic_get_new_connector_state(&state->base,
2166 &connector->base));
2167 }
2168
2169 static inline struct intel_digital_connector_state *
intel_atomic_get_old_connector_state(struct intel_atomic_state * state,struct intel_connector * connector)2170 intel_atomic_get_old_connector_state(struct intel_atomic_state *state,
2171 struct intel_connector *connector)
2172 {
2173 return to_intel_digital_connector_state(
2174 drm_atomic_get_old_connector_state(&state->base,
2175 &connector->base));
2176 }
2177
2178 /* intel_display.c */
2179 static inline bool
intel_crtc_has_type(const struct intel_crtc_state * crtc_state,enum intel_output_type type)2180 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
2181 enum intel_output_type type)
2182 {
2183 return crtc_state->output_types & BIT(type);
2184 }
2185
2186 static inline bool
intel_crtc_has_dp_encoder(const struct intel_crtc_state * crtc_state)2187 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
2188 {
2189 return crtc_state->output_types &
2190 (BIT(INTEL_OUTPUT_DP) |
2191 BIT(INTEL_OUTPUT_DP_MST) |
2192 BIT(INTEL_OUTPUT_EDP));
2193 }
2194
2195 static inline bool
intel_crtc_needs_modeset(const struct intel_crtc_state * crtc_state)2196 intel_crtc_needs_modeset(const struct intel_crtc_state *crtc_state)
2197 {
2198 return drm_atomic_crtc_needs_modeset(&crtc_state->uapi);
2199 }
2200
2201 static inline bool
intel_crtc_needs_fastset(const struct intel_crtc_state * crtc_state)2202 intel_crtc_needs_fastset(const struct intel_crtc_state *crtc_state)
2203 {
2204 return crtc_state->update_pipe;
2205 }
2206
2207 static inline bool
intel_crtc_needs_color_update(const struct intel_crtc_state * crtc_state)2208 intel_crtc_needs_color_update(const struct intel_crtc_state *crtc_state)
2209 {
2210 return crtc_state->uapi.color_mgmt_changed ||
2211 intel_crtc_needs_fastset(crtc_state) ||
2212 intel_crtc_needs_modeset(crtc_state);
2213 }
2214
intel_plane_ggtt_offset(const struct intel_plane_state * plane_state)2215 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state)
2216 {
2217 return i915_ggtt_offset(plane_state->ggtt_vma);
2218 }
2219
2220 static inline struct intel_frontbuffer *
to_intel_frontbuffer(struct drm_framebuffer * fb)2221 to_intel_frontbuffer(struct drm_framebuffer *fb)
2222 {
2223 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
2224 }
2225
2226 /*
2227 * Conversion functions/macros from various pointer types to struct
2228 * intel_display pointer.
2229 */
2230 #define __drm_device_to_intel_display(p) \
2231 ((p) ? &to_i915(p)->display : NULL)
2232 #define __device_to_intel_display(p) \
2233 __drm_device_to_intel_display(dev_get_drvdata(p))
2234 #define __pci_dev_to_intel_display(p) \
2235 __drm_device_to_intel_display(pci_get_drvdata(p))
2236 #define __intel_atomic_state_to_intel_display(p) \
2237 __drm_device_to_intel_display((p)->base.dev)
2238 #define __intel_connector_to_intel_display(p) \
2239 __drm_device_to_intel_display((p)->base.dev)
2240 #define __intel_crtc_to_intel_display(p) \
2241 __drm_device_to_intel_display((p)->base.dev)
2242 #define __intel_crtc_state_to_intel_display(p) \
2243 __drm_device_to_intel_display((p)->uapi.crtc->dev)
2244 #define __intel_digital_port_to_intel_display(p) \
2245 __drm_device_to_intel_display((p)->base.base.dev)
2246 #define __intel_dp_to_intel_display(p) \
2247 __drm_device_to_intel_display(dp_to_dig_port(p)->base.base.dev)
2248 #define __intel_encoder_to_intel_display(p) \
2249 __drm_device_to_intel_display((p)->base.dev)
2250 #define __intel_hdmi_to_intel_display(p) \
2251 __drm_device_to_intel_display(hdmi_to_dig_port(p)->base.base.dev)
2252
2253 /* Helper for generic association. Map types to conversion functions/macros. */
2254 #define __assoc(type, p) \
2255 struct type: __##type##_to_intel_display((struct type *)(p))
2256
2257 /* Convert various pointer types to struct intel_display pointer. */
2258 #define to_intel_display(p) \
2259 _Generic(*p, \
2260 __assoc(drm_device, p), \
2261 __assoc(device, p), \
2262 __assoc(pci_dev, p), \
2263 __assoc(intel_atomic_state, p), \
2264 __assoc(intel_connector, p), \
2265 __assoc(intel_crtc, p), \
2266 __assoc(intel_crtc_state, p), \
2267 __assoc(intel_digital_port, p), \
2268 __assoc(intel_dp, p), \
2269 __assoc(intel_encoder, p), \
2270 __assoc(intel_hdmi, p))
2271
2272 #endif /* __INTEL_DISPLAY_TYPES_H__ */
2273