1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * alternative runtime patching
4 * inspired by the x86 version
5 *
6 * Copyright (C) 2014 ARM Ltd.
7 */
8
9 #define pr_fmt(fmt) "alternatives: " fmt
10
11 #include <linux/cfi_types.h>
12 #include <linux/init.h>
13 #include <linux/cpu.h>
14 #include <linux/elf.h>
15 #include <asm/cacheflush.h>
16 #include <asm/alternative.h>
17 #include <asm/cfi.h>
18 #include <asm/cpufeature.h>
19 #include <asm/insn.h>
20 #include <asm/module.h>
21 #include <asm/sections.h>
22 #include <asm/vdso.h>
23 #include <linux/stop_machine.h>
24
25 #define __ALT_PTR(a, f) ((void *)&(a)->f + (a)->f)
26 #define ALT_ORIG_PTR(a) __ALT_PTR(a, orig_offset)
27 #define ALT_REPL_PTR(a) __ALT_PTR(a, alt_offset)
28
29 #define ALT_CAP(a) ((a)->cpucap & ~ARM64_CB_BIT)
30 #define ALT_HAS_CB(a) ((a)->cpucap & ARM64_CB_BIT)
31
32 /* Volatile, as we may be patching the guts of READ_ONCE() */
33 static volatile int all_alternatives_applied;
34
35 static DECLARE_BITMAP(applied_alternatives, ARM64_NCAPS);
36
37 struct alt_region {
38 struct alt_instr *begin;
39 struct alt_instr *end;
40 };
41
alternative_is_applied(u16 cpucap)42 bool alternative_is_applied(u16 cpucap)
43 {
44 if (WARN_ON(cpucap >= ARM64_NCAPS))
45 return false;
46
47 return test_bit(cpucap, applied_alternatives);
48 }
49
50 /*
51 * Check if the target PC is within an alternative block.
52 */
branch_insn_requires_update(struct alt_instr * alt,unsigned long pc)53 static __always_inline bool branch_insn_requires_update(struct alt_instr *alt, unsigned long pc)
54 {
55 unsigned long replptr = (unsigned long)ALT_REPL_PTR(alt);
56 return !(pc >= replptr && pc <= (replptr + alt->alt_len));
57 }
58
59 #define align_down(x, a) ((unsigned long)(x) & ~(((unsigned long)(a)) - 1))
60
get_alt_insn(struct alt_instr * alt,__le32 * insnptr,__le32 * altinsnptr)61 static __always_inline u32 get_alt_insn(struct alt_instr *alt, __le32 *insnptr, __le32 *altinsnptr)
62 {
63 u32 insn;
64
65 insn = le32_to_cpu(*altinsnptr);
66
67 if (aarch64_insn_is_branch_imm(insn)) {
68 s32 offset = aarch64_get_branch_offset(insn);
69 unsigned long target;
70
71 target = (unsigned long)altinsnptr + offset;
72
73 /*
74 * If we're branching inside the alternate sequence,
75 * do not rewrite the instruction, as it is already
76 * correct. Otherwise, generate the new instruction.
77 */
78 if (branch_insn_requires_update(alt, target)) {
79 offset = target - (unsigned long)insnptr;
80 insn = aarch64_set_branch_offset(insn, offset);
81 }
82 } else if (aarch64_insn_is_adrp(insn)) {
83 s32 orig_offset, new_offset;
84 unsigned long target;
85
86 /*
87 * If we're replacing an adrp instruction, which uses PC-relative
88 * immediate addressing, adjust the offset to reflect the new
89 * PC. adrp operates on 4K aligned addresses.
90 */
91 orig_offset = aarch64_insn_adrp_get_offset(insn);
92 target = align_down(altinsnptr, SZ_4K) + orig_offset;
93 new_offset = target - align_down(insnptr, SZ_4K);
94 insn = aarch64_insn_adrp_set_offset(insn, new_offset);
95 } else if (aarch64_insn_uses_literal(insn)) {
96 /*
97 * Disallow patching unhandled instructions using PC relative
98 * literal addresses
99 */
100 BUG();
101 }
102
103 return insn;
104 }
105
patch_alternative(struct alt_instr * alt,__le32 * origptr,__le32 * updptr,int nr_inst)106 static noinstr void patch_alternative(struct alt_instr *alt,
107 __le32 *origptr, __le32 *updptr, int nr_inst)
108 {
109 __le32 *replptr;
110 int i;
111
112 replptr = ALT_REPL_PTR(alt);
113 for (i = 0; i < nr_inst; i++) {
114 u32 insn;
115
116 insn = get_alt_insn(alt, origptr + i, replptr + i);
117 updptr[i] = cpu_to_le32(insn);
118 }
119 }
120
121 /*
122 * We provide our own, private D-cache cleaning function so that we don't
123 * accidentally call into the cache.S code, which is patched by us at
124 * runtime.
125 */
clean_dcache_range_nopatch(u64 start,u64 end)126 static noinstr void clean_dcache_range_nopatch(u64 start, u64 end)
127 {
128 u64 cur, d_size, ctr_el0;
129
130 ctr_el0 = arm64_ftr_reg_ctrel0.sys_val;
131 d_size = 4 << cpuid_feature_extract_unsigned_field(ctr_el0,
132 CTR_EL0_DminLine_SHIFT);
133 cur = start & ~(d_size - 1);
134 do {
135 /*
136 * We must clean+invalidate to the PoC in order to avoid
137 * Cortex-A53 errata 826319, 827319, 824069 and 819472
138 * (this corresponds to ARM64_WORKAROUND_CLEAN_CACHE)
139 */
140 asm volatile("dc civac, %0" : : "r" (cur) : "memory");
141 } while (cur += d_size, cur < end);
142 }
143
__apply_alternatives(const struct alt_region * region,bool is_module,unsigned long * cpucap_mask)144 static void __apply_alternatives(const struct alt_region *region,
145 bool is_module,
146 unsigned long *cpucap_mask)
147 {
148 struct alt_instr *alt;
149 __le32 *origptr, *updptr;
150 alternative_cb_t alt_cb;
151
152 for (alt = region->begin; alt < region->end; alt++) {
153 int nr_inst;
154 int cap = ALT_CAP(alt);
155
156 if (!test_bit(cap, cpucap_mask))
157 continue;
158
159 if (!cpus_have_cap(cap))
160 continue;
161
162 if (ALT_HAS_CB(alt))
163 BUG_ON(alt->alt_len != 0);
164 else
165 BUG_ON(alt->alt_len != alt->orig_len);
166
167 origptr = ALT_ORIG_PTR(alt);
168 updptr = is_module ? origptr : lm_alias(origptr);
169 nr_inst = alt->orig_len / AARCH64_INSN_SIZE;
170
171 if (ALT_HAS_CB(alt))
172 alt_cb = ALT_REPL_PTR(alt);
173 else
174 alt_cb = patch_alternative;
175
176 alt_cb(alt, origptr, updptr, nr_inst);
177
178 if (!is_module) {
179 clean_dcache_range_nopatch((u64)origptr,
180 (u64)(origptr + nr_inst));
181 }
182 }
183
184 /*
185 * The core module code takes care of cache maintenance in
186 * flush_module_icache().
187 */
188 if (!is_module) {
189 dsb(ish);
190 icache_inval_all_pou();
191 isb();
192
193 bitmap_or(applied_alternatives, applied_alternatives,
194 cpucap_mask, ARM64_NCAPS);
195 bitmap_and(applied_alternatives, applied_alternatives,
196 system_cpucaps, ARM64_NCAPS);
197 }
198 }
199
apply_alternatives_vdso(void)200 static void __init apply_alternatives_vdso(void)
201 {
202 struct alt_region region;
203 const struct elf64_hdr *hdr;
204 const struct elf64_shdr *shdr;
205 const struct elf64_shdr *alt;
206 DECLARE_BITMAP(all_capabilities, ARM64_NCAPS);
207
208 bitmap_fill(all_capabilities, ARM64_NCAPS);
209
210 hdr = (struct elf64_hdr *)vdso_start;
211 shdr = (void *)hdr + hdr->e_shoff;
212 alt = find_section(hdr, shdr, ".altinstructions");
213 if (!alt)
214 return;
215
216 region = (struct alt_region){
217 .begin = (void *)hdr + alt->sh_offset,
218 .end = (void *)hdr + alt->sh_offset + alt->sh_size,
219 };
220
221 __apply_alternatives(®ion, false, &all_capabilities[0]);
222 }
223
224 static const struct alt_region kernel_alternatives __initconst = {
225 .begin = (struct alt_instr *)__alt_instructions,
226 .end = (struct alt_instr *)__alt_instructions_end,
227 };
228
229 /*
230 * We might be patching the stop_machine state machine, so implement a
231 * really simple polling protocol here.
232 */
__apply_alternatives_multi_stop(void * unused)233 static int __init __apply_alternatives_multi_stop(void *unused)
234 {
235 /* We always have a CPU 0 at this point (__init) */
236 if (smp_processor_id()) {
237 while (!all_alternatives_applied)
238 cpu_relax();
239 isb();
240 } else {
241 DECLARE_BITMAP(remaining_capabilities, ARM64_NCAPS);
242
243 bitmap_complement(remaining_capabilities, boot_cpucaps,
244 ARM64_NCAPS);
245
246 BUG_ON(all_alternatives_applied);
247 __apply_alternatives(&kernel_alternatives, false,
248 remaining_capabilities);
249 /* Barriers provided by the cache flushing */
250 all_alternatives_applied = 1;
251 }
252
253 return 0;
254 }
255
apply_alternatives_all(void)256 void __init apply_alternatives_all(void)
257 {
258 pr_info("applying system-wide alternatives\n");
259
260 apply_alternatives_vdso();
261 /* better not try code patching on a live SMP system */
262 stop_machine(__apply_alternatives_multi_stop, NULL, cpu_online_mask);
263 }
264
265 /*
266 * This is called very early in the boot process (directly after we run
267 * a feature detect on the boot CPU). No need to worry about other CPUs
268 * here.
269 */
apply_boot_alternatives(void)270 void __init apply_boot_alternatives(void)
271 {
272 /* If called on non-boot cpu things could go wrong */
273 WARN_ON(smp_processor_id() != 0);
274
275 pr_info("applying boot alternatives\n");
276
277 __apply_alternatives(&kernel_alternatives, false,
278 &boot_cpucaps[0]);
279 }
280
281 #ifdef CONFIG_MODULES
apply_alternatives_module(void * start,size_t length)282 void apply_alternatives_module(void *start, size_t length)
283 {
284 struct alt_region region = {
285 .begin = start,
286 .end = start + length,
287 };
288 DECLARE_BITMAP(all_capabilities, ARM64_NCAPS);
289
290 bitmap_fill(all_capabilities, ARM64_NCAPS);
291
292 __apply_alternatives(®ion, true, &all_capabilities[0]);
293 }
294 #endif
295
alt_cb_patch_nops(struct alt_instr * alt,__le32 * origptr,__le32 * updptr,int nr_inst)296 noinstr void alt_cb_patch_nops(struct alt_instr *alt, __le32 *origptr,
297 __le32 *updptr, int nr_inst)
298 {
299 for (int i = 0; i < nr_inst; i++)
300 updptr[i] = cpu_to_le32(aarch64_insn_gen_nop());
301 }
302 EXPORT_SYMBOL(alt_cb_patch_nops);
303
304 #ifdef CONFIG_CFI_CLANG
305 struct bpf_insn;
306
307 /* Must match bpf_func_t / DEFINE_BPF_PROG_RUN() */
308 extern unsigned int __bpf_prog_runX(const void *ctx,
309 const struct bpf_insn *insn);
310 DEFINE_CFI_TYPE(cfi_bpf_hash, __bpf_prog_runX);
311
312 /* Must match bpf_callback_t */
313 extern u64 __bpf_callback_fn(u64, u64, u64, u64, u64);
314 DEFINE_CFI_TYPE(cfi_bpf_subprog_hash, __bpf_callback_fn);
315
cfi_get_func_hash(void * func)316 u32 cfi_get_func_hash(void *func)
317 {
318 u32 hash;
319
320 if (get_kernel_nofault(hash, func - cfi_get_offset()))
321 return 0;
322
323 return hash;
324 }
325 #endif /* CONFIG_CFI_CLANG */
326