1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <crypto/hash.h>
8 #include "core.h"
9 #include "dp_tx.h"
10 #include "hal_tx.h"
11 #include "hif.h"
12 #include "debug.h"
13 #include "dp_rx.h"
14 #include "peer.h"
15 #include "dp_mon.h"
16
17 enum ath12k_dp_desc_type {
18 ATH12K_DP_TX_DESC,
19 ATH12K_DP_RX_DESC,
20 };
21
ath12k_dp_htt_htc_tx_complete(struct ath12k_base * ab,struct sk_buff * skb)22 static void ath12k_dp_htt_htc_tx_complete(struct ath12k_base *ab,
23 struct sk_buff *skb)
24 {
25 dev_kfree_skb_any(skb);
26 }
27
ath12k_dp_peer_cleanup(struct ath12k * ar,int vdev_id,const u8 * addr)28 void ath12k_dp_peer_cleanup(struct ath12k *ar, int vdev_id, const u8 *addr)
29 {
30 struct ath12k_base *ab = ar->ab;
31 struct ath12k_peer *peer;
32
33 /* TODO: Any other peer specific DP cleanup */
34
35 spin_lock_bh(&ab->base_lock);
36 peer = ath12k_peer_find(ab, vdev_id, addr);
37 if (!peer) {
38 ath12k_warn(ab, "failed to lookup peer %pM on vdev %d\n",
39 addr, vdev_id);
40 spin_unlock_bh(&ab->base_lock);
41 return;
42 }
43
44 ath12k_dp_rx_peer_tid_cleanup(ar, peer);
45 crypto_free_shash(peer->tfm_mmic);
46 peer->dp_setup_done = false;
47 spin_unlock_bh(&ab->base_lock);
48 }
49
ath12k_dp_peer_setup(struct ath12k * ar,int vdev_id,const u8 * addr)50 int ath12k_dp_peer_setup(struct ath12k *ar, int vdev_id, const u8 *addr)
51 {
52 struct ath12k_base *ab = ar->ab;
53 struct ath12k_peer *peer;
54 u32 reo_dest;
55 int ret = 0, tid;
56
57 /* NOTE: reo_dest ring id starts from 1 unlike mac_id which starts from 0 */
58 reo_dest = ar->dp.mac_id + 1;
59 ret = ath12k_wmi_set_peer_param(ar, addr, vdev_id,
60 WMI_PEER_SET_DEFAULT_ROUTING,
61 DP_RX_HASH_ENABLE | (reo_dest << 1));
62
63 if (ret) {
64 ath12k_warn(ab, "failed to set default routing %d peer :%pM vdev_id :%d\n",
65 ret, addr, vdev_id);
66 return ret;
67 }
68
69 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) {
70 ret = ath12k_dp_rx_peer_tid_setup(ar, addr, vdev_id, tid, 1, 0,
71 HAL_PN_TYPE_NONE);
72 if (ret) {
73 ath12k_warn(ab, "failed to setup rxd tid queue for tid %d: %d\n",
74 tid, ret);
75 goto peer_clean;
76 }
77 }
78
79 ret = ath12k_dp_rx_peer_frag_setup(ar, addr, vdev_id);
80 if (ret) {
81 ath12k_warn(ab, "failed to setup rx defrag context\n");
82 tid--;
83 goto peer_clean;
84 }
85
86 /* TODO: Setup other peer specific resource used in data path */
87
88 return 0;
89
90 peer_clean:
91 spin_lock_bh(&ab->base_lock);
92
93 peer = ath12k_peer_find(ab, vdev_id, addr);
94 if (!peer) {
95 ath12k_warn(ab, "failed to find the peer to del rx tid\n");
96 spin_unlock_bh(&ab->base_lock);
97 return -ENOENT;
98 }
99
100 for (tid--; tid >= 0; tid--)
101 ath12k_dp_rx_peer_tid_delete(ar, peer, tid);
102
103 spin_unlock_bh(&ab->base_lock);
104
105 return ret;
106 }
107
ath12k_dp_srng_cleanup(struct ath12k_base * ab,struct dp_srng * ring)108 void ath12k_dp_srng_cleanup(struct ath12k_base *ab, struct dp_srng *ring)
109 {
110 if (!ring->vaddr_unaligned)
111 return;
112
113 dma_free_coherent(ab->dev, ring->size, ring->vaddr_unaligned,
114 ring->paddr_unaligned);
115
116 ring->vaddr_unaligned = NULL;
117 }
118
ath12k_dp_srng_find_ring_in_mask(int ring_num,const u8 * grp_mask)119 static int ath12k_dp_srng_find_ring_in_mask(int ring_num, const u8 *grp_mask)
120 {
121 int ext_group_num;
122 u8 mask = 1 << ring_num;
123
124 for (ext_group_num = 0; ext_group_num < ATH12K_EXT_IRQ_GRP_NUM_MAX;
125 ext_group_num++) {
126 if (mask & grp_mask[ext_group_num])
127 return ext_group_num;
128 }
129
130 return -ENOENT;
131 }
132
ath12k_dp_srng_calculate_msi_group(struct ath12k_base * ab,enum hal_ring_type type,int ring_num)133 static int ath12k_dp_srng_calculate_msi_group(struct ath12k_base *ab,
134 enum hal_ring_type type, int ring_num)
135 {
136 const struct ath12k_hal_tcl_to_wbm_rbm_map *map;
137 const u8 *grp_mask;
138 int i;
139
140 switch (type) {
141 case HAL_WBM2SW_RELEASE:
142 if (ring_num == HAL_WBM2SW_REL_ERR_RING_NUM) {
143 grp_mask = &ab->hw_params->ring_mask->rx_wbm_rel[0];
144 ring_num = 0;
145 } else {
146 map = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map;
147 for (i = 0; i < ab->hw_params->max_tx_ring; i++) {
148 if (ring_num == map[i].wbm_ring_num) {
149 ring_num = i;
150 break;
151 }
152 }
153
154 grp_mask = &ab->hw_params->ring_mask->tx[0];
155 }
156 break;
157 case HAL_REO_EXCEPTION:
158 grp_mask = &ab->hw_params->ring_mask->rx_err[0];
159 break;
160 case HAL_REO_DST:
161 grp_mask = &ab->hw_params->ring_mask->rx[0];
162 break;
163 case HAL_REO_STATUS:
164 grp_mask = &ab->hw_params->ring_mask->reo_status[0];
165 break;
166 case HAL_RXDMA_MONITOR_STATUS:
167 case HAL_RXDMA_MONITOR_DST:
168 grp_mask = &ab->hw_params->ring_mask->rx_mon_dest[0];
169 break;
170 case HAL_TX_MONITOR_DST:
171 grp_mask = &ab->hw_params->ring_mask->tx_mon_dest[0];
172 break;
173 case HAL_RXDMA_BUF:
174 grp_mask = &ab->hw_params->ring_mask->host2rxdma[0];
175 break;
176 case HAL_RXDMA_MONITOR_BUF:
177 case HAL_TCL_DATA:
178 case HAL_TCL_CMD:
179 case HAL_REO_CMD:
180 case HAL_SW2WBM_RELEASE:
181 case HAL_WBM_IDLE_LINK:
182 case HAL_TCL_STATUS:
183 case HAL_REO_REINJECT:
184 case HAL_CE_SRC:
185 case HAL_CE_DST:
186 case HAL_CE_DST_STATUS:
187 default:
188 return -ENOENT;
189 }
190
191 return ath12k_dp_srng_find_ring_in_mask(ring_num, grp_mask);
192 }
193
ath12k_dp_srng_msi_setup(struct ath12k_base * ab,struct hal_srng_params * ring_params,enum hal_ring_type type,int ring_num)194 static void ath12k_dp_srng_msi_setup(struct ath12k_base *ab,
195 struct hal_srng_params *ring_params,
196 enum hal_ring_type type, int ring_num)
197 {
198 int msi_group_number, msi_data_count;
199 u32 msi_data_start, msi_irq_start, addr_lo, addr_hi;
200 int ret;
201
202 ret = ath12k_hif_get_user_msi_vector(ab, "DP",
203 &msi_data_count, &msi_data_start,
204 &msi_irq_start);
205 if (ret)
206 return;
207
208 msi_group_number = ath12k_dp_srng_calculate_msi_group(ab, type,
209 ring_num);
210 if (msi_group_number < 0) {
211 ath12k_dbg(ab, ATH12K_DBG_PCI,
212 "ring not part of an ext_group; ring_type: %d,ring_num %d",
213 type, ring_num);
214 ring_params->msi_addr = 0;
215 ring_params->msi_data = 0;
216 return;
217 }
218
219 if (msi_group_number > msi_data_count) {
220 ath12k_dbg(ab, ATH12K_DBG_PCI,
221 "multiple msi_groups share one msi, msi_group_num %d",
222 msi_group_number);
223 }
224
225 ath12k_hif_get_msi_address(ab, &addr_lo, &addr_hi);
226
227 ring_params->msi_addr = addr_lo;
228 ring_params->msi_addr |= (dma_addr_t)(((uint64_t)addr_hi) << 32);
229 ring_params->msi_data = (msi_group_number % msi_data_count)
230 + msi_data_start;
231 ring_params->flags |= HAL_SRNG_FLAGS_MSI_INTR;
232 }
233
ath12k_dp_srng_setup(struct ath12k_base * ab,struct dp_srng * ring,enum hal_ring_type type,int ring_num,int mac_id,int num_entries)234 int ath12k_dp_srng_setup(struct ath12k_base *ab, struct dp_srng *ring,
235 enum hal_ring_type type, int ring_num,
236 int mac_id, int num_entries)
237 {
238 struct hal_srng_params params = { 0 };
239 int entry_sz = ath12k_hal_srng_get_entrysize(ab, type);
240 int max_entries = ath12k_hal_srng_get_max_entries(ab, type);
241 int ret;
242
243 if (max_entries < 0 || entry_sz < 0)
244 return -EINVAL;
245
246 if (num_entries > max_entries)
247 num_entries = max_entries;
248
249 ring->size = (num_entries * entry_sz) + HAL_RING_BASE_ALIGN - 1;
250 ring->vaddr_unaligned = dma_alloc_coherent(ab->dev, ring->size,
251 &ring->paddr_unaligned,
252 GFP_KERNEL);
253 if (!ring->vaddr_unaligned)
254 return -ENOMEM;
255
256 ring->vaddr = PTR_ALIGN(ring->vaddr_unaligned, HAL_RING_BASE_ALIGN);
257 ring->paddr = ring->paddr_unaligned + ((unsigned long)ring->vaddr -
258 (unsigned long)ring->vaddr_unaligned);
259
260 params.ring_base_vaddr = ring->vaddr;
261 params.ring_base_paddr = ring->paddr;
262 params.num_entries = num_entries;
263 ath12k_dp_srng_msi_setup(ab, ¶ms, type, ring_num + mac_id);
264
265 switch (type) {
266 case HAL_REO_DST:
267 params.intr_batch_cntr_thres_entries =
268 HAL_SRNG_INT_BATCH_THRESHOLD_RX;
269 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX;
270 break;
271 case HAL_RXDMA_BUF:
272 case HAL_RXDMA_MONITOR_BUF:
273 case HAL_RXDMA_MONITOR_STATUS:
274 params.low_threshold = num_entries >> 3;
275 params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN;
276 params.intr_batch_cntr_thres_entries = 0;
277 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX;
278 break;
279 case HAL_TX_MONITOR_DST:
280 params.low_threshold = DP_TX_MONITOR_BUF_SIZE_MAX >> 3;
281 params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN;
282 params.intr_batch_cntr_thres_entries = 0;
283 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX;
284 break;
285 case HAL_WBM2SW_RELEASE:
286 if (ab->hw_params->hw_ops->dp_srng_is_tx_comp_ring(ring_num)) {
287 params.intr_batch_cntr_thres_entries =
288 HAL_SRNG_INT_BATCH_THRESHOLD_TX;
289 params.intr_timer_thres_us =
290 HAL_SRNG_INT_TIMER_THRESHOLD_TX;
291 break;
292 }
293 /* follow through when ring_num != HAL_WBM2SW_REL_ERR_RING_NUM */
294 fallthrough;
295 case HAL_REO_EXCEPTION:
296 case HAL_REO_REINJECT:
297 case HAL_REO_CMD:
298 case HAL_REO_STATUS:
299 case HAL_TCL_DATA:
300 case HAL_TCL_CMD:
301 case HAL_TCL_STATUS:
302 case HAL_WBM_IDLE_LINK:
303 case HAL_SW2WBM_RELEASE:
304 case HAL_RXDMA_DST:
305 case HAL_RXDMA_MONITOR_DST:
306 case HAL_RXDMA_MONITOR_DESC:
307 params.intr_batch_cntr_thres_entries =
308 HAL_SRNG_INT_BATCH_THRESHOLD_OTHER;
309 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_OTHER;
310 break;
311 case HAL_RXDMA_DIR_BUF:
312 break;
313 default:
314 ath12k_warn(ab, "Not a valid ring type in dp :%d\n", type);
315 return -EINVAL;
316 }
317
318 ret = ath12k_hal_srng_setup(ab, type, ring_num, mac_id, ¶ms);
319 if (ret < 0) {
320 ath12k_warn(ab, "failed to setup srng: %d ring_id %d\n",
321 ret, ring_num);
322 return ret;
323 }
324
325 ring->ring_id = ret;
326
327 return 0;
328 }
329
330 static
ath12k_dp_tx_get_vdev_bank_config(struct ath12k_base * ab,struct ath12k_vif * arvif)331 u32 ath12k_dp_tx_get_vdev_bank_config(struct ath12k_base *ab, struct ath12k_vif *arvif)
332 {
333 u32 bank_config = 0;
334
335 /* Only valid for raw frames with HW crypto enabled.
336 * With SW crypto, mac80211 sets key per packet
337 */
338 if (arvif->tx_encap_type == HAL_TCL_ENCAP_TYPE_RAW &&
339 test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags))
340 bank_config |=
341 u32_encode_bits(ath12k_dp_tx_get_encrypt_type(arvif->key_cipher),
342 HAL_TX_BANK_CONFIG_ENCRYPT_TYPE);
343
344 bank_config |= u32_encode_bits(arvif->tx_encap_type,
345 HAL_TX_BANK_CONFIG_ENCAP_TYPE);
346 bank_config |= u32_encode_bits(0, HAL_TX_BANK_CONFIG_SRC_BUFFER_SWAP) |
347 u32_encode_bits(0, HAL_TX_BANK_CONFIG_LINK_META_SWAP) |
348 u32_encode_bits(0, HAL_TX_BANK_CONFIG_EPD);
349
350 /* only valid if idx_lookup_override is not set in tcl_data_cmd */
351 bank_config |= u32_encode_bits(0, HAL_TX_BANK_CONFIG_INDEX_LOOKUP_EN);
352
353 bank_config |= u32_encode_bits(arvif->hal_addr_search_flags & HAL_TX_ADDRX_EN,
354 HAL_TX_BANK_CONFIG_ADDRX_EN) |
355 u32_encode_bits(!!(arvif->hal_addr_search_flags &
356 HAL_TX_ADDRY_EN),
357 HAL_TX_BANK_CONFIG_ADDRY_EN);
358
359 bank_config |= u32_encode_bits(ieee80211_vif_is_mesh(arvif->vif) ? 3 : 0,
360 HAL_TX_BANK_CONFIG_MESH_EN) |
361 u32_encode_bits(arvif->vdev_id_check_en,
362 HAL_TX_BANK_CONFIG_VDEV_ID_CHECK_EN);
363
364 bank_config |= u32_encode_bits(0, HAL_TX_BANK_CONFIG_DSCP_TIP_MAP_ID);
365
366 return bank_config;
367 }
368
ath12k_dp_tx_get_bank_profile(struct ath12k_base * ab,struct ath12k_vif * arvif,struct ath12k_dp * dp)369 static int ath12k_dp_tx_get_bank_profile(struct ath12k_base *ab, struct ath12k_vif *arvif,
370 struct ath12k_dp *dp)
371 {
372 int bank_id = DP_INVALID_BANK_ID;
373 int i;
374 u32 bank_config;
375 bool configure_register = false;
376
377 /* convert vdev params into hal_tx_bank_config */
378 bank_config = ath12k_dp_tx_get_vdev_bank_config(ab, arvif);
379
380 spin_lock_bh(&dp->tx_bank_lock);
381 /* TODO: implement using idr kernel framework*/
382 for (i = 0; i < dp->num_bank_profiles; i++) {
383 if (dp->bank_profiles[i].is_configured &&
384 (dp->bank_profiles[i].bank_config ^ bank_config) == 0) {
385 bank_id = i;
386 goto inc_ref_and_return;
387 }
388 if (!dp->bank_profiles[i].is_configured ||
389 !dp->bank_profiles[i].num_users) {
390 bank_id = i;
391 goto configure_and_return;
392 }
393 }
394
395 if (bank_id == DP_INVALID_BANK_ID) {
396 spin_unlock_bh(&dp->tx_bank_lock);
397 ath12k_err(ab, "unable to find TX bank!");
398 return bank_id;
399 }
400
401 configure_and_return:
402 dp->bank_profiles[bank_id].is_configured = true;
403 dp->bank_profiles[bank_id].bank_config = bank_config;
404 configure_register = true;
405 inc_ref_and_return:
406 dp->bank_profiles[bank_id].num_users++;
407 spin_unlock_bh(&dp->tx_bank_lock);
408
409 if (configure_register)
410 ath12k_hal_tx_configure_bank_register(ab, bank_config, bank_id);
411
412 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt tcl bank_id %d input 0x%x match 0x%x num_users %u",
413 bank_id, bank_config, dp->bank_profiles[bank_id].bank_config,
414 dp->bank_profiles[bank_id].num_users);
415
416 return bank_id;
417 }
418
ath12k_dp_tx_put_bank_profile(struct ath12k_dp * dp,u8 bank_id)419 void ath12k_dp_tx_put_bank_profile(struct ath12k_dp *dp, u8 bank_id)
420 {
421 spin_lock_bh(&dp->tx_bank_lock);
422 dp->bank_profiles[bank_id].num_users--;
423 spin_unlock_bh(&dp->tx_bank_lock);
424 }
425
ath12k_dp_deinit_bank_profiles(struct ath12k_base * ab)426 static void ath12k_dp_deinit_bank_profiles(struct ath12k_base *ab)
427 {
428 struct ath12k_dp *dp = &ab->dp;
429
430 kfree(dp->bank_profiles);
431 dp->bank_profiles = NULL;
432 }
433
ath12k_dp_init_bank_profiles(struct ath12k_base * ab)434 static int ath12k_dp_init_bank_profiles(struct ath12k_base *ab)
435 {
436 struct ath12k_dp *dp = &ab->dp;
437 u32 num_tcl_banks = ab->hw_params->num_tcl_banks;
438 int i;
439
440 dp->num_bank_profiles = num_tcl_banks;
441 dp->bank_profiles = kmalloc_array(num_tcl_banks,
442 sizeof(struct ath12k_dp_tx_bank_profile),
443 GFP_KERNEL);
444 if (!dp->bank_profiles)
445 return -ENOMEM;
446
447 spin_lock_init(&dp->tx_bank_lock);
448
449 for (i = 0; i < num_tcl_banks; i++) {
450 dp->bank_profiles[i].is_configured = false;
451 dp->bank_profiles[i].num_users = 0;
452 }
453
454 return 0;
455 }
456
ath12k_dp_srng_common_cleanup(struct ath12k_base * ab)457 static void ath12k_dp_srng_common_cleanup(struct ath12k_base *ab)
458 {
459 struct ath12k_dp *dp = &ab->dp;
460 int i;
461
462 ath12k_dp_srng_cleanup(ab, &dp->reo_status_ring);
463 ath12k_dp_srng_cleanup(ab, &dp->reo_cmd_ring);
464 ath12k_dp_srng_cleanup(ab, &dp->reo_except_ring);
465 ath12k_dp_srng_cleanup(ab, &dp->rx_rel_ring);
466 ath12k_dp_srng_cleanup(ab, &dp->reo_reinject_ring);
467 for (i = 0; i < ab->hw_params->max_tx_ring; i++) {
468 ath12k_dp_srng_cleanup(ab, &dp->tx_ring[i].tcl_comp_ring);
469 ath12k_dp_srng_cleanup(ab, &dp->tx_ring[i].tcl_data_ring);
470 }
471 ath12k_dp_srng_cleanup(ab, &dp->wbm_desc_rel_ring);
472 }
473
ath12k_dp_srng_common_setup(struct ath12k_base * ab)474 static int ath12k_dp_srng_common_setup(struct ath12k_base *ab)
475 {
476 struct ath12k_dp *dp = &ab->dp;
477 const struct ath12k_hal_tcl_to_wbm_rbm_map *map;
478 struct hal_srng *srng;
479 int i, ret, tx_comp_ring_num;
480 u32 ring_hash_map;
481
482 ret = ath12k_dp_srng_setup(ab, &dp->wbm_desc_rel_ring,
483 HAL_SW2WBM_RELEASE, 0, 0,
484 DP_WBM_RELEASE_RING_SIZE);
485 if (ret) {
486 ath12k_warn(ab, "failed to set up wbm2sw_release ring :%d\n",
487 ret);
488 goto err;
489 }
490
491 for (i = 0; i < ab->hw_params->max_tx_ring; i++) {
492 map = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map;
493 tx_comp_ring_num = map[i].wbm_ring_num;
494
495 ret = ath12k_dp_srng_setup(ab, &dp->tx_ring[i].tcl_data_ring,
496 HAL_TCL_DATA, i, 0,
497 DP_TCL_DATA_RING_SIZE);
498 if (ret) {
499 ath12k_warn(ab, "failed to set up tcl_data ring (%d) :%d\n",
500 i, ret);
501 goto err;
502 }
503
504 ret = ath12k_dp_srng_setup(ab, &dp->tx_ring[i].tcl_comp_ring,
505 HAL_WBM2SW_RELEASE, tx_comp_ring_num, 0,
506 DP_TX_COMP_RING_SIZE);
507 if (ret) {
508 ath12k_warn(ab, "failed to set up tcl_comp ring (%d) :%d\n",
509 tx_comp_ring_num, ret);
510 goto err;
511 }
512 }
513
514 ret = ath12k_dp_srng_setup(ab, &dp->reo_reinject_ring, HAL_REO_REINJECT,
515 0, 0, DP_REO_REINJECT_RING_SIZE);
516 if (ret) {
517 ath12k_warn(ab, "failed to set up reo_reinject ring :%d\n",
518 ret);
519 goto err;
520 }
521
522 ret = ath12k_dp_srng_setup(ab, &dp->rx_rel_ring, HAL_WBM2SW_RELEASE,
523 HAL_WBM2SW_REL_ERR_RING_NUM, 0,
524 DP_RX_RELEASE_RING_SIZE);
525 if (ret) {
526 ath12k_warn(ab, "failed to set up rx_rel ring :%d\n", ret);
527 goto err;
528 }
529
530 ret = ath12k_dp_srng_setup(ab, &dp->reo_except_ring, HAL_REO_EXCEPTION,
531 0, 0, DP_REO_EXCEPTION_RING_SIZE);
532 if (ret) {
533 ath12k_warn(ab, "failed to set up reo_exception ring :%d\n",
534 ret);
535 goto err;
536 }
537
538 ret = ath12k_dp_srng_setup(ab, &dp->reo_cmd_ring, HAL_REO_CMD,
539 0, 0, DP_REO_CMD_RING_SIZE);
540 if (ret) {
541 ath12k_warn(ab, "failed to set up reo_cmd ring :%d\n", ret);
542 goto err;
543 }
544
545 srng = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id];
546 ath12k_hal_reo_init_cmd_ring(ab, srng);
547
548 ret = ath12k_dp_srng_setup(ab, &dp->reo_status_ring, HAL_REO_STATUS,
549 0, 0, DP_REO_STATUS_RING_SIZE);
550 if (ret) {
551 ath12k_warn(ab, "failed to set up reo_status ring :%d\n", ret);
552 goto err;
553 }
554
555 /* When hash based routing of rx packet is enabled, 32 entries to map
556 * the hash values to the ring will be configured. Each hash entry uses
557 * four bits to map to a particular ring. The ring mapping will be
558 * 0:TCL, 1:SW1, 2:SW2, 3:SW3, 4:SW4, 5:Release, 6:FW and 7:SW5
559 * 8:SW6, 9:SW7, 10:SW8, 11:Not used.
560 */
561 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 |
562 HAL_HASH_ROUTING_RING_SW2 << 4 |
563 HAL_HASH_ROUTING_RING_SW3 << 8 |
564 HAL_HASH_ROUTING_RING_SW4 << 12 |
565 HAL_HASH_ROUTING_RING_SW1 << 16 |
566 HAL_HASH_ROUTING_RING_SW2 << 20 |
567 HAL_HASH_ROUTING_RING_SW3 << 24 |
568 HAL_HASH_ROUTING_RING_SW4 << 28;
569
570 ath12k_hal_reo_hw_setup(ab, ring_hash_map);
571
572 return 0;
573
574 err:
575 ath12k_dp_srng_common_cleanup(ab);
576
577 return ret;
578 }
579
ath12k_dp_scatter_idle_link_desc_cleanup(struct ath12k_base * ab)580 static void ath12k_dp_scatter_idle_link_desc_cleanup(struct ath12k_base *ab)
581 {
582 struct ath12k_dp *dp = &ab->dp;
583 struct hal_wbm_idle_scatter_list *slist = dp->scatter_list;
584 int i;
585
586 for (i = 0; i < DP_IDLE_SCATTER_BUFS_MAX; i++) {
587 if (!slist[i].vaddr)
588 continue;
589
590 dma_free_coherent(ab->dev, HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX,
591 slist[i].vaddr, slist[i].paddr);
592 slist[i].vaddr = NULL;
593 }
594 }
595
ath12k_dp_scatter_idle_link_desc_setup(struct ath12k_base * ab,int size,u32 n_link_desc_bank,u32 n_link_desc,u32 last_bank_sz)596 static int ath12k_dp_scatter_idle_link_desc_setup(struct ath12k_base *ab,
597 int size,
598 u32 n_link_desc_bank,
599 u32 n_link_desc,
600 u32 last_bank_sz)
601 {
602 struct ath12k_dp *dp = &ab->dp;
603 struct dp_link_desc_bank *link_desc_banks = dp->link_desc_banks;
604 struct hal_wbm_idle_scatter_list *slist = dp->scatter_list;
605 u32 n_entries_per_buf;
606 int num_scatter_buf, scatter_idx;
607 struct hal_wbm_link_desc *scatter_buf;
608 int align_bytes, n_entries;
609 dma_addr_t paddr;
610 int rem_entries;
611 int i;
612 int ret = 0;
613 u32 end_offset, cookie;
614 enum hal_rx_buf_return_buf_manager rbm = dp->idle_link_rbm;
615
616 n_entries_per_buf = HAL_WBM_IDLE_SCATTER_BUF_SIZE /
617 ath12k_hal_srng_get_entrysize(ab, HAL_WBM_IDLE_LINK);
618 num_scatter_buf = DIV_ROUND_UP(size, HAL_WBM_IDLE_SCATTER_BUF_SIZE);
619
620 if (num_scatter_buf > DP_IDLE_SCATTER_BUFS_MAX)
621 return -EINVAL;
622
623 for (i = 0; i < num_scatter_buf; i++) {
624 slist[i].vaddr = dma_alloc_coherent(ab->dev,
625 HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX,
626 &slist[i].paddr, GFP_KERNEL);
627 if (!slist[i].vaddr) {
628 ret = -ENOMEM;
629 goto err;
630 }
631 }
632
633 scatter_idx = 0;
634 scatter_buf = slist[scatter_idx].vaddr;
635 rem_entries = n_entries_per_buf;
636
637 for (i = 0; i < n_link_desc_bank; i++) {
638 align_bytes = link_desc_banks[i].vaddr -
639 link_desc_banks[i].vaddr_unaligned;
640 n_entries = (DP_LINK_DESC_ALLOC_SIZE_THRESH - align_bytes) /
641 HAL_LINK_DESC_SIZE;
642 paddr = link_desc_banks[i].paddr;
643 while (n_entries) {
644 cookie = DP_LINK_DESC_COOKIE_SET(n_entries, i);
645 ath12k_hal_set_link_desc_addr(scatter_buf, cookie,
646 paddr, rbm);
647 n_entries--;
648 paddr += HAL_LINK_DESC_SIZE;
649 if (rem_entries) {
650 rem_entries--;
651 scatter_buf++;
652 continue;
653 }
654
655 rem_entries = n_entries_per_buf;
656 scatter_idx++;
657 scatter_buf = slist[scatter_idx].vaddr;
658 }
659 }
660
661 end_offset = (scatter_buf - slist[scatter_idx].vaddr) *
662 sizeof(struct hal_wbm_link_desc);
663 ath12k_hal_setup_link_idle_list(ab, slist, num_scatter_buf,
664 n_link_desc, end_offset);
665
666 return 0;
667
668 err:
669 ath12k_dp_scatter_idle_link_desc_cleanup(ab);
670
671 return ret;
672 }
673
674 static void
ath12k_dp_link_desc_bank_free(struct ath12k_base * ab,struct dp_link_desc_bank * link_desc_banks)675 ath12k_dp_link_desc_bank_free(struct ath12k_base *ab,
676 struct dp_link_desc_bank *link_desc_banks)
677 {
678 int i;
679
680 for (i = 0; i < DP_LINK_DESC_BANKS_MAX; i++) {
681 if (link_desc_banks[i].vaddr_unaligned) {
682 dma_free_coherent(ab->dev,
683 link_desc_banks[i].size,
684 link_desc_banks[i].vaddr_unaligned,
685 link_desc_banks[i].paddr_unaligned);
686 link_desc_banks[i].vaddr_unaligned = NULL;
687 }
688 }
689 }
690
ath12k_dp_link_desc_bank_alloc(struct ath12k_base * ab,struct dp_link_desc_bank * desc_bank,int n_link_desc_bank,int last_bank_sz)691 static int ath12k_dp_link_desc_bank_alloc(struct ath12k_base *ab,
692 struct dp_link_desc_bank *desc_bank,
693 int n_link_desc_bank,
694 int last_bank_sz)
695 {
696 struct ath12k_dp *dp = &ab->dp;
697 int i;
698 int ret = 0;
699 int desc_sz = DP_LINK_DESC_ALLOC_SIZE_THRESH;
700
701 for (i = 0; i < n_link_desc_bank; i++) {
702 if (i == (n_link_desc_bank - 1) && last_bank_sz)
703 desc_sz = last_bank_sz;
704
705 desc_bank[i].vaddr_unaligned =
706 dma_alloc_coherent(ab->dev, desc_sz,
707 &desc_bank[i].paddr_unaligned,
708 GFP_KERNEL);
709 if (!desc_bank[i].vaddr_unaligned) {
710 ret = -ENOMEM;
711 goto err;
712 }
713
714 desc_bank[i].vaddr = PTR_ALIGN(desc_bank[i].vaddr_unaligned,
715 HAL_LINK_DESC_ALIGN);
716 desc_bank[i].paddr = desc_bank[i].paddr_unaligned +
717 ((unsigned long)desc_bank[i].vaddr -
718 (unsigned long)desc_bank[i].vaddr_unaligned);
719 desc_bank[i].size = desc_sz;
720 }
721
722 return 0;
723
724 err:
725 ath12k_dp_link_desc_bank_free(ab, dp->link_desc_banks);
726
727 return ret;
728 }
729
ath12k_dp_link_desc_cleanup(struct ath12k_base * ab,struct dp_link_desc_bank * desc_bank,u32 ring_type,struct dp_srng * ring)730 void ath12k_dp_link_desc_cleanup(struct ath12k_base *ab,
731 struct dp_link_desc_bank *desc_bank,
732 u32 ring_type, struct dp_srng *ring)
733 {
734 ath12k_dp_link_desc_bank_free(ab, desc_bank);
735
736 if (ring_type != HAL_RXDMA_MONITOR_DESC) {
737 ath12k_dp_srng_cleanup(ab, ring);
738 ath12k_dp_scatter_idle_link_desc_cleanup(ab);
739 }
740 }
741
ath12k_wbm_idle_ring_setup(struct ath12k_base * ab,u32 * n_link_desc)742 static int ath12k_wbm_idle_ring_setup(struct ath12k_base *ab, u32 *n_link_desc)
743 {
744 struct ath12k_dp *dp = &ab->dp;
745 u32 n_mpdu_link_desc, n_mpdu_queue_desc;
746 u32 n_tx_msdu_link_desc, n_rx_msdu_link_desc;
747 int ret = 0;
748
749 n_mpdu_link_desc = (DP_NUM_TIDS_MAX * DP_AVG_MPDUS_PER_TID_MAX) /
750 HAL_NUM_MPDUS_PER_LINK_DESC;
751
752 n_mpdu_queue_desc = n_mpdu_link_desc /
753 HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC;
754
755 n_tx_msdu_link_desc = (DP_NUM_TIDS_MAX * DP_AVG_FLOWS_PER_TID *
756 DP_AVG_MSDUS_PER_FLOW) /
757 HAL_NUM_TX_MSDUS_PER_LINK_DESC;
758
759 n_rx_msdu_link_desc = (DP_NUM_TIDS_MAX * DP_AVG_MPDUS_PER_TID_MAX *
760 DP_AVG_MSDUS_PER_MPDU) /
761 HAL_NUM_RX_MSDUS_PER_LINK_DESC;
762
763 *n_link_desc = n_mpdu_link_desc + n_mpdu_queue_desc +
764 n_tx_msdu_link_desc + n_rx_msdu_link_desc;
765
766 if (*n_link_desc & (*n_link_desc - 1))
767 *n_link_desc = 1 << fls(*n_link_desc);
768
769 ret = ath12k_dp_srng_setup(ab, &dp->wbm_idle_ring,
770 HAL_WBM_IDLE_LINK, 0, 0, *n_link_desc);
771 if (ret) {
772 ath12k_warn(ab, "failed to setup wbm_idle_ring: %d\n", ret);
773 return ret;
774 }
775 return ret;
776 }
777
ath12k_dp_link_desc_setup(struct ath12k_base * ab,struct dp_link_desc_bank * link_desc_banks,u32 ring_type,struct hal_srng * srng,u32 n_link_desc)778 int ath12k_dp_link_desc_setup(struct ath12k_base *ab,
779 struct dp_link_desc_bank *link_desc_banks,
780 u32 ring_type, struct hal_srng *srng,
781 u32 n_link_desc)
782 {
783 u32 tot_mem_sz;
784 u32 n_link_desc_bank, last_bank_sz;
785 u32 entry_sz, align_bytes, n_entries;
786 struct hal_wbm_link_desc *desc;
787 u32 paddr;
788 int i, ret;
789 u32 cookie;
790 enum hal_rx_buf_return_buf_manager rbm = ab->dp.idle_link_rbm;
791
792 tot_mem_sz = n_link_desc * HAL_LINK_DESC_SIZE;
793 tot_mem_sz += HAL_LINK_DESC_ALIGN;
794
795 if (tot_mem_sz <= DP_LINK_DESC_ALLOC_SIZE_THRESH) {
796 n_link_desc_bank = 1;
797 last_bank_sz = tot_mem_sz;
798 } else {
799 n_link_desc_bank = tot_mem_sz /
800 (DP_LINK_DESC_ALLOC_SIZE_THRESH -
801 HAL_LINK_DESC_ALIGN);
802 last_bank_sz = tot_mem_sz %
803 (DP_LINK_DESC_ALLOC_SIZE_THRESH -
804 HAL_LINK_DESC_ALIGN);
805
806 if (last_bank_sz)
807 n_link_desc_bank += 1;
808 }
809
810 if (n_link_desc_bank > DP_LINK_DESC_BANKS_MAX)
811 return -EINVAL;
812
813 ret = ath12k_dp_link_desc_bank_alloc(ab, link_desc_banks,
814 n_link_desc_bank, last_bank_sz);
815 if (ret)
816 return ret;
817
818 /* Setup link desc idle list for HW internal usage */
819 entry_sz = ath12k_hal_srng_get_entrysize(ab, ring_type);
820 tot_mem_sz = entry_sz * n_link_desc;
821
822 /* Setup scatter desc list when the total memory requirement is more */
823 if (tot_mem_sz > DP_LINK_DESC_ALLOC_SIZE_THRESH &&
824 ring_type != HAL_RXDMA_MONITOR_DESC) {
825 ret = ath12k_dp_scatter_idle_link_desc_setup(ab, tot_mem_sz,
826 n_link_desc_bank,
827 n_link_desc,
828 last_bank_sz);
829 if (ret) {
830 ath12k_warn(ab, "failed to setup scatting idle list descriptor :%d\n",
831 ret);
832 goto fail_desc_bank_free;
833 }
834
835 return 0;
836 }
837
838 spin_lock_bh(&srng->lock);
839
840 ath12k_hal_srng_access_begin(ab, srng);
841
842 for (i = 0; i < n_link_desc_bank; i++) {
843 align_bytes = link_desc_banks[i].vaddr -
844 link_desc_banks[i].vaddr_unaligned;
845 n_entries = (link_desc_banks[i].size - align_bytes) /
846 HAL_LINK_DESC_SIZE;
847 paddr = link_desc_banks[i].paddr;
848 while (n_entries &&
849 (desc = ath12k_hal_srng_src_get_next_entry(ab, srng))) {
850 cookie = DP_LINK_DESC_COOKIE_SET(n_entries, i);
851 ath12k_hal_set_link_desc_addr(desc, cookie, paddr, rbm);
852 n_entries--;
853 paddr += HAL_LINK_DESC_SIZE;
854 }
855 }
856
857 ath12k_hal_srng_access_end(ab, srng);
858
859 spin_unlock_bh(&srng->lock);
860
861 return 0;
862
863 fail_desc_bank_free:
864 ath12k_dp_link_desc_bank_free(ab, link_desc_banks);
865
866 return ret;
867 }
868
ath12k_dp_service_srng(struct ath12k_base * ab,struct ath12k_ext_irq_grp * irq_grp,int budget)869 int ath12k_dp_service_srng(struct ath12k_base *ab,
870 struct ath12k_ext_irq_grp *irq_grp,
871 int budget)
872 {
873 struct napi_struct *napi = &irq_grp->napi;
874 int grp_id = irq_grp->grp_id;
875 int work_done = 0;
876 int i = 0, j;
877 int tot_work_done = 0;
878 enum dp_monitor_mode monitor_mode;
879 u8 ring_mask;
880
881 if (ab->hw_params->ring_mask->tx[grp_id]) {
882 i = fls(ab->hw_params->ring_mask->tx[grp_id]) - 1;
883 ath12k_dp_tx_completion_handler(ab, i);
884 }
885
886 if (ab->hw_params->ring_mask->rx_err[grp_id]) {
887 work_done = ath12k_dp_rx_process_err(ab, napi, budget);
888 budget -= work_done;
889 tot_work_done += work_done;
890 if (budget <= 0)
891 goto done;
892 }
893
894 if (ab->hw_params->ring_mask->rx_wbm_rel[grp_id]) {
895 work_done = ath12k_dp_rx_process_wbm_err(ab,
896 napi,
897 budget);
898 budget -= work_done;
899 tot_work_done += work_done;
900
901 if (budget <= 0)
902 goto done;
903 }
904
905 if (ab->hw_params->ring_mask->rx[grp_id]) {
906 i = fls(ab->hw_params->ring_mask->rx[grp_id]) - 1;
907 work_done = ath12k_dp_rx_process(ab, i, napi,
908 budget);
909 budget -= work_done;
910 tot_work_done += work_done;
911 if (budget <= 0)
912 goto done;
913 }
914
915 if (ab->hw_params->ring_mask->rx_mon_dest[grp_id]) {
916 monitor_mode = ATH12K_DP_RX_MONITOR_MODE;
917 ring_mask = ab->hw_params->ring_mask->rx_mon_dest[grp_id];
918 for (i = 0; i < ab->num_radios; i++) {
919 for (j = 0; j < ab->hw_params->num_rxdma_per_pdev; j++) {
920 int id = i * ab->hw_params->num_rxdma_per_pdev + j;
921
922 if (ring_mask & BIT(id)) {
923 work_done =
924 ath12k_dp_mon_process_ring(ab, id, napi, budget,
925 monitor_mode);
926 budget -= work_done;
927 tot_work_done += work_done;
928
929 if (budget <= 0)
930 goto done;
931 }
932 }
933 }
934 }
935
936 if (ab->hw_params->ring_mask->tx_mon_dest[grp_id]) {
937 monitor_mode = ATH12K_DP_TX_MONITOR_MODE;
938 ring_mask = ab->hw_params->ring_mask->tx_mon_dest[grp_id];
939 for (i = 0; i < ab->num_radios; i++) {
940 for (j = 0; j < ab->hw_params->num_rxdma_per_pdev; j++) {
941 int id = i * ab->hw_params->num_rxdma_per_pdev + j;
942
943 if (ring_mask & BIT(id)) {
944 work_done =
945 ath12k_dp_mon_process_ring(ab, id, napi, budget,
946 monitor_mode);
947 budget -= work_done;
948 tot_work_done += work_done;
949
950 if (budget <= 0)
951 goto done;
952 }
953 }
954 }
955 }
956
957 if (ab->hw_params->ring_mask->reo_status[grp_id])
958 ath12k_dp_rx_process_reo_status(ab);
959
960 if (ab->hw_params->ring_mask->host2rxdma[grp_id]) {
961 struct ath12k_dp *dp = &ab->dp;
962 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
963 LIST_HEAD(list);
964
965 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &list, 0);
966 }
967
968 /* TODO: Implement handler for other interrupts */
969
970 done:
971 return tot_work_done;
972 }
973
ath12k_dp_pdev_free(struct ath12k_base * ab)974 void ath12k_dp_pdev_free(struct ath12k_base *ab)
975 {
976 int i;
977
978 del_timer_sync(&ab->mon_reap_timer);
979
980 for (i = 0; i < ab->num_radios; i++)
981 ath12k_dp_rx_pdev_free(ab, i);
982 }
983
ath12k_dp_pdev_pre_alloc(struct ath12k_base * ab)984 void ath12k_dp_pdev_pre_alloc(struct ath12k_base *ab)
985 {
986 struct ath12k *ar;
987 struct ath12k_pdev_dp *dp;
988 int i;
989
990 for (i = 0; i < ab->num_radios; i++) {
991 ar = ab->pdevs[i].ar;
992 dp = &ar->dp;
993 dp->mac_id = i;
994 atomic_set(&dp->num_tx_pending, 0);
995 init_waitqueue_head(&dp->tx_empty_waitq);
996
997 /* TODO: Add any RXDMA setup required per pdev */
998 }
999 }
1000
ath12k_dp_wmask_compaction_rx_tlv_supported(struct ath12k_base * ab)1001 bool ath12k_dp_wmask_compaction_rx_tlv_supported(struct ath12k_base *ab)
1002 {
1003 if (test_bit(WMI_TLV_SERVICE_WMSK_COMPACTION_RX_TLVS, ab->wmi_ab.svc_map) &&
1004 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_mpdu_start &&
1005 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_msdu_end &&
1006 ab->hw_params->hal_ops->get_hal_rx_compact_ops) {
1007 return true;
1008 }
1009 return false;
1010 }
1011
ath12k_dp_hal_rx_desc_init(struct ath12k_base * ab)1012 void ath12k_dp_hal_rx_desc_init(struct ath12k_base *ab)
1013 {
1014 if (ath12k_dp_wmask_compaction_rx_tlv_supported(ab)) {
1015 /* RX TLVS compaction is supported, hence change the hal_rx_ops
1016 * to compact hal_rx_ops.
1017 */
1018 ab->hal_rx_ops = ab->hw_params->hal_ops->get_hal_rx_compact_ops();
1019 }
1020 ab->hal.hal_desc_sz =
1021 ab->hal_rx_ops->rx_desc_get_desc_size();
1022 }
1023
ath12k_dp_service_mon_ring(struct timer_list * t)1024 static void ath12k_dp_service_mon_ring(struct timer_list *t)
1025 {
1026 struct ath12k_base *ab = from_timer(ab, t, mon_reap_timer);
1027 int i;
1028
1029 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++)
1030 ath12k_dp_mon_process_ring(ab, i, NULL, DP_MON_SERVICE_BUDGET,
1031 ATH12K_DP_RX_MONITOR_MODE);
1032
1033 mod_timer(&ab->mon_reap_timer, jiffies +
1034 msecs_to_jiffies(ATH12K_MON_TIMER_INTERVAL));
1035 }
1036
ath12k_dp_mon_reap_timer_init(struct ath12k_base * ab)1037 static void ath12k_dp_mon_reap_timer_init(struct ath12k_base *ab)
1038 {
1039 if (ab->hw_params->rxdma1_enable)
1040 return;
1041
1042 timer_setup(&ab->mon_reap_timer, ath12k_dp_service_mon_ring, 0);
1043 }
1044
ath12k_dp_pdev_alloc(struct ath12k_base * ab)1045 int ath12k_dp_pdev_alloc(struct ath12k_base *ab)
1046 {
1047 struct ath12k *ar;
1048 int ret;
1049 int i;
1050
1051 ret = ath12k_dp_rx_htt_setup(ab);
1052 if (ret)
1053 goto out;
1054
1055 ath12k_dp_mon_reap_timer_init(ab);
1056
1057 /* TODO: Per-pdev rx ring unlike tx ring which is mapped to different AC's */
1058 for (i = 0; i < ab->num_radios; i++) {
1059 ar = ab->pdevs[i].ar;
1060 ret = ath12k_dp_rx_pdev_alloc(ab, i);
1061 if (ret) {
1062 ath12k_warn(ab, "failed to allocate pdev rx for pdev_id :%d\n",
1063 i);
1064 goto err;
1065 }
1066 ret = ath12k_dp_rx_pdev_mon_attach(ar);
1067 if (ret) {
1068 ath12k_warn(ab, "failed to initialize mon pdev %d\n", i);
1069 goto err;
1070 }
1071 }
1072
1073 return 0;
1074 err:
1075 ath12k_dp_pdev_free(ab);
1076 out:
1077 return ret;
1078 }
1079
ath12k_dp_htt_connect(struct ath12k_dp * dp)1080 int ath12k_dp_htt_connect(struct ath12k_dp *dp)
1081 {
1082 struct ath12k_htc_svc_conn_req conn_req = {0};
1083 struct ath12k_htc_svc_conn_resp conn_resp = {0};
1084 int status;
1085
1086 conn_req.ep_ops.ep_tx_complete = ath12k_dp_htt_htc_tx_complete;
1087 conn_req.ep_ops.ep_rx_complete = ath12k_dp_htt_htc_t2h_msg_handler;
1088
1089 /* connect to control service */
1090 conn_req.service_id = ATH12K_HTC_SVC_ID_HTT_DATA_MSG;
1091
1092 status = ath12k_htc_connect_service(&dp->ab->htc, &conn_req,
1093 &conn_resp);
1094
1095 if (status)
1096 return status;
1097
1098 dp->eid = conn_resp.eid;
1099
1100 return 0;
1101 }
1102
ath12k_dp_update_vdev_search(struct ath12k_vif * arvif)1103 static void ath12k_dp_update_vdev_search(struct ath12k_vif *arvif)
1104 {
1105 switch (arvif->vdev_type) {
1106 case WMI_VDEV_TYPE_STA:
1107 /* TODO: Verify the search type and flags since ast hash
1108 * is not part of peer mapv3
1109 */
1110 arvif->hal_addr_search_flags = HAL_TX_ADDRY_EN;
1111 arvif->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
1112 break;
1113 case WMI_VDEV_TYPE_AP:
1114 case WMI_VDEV_TYPE_IBSS:
1115 arvif->hal_addr_search_flags = HAL_TX_ADDRX_EN;
1116 arvif->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
1117 break;
1118 case WMI_VDEV_TYPE_MONITOR:
1119 default:
1120 return;
1121 }
1122 }
1123
ath12k_dp_vdev_tx_attach(struct ath12k * ar,struct ath12k_vif * arvif)1124 void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_vif *arvif)
1125 {
1126 struct ath12k_base *ab = ar->ab;
1127
1128 arvif->tcl_metadata |= u32_encode_bits(1, HTT_TCL_META_DATA_TYPE) |
1129 u32_encode_bits(arvif->vdev_id,
1130 HTT_TCL_META_DATA_VDEV_ID) |
1131 u32_encode_bits(ar->pdev->pdev_id,
1132 HTT_TCL_META_DATA_PDEV_ID);
1133
1134 /* set HTT extension valid bit to 0 by default */
1135 arvif->tcl_metadata &= ~HTT_TCL_META_DATA_VALID_HTT;
1136
1137 ath12k_dp_update_vdev_search(arvif);
1138 arvif->vdev_id_check_en = true;
1139 arvif->bank_id = ath12k_dp_tx_get_bank_profile(ab, arvif, &ab->dp);
1140
1141 /* TODO: error path for bank id failure */
1142 if (arvif->bank_id == DP_INVALID_BANK_ID) {
1143 ath12k_err(ar->ab, "Failed to initialize DP TX Banks");
1144 return;
1145 }
1146 }
1147
ath12k_dp_cc_cleanup(struct ath12k_base * ab)1148 static void ath12k_dp_cc_cleanup(struct ath12k_base *ab)
1149 {
1150 struct ath12k_rx_desc_info *desc_info;
1151 struct ath12k_tx_desc_info *tx_desc_info, *tmp1;
1152 struct ath12k_dp *dp = &ab->dp;
1153 struct ath12k_skb_cb *skb_cb;
1154 struct sk_buff *skb;
1155 struct ath12k *ar;
1156 int i, j;
1157 u32 pool_id, tx_spt_page;
1158
1159 if (!dp->spt_info)
1160 return;
1161
1162 /* RX Descriptor cleanup */
1163 spin_lock_bh(&dp->rx_desc_lock);
1164
1165 for (i = 0; i < ATH12K_NUM_RX_SPT_PAGES; i++) {
1166 desc_info = dp->spt_info->rxbaddr[i];
1167
1168 for (j = 0; j < ATH12K_MAX_SPT_ENTRIES; j++) {
1169 if (!desc_info[j].in_use) {
1170 list_del(&desc_info[j].list);
1171 continue;
1172 }
1173
1174 skb = desc_info[j].skb;
1175 if (!skb)
1176 continue;
1177
1178 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr,
1179 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
1180 dev_kfree_skb_any(skb);
1181 }
1182 }
1183
1184 for (i = 0; i < ATH12K_NUM_RX_SPT_PAGES; i++) {
1185 if (!dp->spt_info->rxbaddr[i])
1186 continue;
1187
1188 kfree(dp->spt_info->rxbaddr[i]);
1189 dp->spt_info->rxbaddr[i] = NULL;
1190 }
1191
1192 spin_unlock_bh(&dp->rx_desc_lock);
1193
1194 /* TX Descriptor cleanup */
1195 for (i = 0; i < ATH12K_HW_MAX_QUEUES; i++) {
1196 spin_lock_bh(&dp->tx_desc_lock[i]);
1197
1198 list_for_each_entry_safe(tx_desc_info, tmp1, &dp->tx_desc_used_list[i],
1199 list) {
1200 list_del(&tx_desc_info->list);
1201 skb = tx_desc_info->skb;
1202
1203 if (!skb)
1204 continue;
1205
1206 /* if we are unregistering, hw would've been destroyed and
1207 * ar is no longer valid.
1208 */
1209 if (!(test_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags))) {
1210 skb_cb = ATH12K_SKB_CB(skb);
1211 ar = skb_cb->ar;
1212
1213 if (atomic_dec_and_test(&ar->dp.num_tx_pending))
1214 wake_up(&ar->dp.tx_empty_waitq);
1215 }
1216
1217 dma_unmap_single(ab->dev, ATH12K_SKB_CB(skb)->paddr,
1218 skb->len, DMA_TO_DEVICE);
1219 dev_kfree_skb_any(skb);
1220 }
1221
1222 spin_unlock_bh(&dp->tx_desc_lock[i]);
1223 }
1224
1225 for (pool_id = 0; pool_id < ATH12K_HW_MAX_QUEUES; pool_id++) {
1226 spin_lock_bh(&dp->tx_desc_lock[pool_id]);
1227
1228 for (i = 0; i < ATH12K_TX_SPT_PAGES_PER_POOL; i++) {
1229 tx_spt_page = i + pool_id * ATH12K_TX_SPT_PAGES_PER_POOL;
1230 if (!dp->spt_info->txbaddr[tx_spt_page])
1231 continue;
1232
1233 kfree(dp->spt_info->txbaddr[tx_spt_page]);
1234 dp->spt_info->txbaddr[tx_spt_page] = NULL;
1235 }
1236
1237 spin_unlock_bh(&dp->tx_desc_lock[pool_id]);
1238 }
1239
1240 /* unmap SPT pages */
1241 for (i = 0; i < dp->num_spt_pages; i++) {
1242 if (!dp->spt_info[i].vaddr)
1243 continue;
1244
1245 dma_free_coherent(ab->dev, ATH12K_PAGE_SIZE,
1246 dp->spt_info[i].vaddr, dp->spt_info[i].paddr);
1247 dp->spt_info[i].vaddr = NULL;
1248 }
1249
1250 kfree(dp->spt_info);
1251 dp->spt_info = NULL;
1252 }
1253
ath12k_dp_reoq_lut_cleanup(struct ath12k_base * ab)1254 static void ath12k_dp_reoq_lut_cleanup(struct ath12k_base *ab)
1255 {
1256 struct ath12k_dp *dp = &ab->dp;
1257
1258 if (!ab->hw_params->reoq_lut_support)
1259 return;
1260
1261 if (!dp->reoq_lut.vaddr)
1262 return;
1263
1264 dma_free_coherent(ab->dev, DP_REOQ_LUT_SIZE,
1265 dp->reoq_lut.vaddr, dp->reoq_lut.paddr);
1266 dp->reoq_lut.vaddr = NULL;
1267
1268 ath12k_hif_write32(ab,
1269 HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_LUT_BASE0(ab), 0);
1270 }
1271
ath12k_dp_free(struct ath12k_base * ab)1272 void ath12k_dp_free(struct ath12k_base *ab)
1273 {
1274 struct ath12k_dp *dp = &ab->dp;
1275 int i;
1276
1277 ath12k_dp_link_desc_cleanup(ab, dp->link_desc_banks,
1278 HAL_WBM_IDLE_LINK, &dp->wbm_idle_ring);
1279
1280 ath12k_dp_cc_cleanup(ab);
1281 ath12k_dp_reoq_lut_cleanup(ab);
1282 ath12k_dp_deinit_bank_profiles(ab);
1283 ath12k_dp_srng_common_cleanup(ab);
1284
1285 ath12k_dp_rx_reo_cmd_list_cleanup(ab);
1286
1287 for (i = 0; i < ab->hw_params->max_tx_ring; i++) {
1288 kfree(dp->tx_ring[i].tx_status);
1289 dp->tx_ring[i].tx_status = NULL;
1290 }
1291
1292 ath12k_dp_rx_free(ab);
1293 /* Deinit any SOC level resource */
1294 }
1295
ath12k_dp_cc_config(struct ath12k_base * ab)1296 void ath12k_dp_cc_config(struct ath12k_base *ab)
1297 {
1298 u32 cmem_base = ab->qmi.dev_mem[ATH12K_QMI_DEVMEM_CMEM_INDEX].start;
1299 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;
1300 u32 wbm_base = HAL_SEQ_WCSS_UMAC_WBM_REG;
1301 u32 val = 0;
1302
1303 ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG0(ab), cmem_base);
1304
1305 val |= u32_encode_bits(ATH12K_CMEM_ADDR_MSB,
1306 HAL_REO1_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB) |
1307 u32_encode_bits(ATH12K_CC_PPT_MSB,
1308 HAL_REO1_SW_COOKIE_CFG_COOKIE_PPT_MSB) |
1309 u32_encode_bits(ATH12K_CC_SPT_MSB,
1310 HAL_REO1_SW_COOKIE_CFG_COOKIE_SPT_MSB) |
1311 u32_encode_bits(1, HAL_REO1_SW_COOKIE_CFG_ALIGN) |
1312 u32_encode_bits(1, HAL_REO1_SW_COOKIE_CFG_ENABLE) |
1313 u32_encode_bits(1, HAL_REO1_SW_COOKIE_CFG_GLOBAL_ENABLE);
1314
1315 ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG1(ab), val);
1316
1317 /* Enable HW CC for WBM */
1318 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG0, cmem_base);
1319
1320 val = u32_encode_bits(ATH12K_CMEM_ADDR_MSB,
1321 HAL_WBM_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB) |
1322 u32_encode_bits(ATH12K_CC_PPT_MSB,
1323 HAL_WBM_SW_COOKIE_CFG_COOKIE_PPT_MSB) |
1324 u32_encode_bits(ATH12K_CC_SPT_MSB,
1325 HAL_WBM_SW_COOKIE_CFG_COOKIE_SPT_MSB) |
1326 u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_ALIGN);
1327
1328 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG1, val);
1329
1330 /* Enable conversion complete indication */
1331 val = ath12k_hif_read32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG2);
1332 val |= u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_RELEASE_PATH_EN) |
1333 u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_ERR_PATH_EN) |
1334 u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_CONV_IND_EN);
1335
1336 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG2, val);
1337
1338 /* Enable Cookie conversion for WBM2SW Rings */
1339 val = ath12k_hif_read32(ab, wbm_base + HAL_WBM_SW_COOKIE_CONVERT_CFG);
1340 val |= u32_encode_bits(1, HAL_WBM_SW_COOKIE_CONV_CFG_GLOBAL_EN) |
1341 ab->hw_params->hal_params->wbm2sw_cc_enable;
1342
1343 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CONVERT_CFG, val);
1344 }
1345
ath12k_dp_cc_cookie_gen(u16 ppt_idx,u16 spt_idx)1346 static u32 ath12k_dp_cc_cookie_gen(u16 ppt_idx, u16 spt_idx)
1347 {
1348 return (u32)ppt_idx << ATH12K_CC_PPT_SHIFT | spt_idx;
1349 }
1350
ath12k_dp_cc_get_desc_addr_ptr(struct ath12k_base * ab,u16 ppt_idx,u16 spt_idx)1351 static inline void *ath12k_dp_cc_get_desc_addr_ptr(struct ath12k_base *ab,
1352 u16 ppt_idx, u16 spt_idx)
1353 {
1354 struct ath12k_dp *dp = &ab->dp;
1355
1356 return dp->spt_info[ppt_idx].vaddr + spt_idx;
1357 }
1358
ath12k_dp_get_rx_desc(struct ath12k_base * ab,u32 cookie)1359 struct ath12k_rx_desc_info *ath12k_dp_get_rx_desc(struct ath12k_base *ab,
1360 u32 cookie)
1361 {
1362 struct ath12k_dp *dp = &ab->dp;
1363 struct ath12k_rx_desc_info **desc_addr_ptr;
1364 u16 start_ppt_idx, end_ppt_idx, ppt_idx, spt_idx;
1365
1366 ppt_idx = u32_get_bits(cookie, ATH12K_DP_CC_COOKIE_PPT);
1367 spt_idx = u32_get_bits(cookie, ATH12K_DP_CC_COOKIE_SPT);
1368
1369 start_ppt_idx = dp->rx_ppt_base + ATH12K_RX_SPT_PAGE_OFFSET;
1370 end_ppt_idx = start_ppt_idx + ATH12K_NUM_RX_SPT_PAGES;
1371
1372 if (ppt_idx < start_ppt_idx ||
1373 ppt_idx >= end_ppt_idx ||
1374 spt_idx > ATH12K_MAX_SPT_ENTRIES)
1375 return NULL;
1376
1377 ppt_idx = ppt_idx - dp->rx_ppt_base;
1378 desc_addr_ptr = ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, spt_idx);
1379
1380 return *desc_addr_ptr;
1381 }
1382
ath12k_dp_get_tx_desc(struct ath12k_base * ab,u32 cookie)1383 struct ath12k_tx_desc_info *ath12k_dp_get_tx_desc(struct ath12k_base *ab,
1384 u32 cookie)
1385 {
1386 struct ath12k_tx_desc_info **desc_addr_ptr;
1387 u16 start_ppt_idx, end_ppt_idx, ppt_idx, spt_idx;
1388
1389 ppt_idx = u32_get_bits(cookie, ATH12K_DP_CC_COOKIE_PPT);
1390 spt_idx = u32_get_bits(cookie, ATH12K_DP_CC_COOKIE_SPT);
1391
1392 start_ppt_idx = ATH12K_TX_SPT_PAGE_OFFSET;
1393 end_ppt_idx = start_ppt_idx +
1394 (ATH12K_TX_SPT_PAGES_PER_POOL * ATH12K_HW_MAX_QUEUES);
1395
1396 if (ppt_idx < start_ppt_idx ||
1397 ppt_idx >= end_ppt_idx ||
1398 spt_idx > ATH12K_MAX_SPT_ENTRIES)
1399 return NULL;
1400
1401 desc_addr_ptr = ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, spt_idx);
1402
1403 return *desc_addr_ptr;
1404 }
1405
ath12k_dp_cc_desc_init(struct ath12k_base * ab)1406 static int ath12k_dp_cc_desc_init(struct ath12k_base *ab)
1407 {
1408 struct ath12k_dp *dp = &ab->dp;
1409 struct ath12k_rx_desc_info *rx_descs, **rx_desc_addr;
1410 struct ath12k_tx_desc_info *tx_descs, **tx_desc_addr;
1411 u32 i, j, pool_id, tx_spt_page;
1412 u32 ppt_idx, cookie_ppt_idx;
1413
1414 spin_lock_bh(&dp->rx_desc_lock);
1415
1416 /* First ATH12K_NUM_RX_SPT_PAGES of allocated SPT pages are used for RX */
1417 for (i = 0; i < ATH12K_NUM_RX_SPT_PAGES; i++) {
1418 rx_descs = kcalloc(ATH12K_MAX_SPT_ENTRIES, sizeof(*rx_descs),
1419 GFP_ATOMIC);
1420
1421 if (!rx_descs) {
1422 spin_unlock_bh(&dp->rx_desc_lock);
1423 return -ENOMEM;
1424 }
1425
1426 ppt_idx = ATH12K_RX_SPT_PAGE_OFFSET + i;
1427 cookie_ppt_idx = dp->rx_ppt_base + ppt_idx;
1428 dp->spt_info->rxbaddr[i] = &rx_descs[0];
1429
1430 for (j = 0; j < ATH12K_MAX_SPT_ENTRIES; j++) {
1431 rx_descs[j].cookie = ath12k_dp_cc_cookie_gen(cookie_ppt_idx, j);
1432 rx_descs[j].magic = ATH12K_DP_RX_DESC_MAGIC;
1433 list_add_tail(&rx_descs[j].list, &dp->rx_desc_free_list);
1434
1435 /* Update descriptor VA in SPT */
1436 rx_desc_addr = ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, j);
1437 *rx_desc_addr = &rx_descs[j];
1438 }
1439 }
1440
1441 spin_unlock_bh(&dp->rx_desc_lock);
1442
1443 for (pool_id = 0; pool_id < ATH12K_HW_MAX_QUEUES; pool_id++) {
1444 spin_lock_bh(&dp->tx_desc_lock[pool_id]);
1445 for (i = 0; i < ATH12K_TX_SPT_PAGES_PER_POOL; i++) {
1446 tx_descs = kcalloc(ATH12K_MAX_SPT_ENTRIES, sizeof(*tx_descs),
1447 GFP_ATOMIC);
1448
1449 if (!tx_descs) {
1450 spin_unlock_bh(&dp->tx_desc_lock[pool_id]);
1451 /* Caller takes care of TX pending and RX desc cleanup */
1452 return -ENOMEM;
1453 }
1454
1455 tx_spt_page = i + pool_id * ATH12K_TX_SPT_PAGES_PER_POOL;
1456 ppt_idx = ATH12K_TX_SPT_PAGE_OFFSET + tx_spt_page;
1457
1458 dp->spt_info->txbaddr[tx_spt_page] = &tx_descs[0];
1459
1460 for (j = 0; j < ATH12K_MAX_SPT_ENTRIES; j++) {
1461 tx_descs[j].desc_id = ath12k_dp_cc_cookie_gen(ppt_idx, j);
1462 tx_descs[j].pool_id = pool_id;
1463 list_add_tail(&tx_descs[j].list,
1464 &dp->tx_desc_free_list[pool_id]);
1465
1466 /* Update descriptor VA in SPT */
1467 tx_desc_addr =
1468 ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, j);
1469 *tx_desc_addr = &tx_descs[j];
1470 }
1471 }
1472 spin_unlock_bh(&dp->tx_desc_lock[pool_id]);
1473 }
1474 return 0;
1475 }
1476
ath12k_dp_cmem_init(struct ath12k_base * ab,struct ath12k_dp * dp,enum ath12k_dp_desc_type type)1477 static int ath12k_dp_cmem_init(struct ath12k_base *ab,
1478 struct ath12k_dp *dp,
1479 enum ath12k_dp_desc_type type)
1480 {
1481 u32 cmem_base;
1482 int i, start, end;
1483
1484 cmem_base = ab->qmi.dev_mem[ATH12K_QMI_DEVMEM_CMEM_INDEX].start;
1485
1486 switch (type) {
1487 case ATH12K_DP_TX_DESC:
1488 start = ATH12K_TX_SPT_PAGE_OFFSET;
1489 end = start + ATH12K_NUM_TX_SPT_PAGES;
1490 break;
1491 case ATH12K_DP_RX_DESC:
1492 cmem_base += ATH12K_PPT_ADDR_OFFSET(dp->rx_ppt_base);
1493 start = ATH12K_RX_SPT_PAGE_OFFSET;
1494 end = start + ATH12K_NUM_RX_SPT_PAGES;
1495 break;
1496 default:
1497 ath12k_err(ab, "invalid descriptor type %d in cmem init\n", type);
1498 return -EINVAL;
1499 }
1500
1501 /* Write to PPT in CMEM */
1502 for (i = start; i < end; i++)
1503 ath12k_hif_write32(ab, cmem_base + ATH12K_PPT_ADDR_OFFSET(i),
1504 dp->spt_info[i].paddr >> ATH12K_SPT_4K_ALIGN_OFFSET);
1505
1506 return 0;
1507 }
1508
ath12k_dp_cc_init(struct ath12k_base * ab)1509 static int ath12k_dp_cc_init(struct ath12k_base *ab)
1510 {
1511 struct ath12k_dp *dp = &ab->dp;
1512 int i, ret = 0;
1513
1514 INIT_LIST_HEAD(&dp->rx_desc_free_list);
1515 spin_lock_init(&dp->rx_desc_lock);
1516
1517 for (i = 0; i < ATH12K_HW_MAX_QUEUES; i++) {
1518 INIT_LIST_HEAD(&dp->tx_desc_free_list[i]);
1519 INIT_LIST_HEAD(&dp->tx_desc_used_list[i]);
1520 spin_lock_init(&dp->tx_desc_lock[i]);
1521 }
1522
1523 dp->num_spt_pages = ATH12K_NUM_SPT_PAGES;
1524 if (dp->num_spt_pages > ATH12K_MAX_PPT_ENTRIES)
1525 dp->num_spt_pages = ATH12K_MAX_PPT_ENTRIES;
1526
1527 dp->spt_info = kcalloc(dp->num_spt_pages, sizeof(struct ath12k_spt_info),
1528 GFP_KERNEL);
1529
1530 if (!dp->spt_info) {
1531 ath12k_warn(ab, "SPT page allocation failure");
1532 return -ENOMEM;
1533 }
1534
1535 dp->rx_ppt_base = ab->device_id * ATH12K_NUM_RX_SPT_PAGES;
1536
1537 for (i = 0; i < dp->num_spt_pages; i++) {
1538 dp->spt_info[i].vaddr = dma_alloc_coherent(ab->dev,
1539 ATH12K_PAGE_SIZE,
1540 &dp->spt_info[i].paddr,
1541 GFP_KERNEL);
1542
1543 if (!dp->spt_info[i].vaddr) {
1544 ret = -ENOMEM;
1545 goto free;
1546 }
1547
1548 if (dp->spt_info[i].paddr & ATH12K_SPT_4K_ALIGN_CHECK) {
1549 ath12k_warn(ab, "SPT allocated memory is not 4K aligned");
1550 ret = -EINVAL;
1551 goto free;
1552 }
1553 }
1554
1555 ret = ath12k_dp_cmem_init(ab, dp, ATH12K_DP_TX_DESC);
1556 if (ret) {
1557 ath12k_warn(ab, "HW CC Tx cmem init failed %d", ret);
1558 goto free;
1559 }
1560
1561 ret = ath12k_dp_cmem_init(ab, dp, ATH12K_DP_RX_DESC);
1562 if (ret) {
1563 ath12k_warn(ab, "HW CC Rx cmem init failed %d", ret);
1564 goto free;
1565 }
1566
1567 ret = ath12k_dp_cc_desc_init(ab);
1568 if (ret) {
1569 ath12k_warn(ab, "HW CC desc init failed %d", ret);
1570 goto free;
1571 }
1572
1573 return 0;
1574 free:
1575 ath12k_dp_cc_cleanup(ab);
1576 return ret;
1577 }
1578
ath12k_dp_reoq_lut_setup(struct ath12k_base * ab)1579 static int ath12k_dp_reoq_lut_setup(struct ath12k_base *ab)
1580 {
1581 struct ath12k_dp *dp = &ab->dp;
1582
1583 if (!ab->hw_params->reoq_lut_support)
1584 return 0;
1585
1586 dp->reoq_lut.vaddr = dma_alloc_coherent(ab->dev,
1587 DP_REOQ_LUT_SIZE,
1588 &dp->reoq_lut.paddr,
1589 GFP_KERNEL | __GFP_ZERO);
1590 if (!dp->reoq_lut.vaddr) {
1591 ath12k_warn(ab, "failed to allocate memory for reoq table");
1592 return -ENOMEM;
1593 }
1594
1595 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_LUT_BASE0(ab),
1596 dp->reoq_lut.paddr);
1597 return 0;
1598 }
1599
1600 static enum hal_rx_buf_return_buf_manager
ath12k_dp_get_idle_link_rbm(struct ath12k_base * ab)1601 ath12k_dp_get_idle_link_rbm(struct ath12k_base *ab)
1602 {
1603 switch (ab->device_id) {
1604 case 0:
1605 return HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST;
1606 case 1:
1607 return HAL_RX_BUF_RBM_WBM_DEV1_IDLE_DESC_LIST;
1608 case 2:
1609 return HAL_RX_BUF_RBM_WBM_DEV2_IDLE_DESC_LIST;
1610 default:
1611 ath12k_warn(ab, "invalid %d device id, so choose default rbm\n",
1612 ab->device_id);
1613 WARN_ON(1);
1614 return HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST;
1615 }
1616 }
1617
ath12k_dp_alloc(struct ath12k_base * ab)1618 int ath12k_dp_alloc(struct ath12k_base *ab)
1619 {
1620 struct ath12k_dp *dp = &ab->dp;
1621 struct hal_srng *srng = NULL;
1622 size_t size = 0;
1623 u32 n_link_desc = 0;
1624 int ret;
1625 int i;
1626
1627 dp->ab = ab;
1628
1629 INIT_LIST_HEAD(&dp->reo_cmd_list);
1630 INIT_LIST_HEAD(&dp->reo_cmd_cache_flush_list);
1631 spin_lock_init(&dp->reo_cmd_lock);
1632
1633 dp->reo_cmd_cache_flush_count = 0;
1634 dp->idle_link_rbm = ath12k_dp_get_idle_link_rbm(ab);
1635
1636 ret = ath12k_wbm_idle_ring_setup(ab, &n_link_desc);
1637 if (ret) {
1638 ath12k_warn(ab, "failed to setup wbm_idle_ring: %d\n", ret);
1639 return ret;
1640 }
1641
1642 srng = &ab->hal.srng_list[dp->wbm_idle_ring.ring_id];
1643
1644 ret = ath12k_dp_link_desc_setup(ab, dp->link_desc_banks,
1645 HAL_WBM_IDLE_LINK, srng, n_link_desc);
1646 if (ret) {
1647 ath12k_warn(ab, "failed to setup link desc: %d\n", ret);
1648 return ret;
1649 }
1650
1651 ret = ath12k_dp_cc_init(ab);
1652
1653 if (ret) {
1654 ath12k_warn(ab, "failed to setup cookie converter %d\n", ret);
1655 goto fail_link_desc_cleanup;
1656 }
1657 ret = ath12k_dp_init_bank_profiles(ab);
1658 if (ret) {
1659 ath12k_warn(ab, "failed to setup bank profiles %d\n", ret);
1660 goto fail_hw_cc_cleanup;
1661 }
1662
1663 ret = ath12k_dp_srng_common_setup(ab);
1664 if (ret)
1665 goto fail_dp_bank_profiles_cleanup;
1666
1667 size = sizeof(struct hal_wbm_release_ring_tx) * DP_TX_COMP_RING_SIZE;
1668
1669 ret = ath12k_dp_reoq_lut_setup(ab);
1670 if (ret) {
1671 ath12k_warn(ab, "failed to setup reoq table %d\n", ret);
1672 goto fail_cmn_srng_cleanup;
1673 }
1674
1675 for (i = 0; i < ab->hw_params->max_tx_ring; i++) {
1676 dp->tx_ring[i].tcl_data_ring_id = i;
1677
1678 dp->tx_ring[i].tx_status_head = 0;
1679 dp->tx_ring[i].tx_status_tail = DP_TX_COMP_RING_SIZE - 1;
1680 dp->tx_ring[i].tx_status = kmalloc(size, GFP_KERNEL);
1681 if (!dp->tx_ring[i].tx_status) {
1682 ret = -ENOMEM;
1683 /* FIXME: The allocated tx status is not freed
1684 * properly here
1685 */
1686 goto fail_cmn_reoq_cleanup;
1687 }
1688 }
1689
1690 for (i = 0; i < HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX; i++)
1691 ath12k_hal_tx_set_dscp_tid_map(ab, i);
1692
1693 ret = ath12k_dp_rx_alloc(ab);
1694 if (ret)
1695 goto fail_dp_rx_free;
1696
1697 /* Init any SOC level resource for DP */
1698
1699 return 0;
1700
1701 fail_dp_rx_free:
1702 ath12k_dp_rx_free(ab);
1703
1704 fail_cmn_reoq_cleanup:
1705 ath12k_dp_reoq_lut_cleanup(ab);
1706
1707 fail_cmn_srng_cleanup:
1708 ath12k_dp_srng_common_cleanup(ab);
1709
1710 fail_dp_bank_profiles_cleanup:
1711 ath12k_dp_deinit_bank_profiles(ab);
1712
1713 fail_hw_cc_cleanup:
1714 ath12k_dp_cc_cleanup(ab);
1715
1716 fail_link_desc_cleanup:
1717 ath12k_dp_link_desc_cleanup(ab, dp->link_desc_banks,
1718 HAL_WBM_IDLE_LINK, &dp->wbm_idle_ring);
1719
1720 return ret;
1721 }
1722