1 /* 2 * Copyright 2012-2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "dc_state.h" 31 #include "dc_plane.h" 32 #include "grph_object_defs.h" 33 #include "logger_types.h" 34 #include "hdcp_msg_types.h" 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "hwss/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 #include "dml2/dml2_wrapper.h" 46 47 #include "dmub/inc/dmub_cmd.h" 48 49 #include "spl/dc_spl_types.h" 50 51 struct abm_save_restore; 52 53 /* forward declaration */ 54 struct aux_payload; 55 struct set_config_cmd_payload; 56 struct dmub_notification; 57 58 #define DC_VER "3.2.301" 59 60 #define MAX_SURFACES 4 61 #define MAX_PLANES 6 62 #define MAX_STREAMS 6 63 #define MIN_VIEWPORT_SIZE 12 64 #define MAX_NUM_EDP 2 65 #define MAX_HOST_ROUTERS_NUM 2 66 67 /* Display Core Interfaces */ 68 struct dc_versions { 69 const char *dc_ver; 70 struct dmcu_version dmcu_version; 71 }; 72 73 enum dp_protocol_version { 74 DP_VERSION_1_4 = 0, 75 DP_VERSION_2_1, 76 DP_VERSION_UNKNOWN, 77 }; 78 79 enum dc_plane_type { 80 DC_PLANE_TYPE_INVALID, 81 DC_PLANE_TYPE_DCE_RGB, 82 DC_PLANE_TYPE_DCE_UNDERLAY, 83 DC_PLANE_TYPE_DCN_UNIVERSAL, 84 }; 85 86 // Sizes defined as multiples of 64KB 87 enum det_size { 88 DET_SIZE_DEFAULT = 0, 89 DET_SIZE_192KB = 3, 90 DET_SIZE_256KB = 4, 91 DET_SIZE_320KB = 5, 92 DET_SIZE_384KB = 6 93 }; 94 95 96 struct dc_plane_cap { 97 enum dc_plane_type type; 98 uint32_t per_pixel_alpha : 1; 99 struct { 100 uint32_t argb8888 : 1; 101 uint32_t nv12 : 1; 102 uint32_t fp16 : 1; 103 uint32_t p010 : 1; 104 uint32_t ayuv : 1; 105 } pixel_format_support; 106 // max upscaling factor x1000 107 // upscaling factors are always >= 1 108 // for example, 1080p -> 8K is 4.0, or 4000 raw value 109 struct { 110 uint32_t argb8888; 111 uint32_t nv12; 112 uint32_t fp16; 113 } max_upscale_factor; 114 // max downscale factor x1000 115 // downscale factors are always <= 1 116 // for example, 8K -> 1080p is 0.25, or 250 raw value 117 struct { 118 uint32_t argb8888; 119 uint32_t nv12; 120 uint32_t fp16; 121 } max_downscale_factor; 122 // minimal width/height 123 uint32_t min_width; 124 uint32_t min_height; 125 }; 126 127 /** 128 * DOC: color-management-caps 129 * 130 * **Color management caps (DPP and MPC)** 131 * 132 * Modules/color calculates various color operations which are translated to 133 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 134 * DCN1, every new generation comes with fairly major differences in color 135 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 136 * decide mapping to HW block based on logical capabilities. 137 */ 138 139 /** 140 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 141 * @srgb: RGB color space transfer func 142 * @bt2020: BT.2020 transfer func 143 * @gamma2_2: standard gamma 144 * @pq: perceptual quantizer transfer function 145 * @hlg: hybrid log–gamma transfer function 146 */ 147 struct rom_curve_caps { 148 uint16_t srgb : 1; 149 uint16_t bt2020 : 1; 150 uint16_t gamma2_2 : 1; 151 uint16_t pq : 1; 152 uint16_t hlg : 1; 153 }; 154 155 /** 156 * struct dpp_color_caps - color pipeline capabilities for display pipe and 157 * plane blocks 158 * 159 * @dcn_arch: all DCE generations treated the same 160 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 161 * just plain 256-entry lookup 162 * @icsc: input color space conversion 163 * @dgam_ram: programmable degamma LUT 164 * @post_csc: post color space conversion, before gamut remap 165 * @gamma_corr: degamma correction 166 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 167 * with MPC by setting mpc:shared_3d_lut flag 168 * @ogam_ram: programmable out/blend gamma LUT 169 * @ocsc: output color space conversion 170 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 171 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 172 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 173 * 174 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 175 */ 176 struct dpp_color_caps { 177 uint16_t dcn_arch : 1; 178 uint16_t input_lut_shared : 1; 179 uint16_t icsc : 1; 180 uint16_t dgam_ram : 1; 181 uint16_t post_csc : 1; 182 uint16_t gamma_corr : 1; 183 uint16_t hw_3d_lut : 1; 184 uint16_t ogam_ram : 1; 185 uint16_t ocsc : 1; 186 uint16_t dgam_rom_for_yuv : 1; 187 struct rom_curve_caps dgam_rom_caps; 188 struct rom_curve_caps ogam_rom_caps; 189 }; 190 191 /** 192 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 193 * plane combined blocks 194 * 195 * @gamut_remap: color transformation matrix 196 * @ogam_ram: programmable out gamma LUT 197 * @ocsc: output color space conversion matrix 198 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 199 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 200 * instance 201 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 202 */ 203 struct mpc_color_caps { 204 uint16_t gamut_remap : 1; 205 uint16_t ogam_ram : 1; 206 uint16_t ocsc : 1; 207 uint16_t num_3dluts : 3; 208 uint16_t shared_3d_lut:1; 209 struct rom_curve_caps ogam_rom_caps; 210 }; 211 212 /** 213 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 214 * @dpp: color pipes caps for DPP 215 * @mpc: color pipes caps for MPC 216 */ 217 struct dc_color_caps { 218 struct dpp_color_caps dpp; 219 struct mpc_color_caps mpc; 220 }; 221 222 struct dc_dmub_caps { 223 bool psr; 224 bool mclk_sw; 225 bool subvp_psr; 226 bool gecc_enable; 227 uint8_t fams_ver; 228 }; 229 230 struct dc_caps { 231 uint32_t max_streams; 232 uint32_t max_links; 233 uint32_t max_audios; 234 uint32_t max_slave_planes; 235 uint32_t max_slave_yuv_planes; 236 uint32_t max_slave_rgb_planes; 237 uint32_t max_planes; 238 uint32_t max_downscale_ratio; 239 uint32_t i2c_speed_in_khz; 240 uint32_t i2c_speed_in_khz_hdcp; 241 uint32_t dmdata_alloc_size; 242 unsigned int max_cursor_size; 243 unsigned int max_video_width; 244 /* 245 * max video plane width that can be safely assumed to be always 246 * supported by single DPP pipe. 247 */ 248 unsigned int max_optimizable_video_width; 249 unsigned int min_horizontal_blanking_period; 250 int linear_pitch_alignment; 251 bool dcc_const_color; 252 bool dynamic_audio; 253 bool is_apu; 254 bool dual_link_dvi; 255 bool post_blend_color_processing; 256 bool force_dp_tps4_for_cp2520; 257 bool disable_dp_clk_share; 258 bool psp_setup_panel_mode; 259 bool extended_aux_timeout_support; 260 bool dmcub_support; 261 bool zstate_support; 262 bool ips_support; 263 uint32_t num_of_internal_disp; 264 enum dp_protocol_version max_dp_protocol_version; 265 unsigned int mall_size_per_mem_channel; 266 unsigned int mall_size_total; 267 unsigned int cursor_cache_size; 268 struct dc_plane_cap planes[MAX_PLANES]; 269 struct dc_color_caps color; 270 struct dc_dmub_caps dmub_caps; 271 bool dp_hpo; 272 bool dp_hdmi21_pcon_support; 273 bool edp_dsc_support; 274 bool vbios_lttpr_aware; 275 bool vbios_lttpr_enable; 276 uint32_t max_otg_num; 277 uint32_t max_cab_allocation_bytes; 278 uint32_t cache_line_size; 279 uint32_t cache_num_ways; 280 uint16_t subvp_fw_processing_delay_us; 281 uint8_t subvp_drr_max_vblank_margin_us; 282 uint16_t subvp_prefetch_end_to_mall_start_us; 283 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 284 uint16_t subvp_pstate_allow_width_us; 285 uint16_t subvp_vertical_int_margin_us; 286 bool seamless_odm; 287 uint32_t max_v_total; 288 bool vtotal_limited_by_fp2; 289 uint32_t max_disp_clock_khz_at_vmin; 290 uint8_t subvp_drr_vblank_start_margin_us; 291 bool cursor_not_scaled; 292 bool dcmode_power_limits_present; 293 bool sequential_ono; 294 /* Conservative limit for DCC cases which require ODM4:1 to support*/ 295 uint32_t dcc_plane_width_limit; 296 }; 297 298 struct dc_bug_wa { 299 bool no_connect_phy_config; 300 bool dedcn20_305_wa; 301 bool skip_clock_update; 302 bool lt_early_cr_pattern; 303 struct { 304 uint8_t uclk : 1; 305 uint8_t fclk : 1; 306 uint8_t dcfclk : 1; 307 uint8_t dcfclk_ds: 1; 308 } clock_update_disable_mask; 309 bool skip_psr_ips_crtc_disable; 310 }; 311 struct dc_dcc_surface_param { 312 struct dc_size surface_size; 313 enum surface_pixel_format format; 314 unsigned int plane0_pitch; 315 struct dc_size plane1_size; 316 unsigned int plane1_pitch; 317 union { 318 enum swizzle_mode_values swizzle_mode; 319 enum swizzle_mode_addr3_values swizzle_mode_addr3; 320 }; 321 enum dc_scan_direction scan; 322 }; 323 324 struct dc_dcc_setting { 325 unsigned int max_compressed_blk_size; 326 unsigned int max_uncompressed_blk_size; 327 bool independent_64b_blks; 328 //These bitfields to be used starting with DCN 3.0 329 struct { 330 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 331 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 332 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 333 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 334 uint32_t dcc_256_256 : 1; //available in ASICs starting with DCN 4.0x (the best compression case) 335 uint32_t dcc_256_128 : 1; //available in ASICs starting with DCN 4.0x 336 uint32_t dcc_256_64 : 1; //available in ASICs starting with DCN 4.0x (the worst compression case) 337 } dcc_controls; 338 }; 339 340 struct dc_surface_dcc_cap { 341 union { 342 struct { 343 struct dc_dcc_setting rgb; 344 } grph; 345 346 struct { 347 struct dc_dcc_setting luma; 348 struct dc_dcc_setting chroma; 349 } video; 350 }; 351 352 bool capable; 353 bool const_color_support; 354 }; 355 356 struct dc_static_screen_params { 357 struct { 358 bool force_trigger; 359 bool cursor_update; 360 bool surface_update; 361 bool overlay_update; 362 } triggers; 363 unsigned int num_frames; 364 }; 365 366 367 /* Surface update type is used by dc_update_surfaces_and_stream 368 * The update type is determined at the very beginning of the function based 369 * on parameters passed in and decides how much programming (or updating) is 370 * going to be done during the call. 371 * 372 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 373 * logical calculations or hardware register programming. This update MUST be 374 * ISR safe on windows. Currently fast update will only be used to flip surface 375 * address. 376 * 377 * UPDATE_TYPE_MED is used for slower updates which require significant hw 378 * re-programming however do not affect bandwidth consumption or clock 379 * requirements. At present, this is the level at which front end updates 380 * that do not require us to run bw_calcs happen. These are in/out transfer func 381 * updates, viewport offset changes, recout size changes and pixel depth changes. 382 * This update can be done at ISR, but we want to minimize how often this happens. 383 * 384 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 385 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 386 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 387 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 388 * a full update. This cannot be done at ISR level and should be a rare event. 389 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 390 * underscan we don't expect to see this call at all. 391 */ 392 393 enum surface_update_type { 394 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 395 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 396 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 397 }; 398 399 /* Forward declaration*/ 400 struct dc; 401 struct dc_plane_state; 402 struct dc_state; 403 404 struct dc_cap_funcs { 405 bool (*get_dcc_compression_cap)(const struct dc *dc, 406 const struct dc_dcc_surface_param *input, 407 struct dc_surface_dcc_cap *output); 408 bool (*get_subvp_en)(struct dc *dc, struct dc_state *context); 409 }; 410 411 struct link_training_settings; 412 413 union allow_lttpr_non_transparent_mode { 414 struct { 415 bool DP1_4A : 1; 416 bool DP2_0 : 1; 417 } bits; 418 unsigned char raw; 419 }; 420 421 /* Structure to hold configuration flags set by dm at dc creation. */ 422 struct dc_config { 423 bool gpu_vm_support; 424 bool disable_disp_pll_sharing; 425 bool fbc_support; 426 bool disable_fractional_pwm; 427 bool allow_seamless_boot_optimization; 428 bool seamless_boot_edp_requested; 429 bool edp_not_connected; 430 bool edp_no_power_sequencing; 431 bool force_enum_edp; 432 bool forced_clocks; 433 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 434 bool multi_mon_pp_mclk_switch; 435 bool disable_dmcu; 436 bool enable_4to1MPC; 437 bool enable_windowed_mpo_odm; 438 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 439 uint32_t allow_edp_hotplug_detection; 440 bool clamp_min_dcfclk; 441 uint64_t vblank_alignment_dto_params; 442 uint8_t vblank_alignment_max_frame_time_diff; 443 bool is_asymmetric_memory; 444 bool is_single_rank_dimm; 445 bool is_vmin_only_asic; 446 bool use_spl; 447 bool prefer_easf; 448 bool use_pipe_ctx_sync_logic; 449 bool ignore_dpref_ss; 450 bool enable_mipi_converter_optimization; 451 bool use_default_clock_table; 452 bool force_bios_enable_lttpr; 453 uint8_t force_bios_fixed_vs; 454 int sdpif_request_limit_words_per_umc; 455 bool dc_mode_clk_limit_support; 456 bool EnableMinDispClkODM; 457 bool enable_auto_dpm_test_logs; 458 unsigned int disable_ips; 459 unsigned int disable_ips_in_vpb; 460 bool usb4_bw_alloc_support; 461 bool allow_0_dtb_clk; 462 bool use_assr_psp_message; 463 bool support_edp0_on_dp1; 464 unsigned int enable_fpo_flicker_detection; 465 bool disable_hbr_audio_dp2; 466 bool consolidated_dpia_dp_lt; 467 }; 468 469 enum visual_confirm { 470 VISUAL_CONFIRM_DISABLE = 0, 471 VISUAL_CONFIRM_SURFACE = 1, 472 VISUAL_CONFIRM_HDR = 2, 473 VISUAL_CONFIRM_MPCTREE = 4, 474 VISUAL_CONFIRM_PSR = 5, 475 VISUAL_CONFIRM_SWAPCHAIN = 6, 476 VISUAL_CONFIRM_FAMS = 7, 477 VISUAL_CONFIRM_SWIZZLE = 9, 478 VISUAL_CONFIRM_REPLAY = 12, 479 VISUAL_CONFIRM_SUBVP = 14, 480 VISUAL_CONFIRM_MCLK_SWITCH = 16, 481 VISUAL_CONFIRM_FAMS2 = 19, 482 VISUAL_CONFIRM_HW_CURSOR = 20, 483 }; 484 485 enum dc_psr_power_opts { 486 psr_power_opt_invalid = 0x0, 487 psr_power_opt_smu_opt_static_screen = 0x1, 488 psr_power_opt_z10_static_screen = 0x10, 489 psr_power_opt_ds_disable_allow = 0x100, 490 }; 491 492 enum dml_hostvm_override_opts { 493 DML_HOSTVM_NO_OVERRIDE = 0x0, 494 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 495 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 496 }; 497 498 enum dc_replay_power_opts { 499 replay_power_opt_invalid = 0x0, 500 replay_power_opt_smu_opt_static_screen = 0x1, 501 replay_power_opt_z10_static_screen = 0x10, 502 }; 503 504 enum dcc_option { 505 DCC_ENABLE = 0, 506 DCC_DISABLE = 1, 507 DCC_HALF_REQ_DISALBE = 2, 508 }; 509 510 enum in_game_fams_config { 511 INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams 512 INGAME_FAMS_DISABLE, // disable in-game fams 513 INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display 514 INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR strategies 515 }; 516 517 /** 518 * enum pipe_split_policy - Pipe split strategy supported by DCN 519 * 520 * This enum is used to define the pipe split policy supported by DCN. By 521 * default, DC favors MPC_SPLIT_DYNAMIC. 522 */ 523 enum pipe_split_policy { 524 /** 525 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 526 * pipe in order to bring the best trade-off between performance and 527 * power consumption. This is the recommended option. 528 */ 529 MPC_SPLIT_DYNAMIC = 0, 530 531 /** 532 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 533 * try any sort of split optimization. 534 */ 535 MPC_SPLIT_AVOID = 1, 536 537 /** 538 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 539 * optimize the pipe utilization when using a single display; if the 540 * user connects to a second display, DC will avoid pipe split. 541 */ 542 MPC_SPLIT_AVOID_MULT_DISP = 2, 543 }; 544 545 enum wm_report_mode { 546 WM_REPORT_DEFAULT = 0, 547 WM_REPORT_OVERRIDE = 1, 548 }; 549 enum dtm_pstate{ 550 dtm_level_p0 = 0,/*highest voltage*/ 551 dtm_level_p1, 552 dtm_level_p2, 553 dtm_level_p3, 554 dtm_level_p4,/*when active_display_count = 0*/ 555 }; 556 557 enum dcn_pwr_state { 558 DCN_PWR_STATE_UNKNOWN = -1, 559 DCN_PWR_STATE_MISSION_MODE = 0, 560 DCN_PWR_STATE_LOW_POWER = 3, 561 }; 562 563 enum dcn_zstate_support_state { 564 DCN_ZSTATE_SUPPORT_UNKNOWN, 565 DCN_ZSTATE_SUPPORT_ALLOW, 566 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 567 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 568 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 569 DCN_ZSTATE_SUPPORT_DISALLOW, 570 }; 571 572 /* 573 * struct dc_clocks - DC pipe clocks 574 * 575 * For any clocks that may differ per pipe only the max is stored in this 576 * structure 577 */ 578 struct dc_clocks { 579 int dispclk_khz; 580 int actual_dispclk_khz; 581 int dppclk_khz; 582 int actual_dppclk_khz; 583 int disp_dpp_voltage_level_khz; 584 int dcfclk_khz; 585 int socclk_khz; 586 int dcfclk_deep_sleep_khz; 587 int fclk_khz; 588 int phyclk_khz; 589 int dramclk_khz; 590 bool p_state_change_support; 591 enum dcn_zstate_support_state zstate_support; 592 bool dtbclk_en; 593 int ref_dtbclk_khz; 594 bool fclk_p_state_change_support; 595 enum dcn_pwr_state pwr_state; 596 /* 597 * Elements below are not compared for the purposes of 598 * optimization required 599 */ 600 bool prev_p_state_change_support; 601 bool fclk_prev_p_state_change_support; 602 int num_ways; 603 int host_router_bw_kbps[MAX_HOST_ROUTERS_NUM]; 604 605 /* 606 * @fw_based_mclk_switching 607 * 608 * DC has a mechanism that leverage the variable refresh rate to switch 609 * memory clock in cases that we have a large latency to achieve the 610 * memory clock change and a short vblank window. DC has some 611 * requirements to enable this feature, and this field describes if the 612 * system support or not such a feature. 613 */ 614 bool fw_based_mclk_switching; 615 bool fw_based_mclk_switching_shut_down; 616 int prev_num_ways; 617 enum dtm_pstate dtm_level; 618 int max_supported_dppclk_khz; 619 int max_supported_dispclk_khz; 620 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 621 int bw_dispclk_khz; 622 int idle_dramclk_khz; 623 int idle_fclk_khz; 624 }; 625 626 struct dc_bw_validation_profile { 627 bool enable; 628 629 unsigned long long total_ticks; 630 unsigned long long voltage_level_ticks; 631 unsigned long long watermark_ticks; 632 unsigned long long rq_dlg_ticks; 633 634 unsigned long long total_count; 635 unsigned long long skip_fast_count; 636 unsigned long long skip_pass_count; 637 unsigned long long skip_fail_count; 638 }; 639 640 #define BW_VAL_TRACE_SETUP() \ 641 unsigned long long end_tick = 0; \ 642 unsigned long long voltage_level_tick = 0; \ 643 unsigned long long watermark_tick = 0; \ 644 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 645 dm_get_timestamp(dc->ctx) : 0 646 647 #define BW_VAL_TRACE_COUNT() \ 648 if (dc->debug.bw_val_profile.enable) \ 649 dc->debug.bw_val_profile.total_count++ 650 651 #define BW_VAL_TRACE_SKIP(status) \ 652 if (dc->debug.bw_val_profile.enable) { \ 653 if (!voltage_level_tick) \ 654 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 655 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 656 } 657 658 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 659 if (dc->debug.bw_val_profile.enable) \ 660 voltage_level_tick = dm_get_timestamp(dc->ctx) 661 662 #define BW_VAL_TRACE_END_WATERMARKS() \ 663 if (dc->debug.bw_val_profile.enable) \ 664 watermark_tick = dm_get_timestamp(dc->ctx) 665 666 #define BW_VAL_TRACE_FINISH() \ 667 if (dc->debug.bw_val_profile.enable) { \ 668 end_tick = dm_get_timestamp(dc->ctx); \ 669 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 670 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 671 if (watermark_tick) { \ 672 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 673 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 674 } \ 675 } 676 677 union mem_low_power_enable_options { 678 struct { 679 bool vga: 1; 680 bool i2c: 1; 681 bool dmcu: 1; 682 bool dscl: 1; 683 bool cm: 1; 684 bool mpc: 1; 685 bool optc: 1; 686 bool vpg: 1; 687 bool afmt: 1; 688 } bits; 689 uint32_t u32All; 690 }; 691 692 union root_clock_optimization_options { 693 struct { 694 bool dpp: 1; 695 bool dsc: 1; 696 bool hdmistream: 1; 697 bool hdmichar: 1; 698 bool dpstream: 1; 699 bool symclk32_se: 1; 700 bool symclk32_le: 1; 701 bool symclk_fe: 1; 702 bool physymclk: 1; 703 bool dpiasymclk: 1; 704 uint32_t reserved: 22; 705 } bits; 706 uint32_t u32All; 707 }; 708 709 union fine_grain_clock_gating_enable_options { 710 struct { 711 bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */ 712 bool dchub : 1; /* Display controller hub */ 713 bool dchubbub : 1; 714 bool dpp : 1; /* Display pipes and planes */ 715 bool opp : 1; /* Output pixel processing */ 716 bool optc : 1; /* Output pipe timing combiner */ 717 bool dio : 1; /* Display output */ 718 bool dwb : 1; /* Display writeback */ 719 bool mmhubbub : 1; /* Multimedia hub */ 720 bool dmu : 1; /* Display core management unit */ 721 bool az : 1; /* Azalia */ 722 bool dchvm : 1; 723 bool dsc : 1; /* Display stream compression */ 724 725 uint32_t reserved : 19; 726 } bits; 727 uint32_t u32All; 728 }; 729 730 enum pg_hw_pipe_resources { 731 PG_HUBP = 0, 732 PG_DPP, 733 PG_DSC, 734 PG_MPCC, 735 PG_OPP, 736 PG_OPTC, 737 PG_DPSTREAM, 738 PG_HDMISTREAM, 739 PG_PHYSYMCLK, 740 PG_HW_PIPE_RESOURCES_NUM_ELEMENT 741 }; 742 743 enum pg_hw_resources { 744 PG_DCCG = 0, 745 PG_DCIO, 746 PG_DIO, 747 PG_DCHUBBUB, 748 PG_DCHVM, 749 PG_DWB, 750 PG_HPO, 751 PG_HW_RESOURCES_NUM_ELEMENT 752 }; 753 754 struct pg_block_update { 755 bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES]; 756 bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT]; 757 }; 758 759 union dpia_debug_options { 760 struct { 761 uint32_t disable_dpia:1; /* bit 0 */ 762 uint32_t force_non_lttpr:1; /* bit 1 */ 763 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 764 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 765 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 766 uint32_t disable_usb4_pm_support:1; /* bit 5 */ 767 uint32_t enable_consolidated_dpia_dp_lt:1; /* bit 6 */ 768 uint32_t reserved:25; 769 } bits; 770 uint32_t raw; 771 }; 772 773 /* AUX wake work around options 774 * 0: enable/disable work around 775 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 776 * 15-2: reserved 777 * 31-16: timeout in ms 778 */ 779 union aux_wake_wa_options { 780 struct { 781 uint32_t enable_wa : 1; 782 uint32_t use_default_timeout : 1; 783 uint32_t rsvd: 14; 784 uint32_t timeout_ms : 16; 785 } bits; 786 uint32_t raw; 787 }; 788 789 struct dc_debug_data { 790 uint32_t ltFailCount; 791 uint32_t i2cErrorCount; 792 uint32_t auxErrorCount; 793 }; 794 795 struct dc_phy_addr_space_config { 796 struct { 797 uint64_t start_addr; 798 uint64_t end_addr; 799 uint64_t fb_top; 800 uint64_t fb_offset; 801 uint64_t fb_base; 802 uint64_t agp_top; 803 uint64_t agp_bot; 804 uint64_t agp_base; 805 } system_aperture; 806 807 struct { 808 uint64_t page_table_start_addr; 809 uint64_t page_table_end_addr; 810 uint64_t page_table_base_addr; 811 bool base_addr_is_mc_addr; 812 } gart_config; 813 814 bool valid; 815 bool is_hvm_enabled; 816 uint64_t page_table_default_page_addr; 817 }; 818 819 struct dc_virtual_addr_space_config { 820 uint64_t page_table_base_addr; 821 uint64_t page_table_start_addr; 822 uint64_t page_table_end_addr; 823 uint32_t page_table_block_size_in_bytes; 824 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 825 }; 826 827 struct dc_bounding_box_overrides { 828 int sr_exit_time_ns; 829 int sr_enter_plus_exit_time_ns; 830 int sr_exit_z8_time_ns; 831 int sr_enter_plus_exit_z8_time_ns; 832 int urgent_latency_ns; 833 int percent_of_ideal_drambw; 834 int dram_clock_change_latency_ns; 835 int dummy_clock_change_latency_ns; 836 int fclk_clock_change_latency_ns; 837 /* This forces a hard min on the DCFCLK we use 838 * for DML. Unlike the debug option for forcing 839 * DCFCLK, this override affects watermark calculations 840 */ 841 int min_dcfclk_mhz; 842 }; 843 844 struct dc_state; 845 struct resource_pool; 846 struct dce_hwseq; 847 struct link_service; 848 849 /* 850 * struct dc_debug_options - DC debug struct 851 * 852 * This struct provides a simple mechanism for developers to change some 853 * configurations, enable/disable features, and activate extra debug options. 854 * This can be very handy to narrow down whether some specific feature is 855 * causing an issue or not. 856 */ 857 struct dc_debug_options { 858 bool native422_support; 859 bool disable_dsc; 860 enum visual_confirm visual_confirm; 861 int visual_confirm_rect_height; 862 863 bool sanity_checks; 864 bool max_disp_clk; 865 bool surface_trace; 866 bool timing_trace; 867 bool clock_trace; 868 bool validation_trace; 869 bool bandwidth_calcs_trace; 870 int max_downscale_src_width; 871 872 /* stutter efficiency related */ 873 bool disable_stutter; 874 bool use_max_lb; 875 enum dcc_option disable_dcc; 876 877 /* 878 * @pipe_split_policy: Define which pipe split policy is used by the 879 * display core. 880 */ 881 enum pipe_split_policy pipe_split_policy; 882 bool force_single_disp_pipe_split; 883 bool voltage_align_fclk; 884 bool disable_min_fclk; 885 886 bool disable_dfs_bypass; 887 bool disable_dpp_power_gate; 888 bool disable_hubp_power_gate; 889 bool disable_dsc_power_gate; 890 bool disable_optc_power_gate; 891 bool disable_hpo_power_gate; 892 int dsc_min_slice_height_override; 893 int dsc_bpp_increment_div; 894 bool disable_pplib_wm_range; 895 enum wm_report_mode pplib_wm_report_mode; 896 unsigned int min_disp_clk_khz; 897 unsigned int min_dpp_clk_khz; 898 unsigned int min_dram_clk_khz; 899 int sr_exit_time_dpm0_ns; 900 int sr_enter_plus_exit_time_dpm0_ns; 901 int sr_exit_time_ns; 902 int sr_enter_plus_exit_time_ns; 903 int sr_exit_z8_time_ns; 904 int sr_enter_plus_exit_z8_time_ns; 905 int urgent_latency_ns; 906 uint32_t underflow_assert_delay_us; 907 int percent_of_ideal_drambw; 908 int dram_clock_change_latency_ns; 909 bool optimized_watermark; 910 int always_scale; 911 bool disable_pplib_clock_request; 912 bool disable_clock_gate; 913 bool disable_mem_low_power; 914 bool pstate_enabled; 915 bool disable_dmcu; 916 bool force_abm_enable; 917 bool disable_stereo_support; 918 bool vsr_support; 919 bool performance_trace; 920 bool az_endpoint_mute_only; 921 bool always_use_regamma; 922 bool recovery_enabled; 923 bool avoid_vbios_exec_table; 924 bool scl_reset_length10; 925 bool hdmi20_disable; 926 bool skip_detection_link_training; 927 uint32_t edid_read_retry_times; 928 unsigned int force_odm_combine; //bit vector based on otg inst 929 unsigned int seamless_boot_odm_combine; 930 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 931 int minimum_z8_residency_time; 932 int minimum_z10_residency_time; 933 bool disable_z9_mpc; 934 unsigned int force_fclk_khz; 935 bool enable_tri_buf; 936 bool ips_disallow_entry; 937 bool dmub_offload_enabled; 938 bool dmcub_emulation; 939 bool disable_idle_power_optimizations; 940 unsigned int mall_size_override; 941 unsigned int mall_additional_timer_percent; 942 bool mall_error_as_fatal; 943 bool dmub_command_table; /* for testing only */ 944 struct dc_bw_validation_profile bw_val_profile; 945 bool disable_fec; 946 bool disable_48mhz_pwrdwn; 947 /* This forces a hard min on the DCFCLK requested to SMU/PP 948 * watermarks are not affected. 949 */ 950 unsigned int force_min_dcfclk_mhz; 951 int dwb_fi_phase; 952 bool disable_timing_sync; 953 bool cm_in_bypass; 954 int force_clock_mode;/*every mode change.*/ 955 956 bool disable_dram_clock_change_vactive_support; 957 bool validate_dml_output; 958 bool enable_dmcub_surface_flip; 959 bool usbc_combo_phy_reset_wa; 960 bool enable_dram_clock_change_one_display_vactive; 961 /* TODO - remove once tested */ 962 bool legacy_dp2_lt; 963 bool set_mst_en_for_sst; 964 bool disable_uhbr; 965 bool force_dp2_lt_fallback_method; 966 bool ignore_cable_id; 967 union mem_low_power_enable_options enable_mem_low_power; 968 union root_clock_optimization_options root_clock_optimization; 969 union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating; 970 bool hpo_optimization; 971 bool force_vblank_alignment; 972 973 /* Enable dmub aux for legacy ddc */ 974 bool enable_dmub_aux_for_legacy_ddc; 975 bool disable_fams; 976 enum in_game_fams_config disable_fams_gaming; 977 /* FEC/PSR1 sequence enable delay in 100us */ 978 uint8_t fec_enable_delay_in100us; 979 bool enable_driver_sequence_debug; 980 enum det_size crb_alloc_policy; 981 int crb_alloc_policy_min_disp_count; 982 bool disable_z10; 983 bool enable_z9_disable_interface; 984 bool psr_skip_crtc_disable; 985 uint32_t ips_skip_crtc_disable_mask; 986 union dpia_debug_options dpia_debug; 987 bool disable_fixed_vs_aux_timeout_wa; 988 uint32_t fixed_vs_aux_delay_config_wa; 989 bool force_disable_subvp; 990 bool force_subvp_mclk_switch; 991 bool allow_sw_cursor_fallback; 992 unsigned int force_subvp_num_ways; 993 unsigned int force_mall_ss_num_ways; 994 bool alloc_extra_way_for_cursor; 995 uint32_t subvp_extra_lines; 996 bool force_usr_allow; 997 /* uses value at boot and disables switch */ 998 bool disable_dtb_ref_clk_switch; 999 bool extended_blank_optimization; 1000 union aux_wake_wa_options aux_wake_wa; 1001 uint32_t mst_start_top_delay; 1002 uint8_t psr_power_use_phy_fsm; 1003 enum dml_hostvm_override_opts dml_hostvm_override; 1004 bool dml_disallow_alternate_prefetch_modes; 1005 bool use_legacy_soc_bb_mechanism; 1006 bool exit_idle_opt_for_cursor_updates; 1007 bool using_dml2; 1008 bool enable_single_display_2to1_odm_policy; 1009 bool enable_double_buffered_dsc_pg_support; 1010 bool enable_dp_dig_pixel_rate_div_policy; 1011 bool using_dml21; 1012 enum lttpr_mode lttpr_mode_override; 1013 unsigned int dsc_delay_factor_wa_x1000; 1014 unsigned int min_prefetch_in_strobe_ns; 1015 bool disable_unbounded_requesting; 1016 bool dig_fifo_off_in_blank; 1017 bool override_dispclk_programming; 1018 bool otg_crc_db; 1019 bool disallow_dispclk_dppclk_ds; 1020 bool disable_fpo_optimizations; 1021 bool support_eDP1_5; 1022 uint32_t fpo_vactive_margin_us; 1023 bool disable_fpo_vactive; 1024 bool disable_boot_optimizations; 1025 bool override_odm_optimization; 1026 bool minimize_dispclk_using_odm; 1027 bool disable_subvp_high_refresh; 1028 bool disable_dp_plus_plus_wa; 1029 uint32_t fpo_vactive_min_active_margin_us; 1030 uint32_t fpo_vactive_max_blank_us; 1031 bool enable_hpo_pg_support; 1032 bool enable_legacy_fast_update; 1033 bool disable_dc_mode_overwrite; 1034 bool replay_skip_crtc_disabled; 1035 bool ignore_pg;/*do nothing, let pmfw control it*/ 1036 bool psp_disabled_wa; 1037 unsigned int ips2_eval_delay_us; 1038 unsigned int ips2_entry_delay_us; 1039 bool optimize_ips_handshake; 1040 bool disable_dmub_reallow_idle; 1041 bool disable_timeout; 1042 bool disable_extblankadj; 1043 bool enable_idle_reg_checks; 1044 unsigned int static_screen_wait_frames; 1045 uint32_t pwm_freq; 1046 bool force_chroma_subsampling_1tap; 1047 unsigned int dcc_meta_propagation_delay_us; 1048 bool disable_422_left_edge_pixel; 1049 bool dml21_force_pstate_method; 1050 uint32_t dml21_force_pstate_method_values[MAX_PIPES]; 1051 uint32_t dml21_disable_pstate_method_mask; 1052 union dmub_fams2_global_feature_config fams2_config; 1053 bool enable_legacy_clock_update; 1054 unsigned int force_cositing; 1055 unsigned int disable_spl; 1056 unsigned int force_easf; 1057 unsigned int force_sharpness; 1058 unsigned int force_sharpness_level; 1059 unsigned int force_lls; 1060 bool notify_dpia_hr_bw; 1061 bool enable_ips_visual_confirm; 1062 unsigned int sharpen_policy; 1063 unsigned int scale_to_sharpness_policy; 1064 bool skip_full_updated_if_possible; 1065 }; 1066 1067 1068 /* Generic structure that can be used to query properties of DC. More fields 1069 * can be added as required. 1070 */ 1071 struct dc_current_properties { 1072 unsigned int cursor_size_limit; 1073 }; 1074 1075 enum frame_buffer_mode { 1076 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 1077 FRAME_BUFFER_MODE_ZFB_ONLY, 1078 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 1079 } ; 1080 1081 struct dchub_init_data { 1082 int64_t zfb_phys_addr_base; 1083 int64_t zfb_mc_base_addr; 1084 uint64_t zfb_size_in_byte; 1085 enum frame_buffer_mode fb_mode; 1086 bool dchub_initialzied; 1087 bool dchub_info_valid; 1088 }; 1089 1090 struct dml2_soc_bb; 1091 1092 struct dc_init_data { 1093 struct hw_asic_id asic_id; 1094 void *driver; /* ctx */ 1095 struct cgs_device *cgs_device; 1096 struct dc_bounding_box_overrides bb_overrides; 1097 1098 int num_virtual_links; 1099 /* 1100 * If 'vbios_override' not NULL, it will be called instead 1101 * of the real VBIOS. Intended use is Diagnostics on FPGA. 1102 */ 1103 struct dc_bios *vbios_override; 1104 enum dce_environment dce_environment; 1105 1106 struct dmub_offload_funcs *dmub_if; 1107 struct dc_reg_helper_state *dmub_offload; 1108 1109 struct dc_config flags; 1110 uint64_t log_mask; 1111 1112 struct dpcd_vendor_signature vendor_signature; 1113 bool force_smu_not_present; 1114 /* 1115 * IP offset for run time initializaion of register addresses 1116 * 1117 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 1118 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 1119 * before them. 1120 */ 1121 uint32_t *dcn_reg_offsets; 1122 uint32_t *nbio_reg_offsets; 1123 uint32_t *clk_reg_offsets; 1124 struct dml2_soc_bb *bb_from_dmub; 1125 }; 1126 1127 struct dc_callback_init { 1128 struct cp_psp cp_psp; 1129 }; 1130 1131 struct dc *dc_create(const struct dc_init_data *init_params); 1132 void dc_hardware_init(struct dc *dc); 1133 1134 int dc_get_vmid_use_vector(struct dc *dc); 1135 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1136 /* Returns the number of vmids supported */ 1137 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1138 void dc_init_callbacks(struct dc *dc, 1139 const struct dc_callback_init *init_params); 1140 void dc_deinit_callbacks(struct dc *dc); 1141 void dc_destroy(struct dc **dc); 1142 1143 /* Surface Interfaces */ 1144 1145 enum { 1146 TRANSFER_FUNC_POINTS = 1025 1147 }; 1148 1149 struct dc_hdr_static_metadata { 1150 /* display chromaticities and white point in units of 0.00001 */ 1151 unsigned int chromaticity_green_x; 1152 unsigned int chromaticity_green_y; 1153 unsigned int chromaticity_blue_x; 1154 unsigned int chromaticity_blue_y; 1155 unsigned int chromaticity_red_x; 1156 unsigned int chromaticity_red_y; 1157 unsigned int chromaticity_white_point_x; 1158 unsigned int chromaticity_white_point_y; 1159 1160 uint32_t min_luminance; 1161 uint32_t max_luminance; 1162 uint32_t maximum_content_light_level; 1163 uint32_t maximum_frame_average_light_level; 1164 }; 1165 1166 enum dc_transfer_func_type { 1167 TF_TYPE_PREDEFINED, 1168 TF_TYPE_DISTRIBUTED_POINTS, 1169 TF_TYPE_BYPASS, 1170 TF_TYPE_HWPWL 1171 }; 1172 1173 struct dc_transfer_func_distributed_points { 1174 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1175 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1176 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1177 1178 uint16_t end_exponent; 1179 uint16_t x_point_at_y1_red; 1180 uint16_t x_point_at_y1_green; 1181 uint16_t x_point_at_y1_blue; 1182 }; 1183 1184 enum dc_transfer_func_predefined { 1185 TRANSFER_FUNCTION_SRGB, 1186 TRANSFER_FUNCTION_BT709, 1187 TRANSFER_FUNCTION_PQ, 1188 TRANSFER_FUNCTION_LINEAR, 1189 TRANSFER_FUNCTION_UNITY, 1190 TRANSFER_FUNCTION_HLG, 1191 TRANSFER_FUNCTION_HLG12, 1192 TRANSFER_FUNCTION_GAMMA22, 1193 TRANSFER_FUNCTION_GAMMA24, 1194 TRANSFER_FUNCTION_GAMMA26 1195 }; 1196 1197 1198 struct dc_transfer_func { 1199 struct kref refcount; 1200 enum dc_transfer_func_type type; 1201 enum dc_transfer_func_predefined tf; 1202 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1203 uint32_t sdr_ref_white_level; 1204 union { 1205 struct pwl_params pwl; 1206 struct dc_transfer_func_distributed_points tf_pts; 1207 }; 1208 }; 1209 1210 1211 union dc_3dlut_state { 1212 struct { 1213 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1214 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1215 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1216 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1217 uint32_t mpc_rmu1_mux:4; 1218 uint32_t mpc_rmu2_mux:4; 1219 uint32_t reserved:15; 1220 } bits; 1221 uint32_t raw; 1222 }; 1223 1224 1225 struct dc_3dlut { 1226 struct kref refcount; 1227 struct tetrahedral_params lut_3d; 1228 struct fixed31_32 hdr_multiplier; 1229 union dc_3dlut_state state; 1230 }; 1231 /* 1232 * This structure is filled in by dc_surface_get_status and contains 1233 * the last requested address and the currently active address so the called 1234 * can determine if there are any outstanding flips 1235 */ 1236 struct dc_plane_status { 1237 struct dc_plane_address requested_address; 1238 struct dc_plane_address current_address; 1239 bool is_flip_pending; 1240 bool is_right_eye; 1241 }; 1242 1243 union surface_update_flags { 1244 1245 struct { 1246 uint32_t addr_update:1; 1247 /* Medium updates */ 1248 uint32_t dcc_change:1; 1249 uint32_t color_space_change:1; 1250 uint32_t horizontal_mirror_change:1; 1251 uint32_t per_pixel_alpha_change:1; 1252 uint32_t global_alpha_change:1; 1253 uint32_t hdr_mult:1; 1254 uint32_t rotation_change:1; 1255 uint32_t swizzle_change:1; 1256 uint32_t scaling_change:1; 1257 uint32_t clip_size_change: 1; 1258 uint32_t position_change:1; 1259 uint32_t in_transfer_func_change:1; 1260 uint32_t input_csc_change:1; 1261 uint32_t coeff_reduction_change:1; 1262 uint32_t output_tf_change:1; 1263 uint32_t pixel_format_change:1; 1264 uint32_t plane_size_change:1; 1265 uint32_t gamut_remap_change:1; 1266 1267 /* Full updates */ 1268 uint32_t new_plane:1; 1269 uint32_t bpp_change:1; 1270 uint32_t gamma_change:1; 1271 uint32_t bandwidth_change:1; 1272 uint32_t clock_change:1; 1273 uint32_t stereo_format_change:1; 1274 uint32_t lut_3d:1; 1275 uint32_t tmz_changed:1; 1276 uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */ 1277 uint32_t full_update:1; 1278 uint32_t sdr_white_level_nits:1; 1279 } bits; 1280 1281 uint32_t raw; 1282 }; 1283 1284 #define DC_REMOVE_PLANE_POINTERS 1 1285 1286 struct dc_plane_state { 1287 struct dc_plane_address address; 1288 struct dc_plane_flip_time time; 1289 bool triplebuffer_flips; 1290 struct scaling_taps scaling_quality; 1291 struct rect src_rect; 1292 struct rect dst_rect; 1293 struct rect clip_rect; 1294 1295 struct plane_size plane_size; 1296 union dc_tiling_info tiling_info; 1297 1298 struct dc_plane_dcc_param dcc; 1299 1300 struct dc_gamma gamma_correction; 1301 struct dc_transfer_func in_transfer_func; 1302 struct dc_bias_and_scale bias_and_scale; 1303 struct dc_csc_transform input_csc_color_matrix; 1304 struct fixed31_32 coeff_reduction_factor; 1305 struct fixed31_32 hdr_mult; 1306 struct colorspace_transform gamut_remap_matrix; 1307 1308 // TODO: No longer used, remove 1309 struct dc_hdr_static_metadata hdr_static_ctx; 1310 1311 enum dc_color_space color_space; 1312 1313 struct dc_3dlut lut3d_func; 1314 struct dc_transfer_func in_shaper_func; 1315 struct dc_transfer_func blend_tf; 1316 1317 struct dc_transfer_func *gamcor_tf; 1318 enum surface_pixel_format format; 1319 enum dc_rotation_angle rotation; 1320 enum plane_stereo_format stereo_format; 1321 1322 bool is_tiling_rotated; 1323 bool per_pixel_alpha; 1324 bool pre_multiplied_alpha; 1325 bool global_alpha; 1326 int global_alpha_value; 1327 bool visible; 1328 bool flip_immediate; 1329 bool horizontal_mirror; 1330 int layer_index; 1331 1332 union surface_update_flags update_flags; 1333 bool flip_int_enabled; 1334 bool skip_manual_trigger; 1335 1336 /* private to DC core */ 1337 struct dc_plane_status status; 1338 struct dc_context *ctx; 1339 1340 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1341 bool force_full_update; 1342 1343 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1344 1345 /* private to dc_surface.c */ 1346 enum dc_irq_source irq_source; 1347 struct kref refcount; 1348 struct tg_color visual_confirm_color; 1349 1350 bool is_statically_allocated; 1351 enum chroma_cositing cositing; 1352 enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting; 1353 bool mcm_lut1d_enable; 1354 struct dc_cm2_func_luts mcm_luts; 1355 bool lut_bank_a; 1356 enum mpcc_movable_cm_location mcm_location; 1357 struct dc_csc_transform cursor_csc_color_matrix; 1358 bool adaptive_sharpness_en; 1359 int sharpness_level; 1360 enum linear_light_scaling linear_light_scaling; 1361 unsigned int sdr_white_level_nits; 1362 }; 1363 1364 struct dc_plane_info { 1365 struct plane_size plane_size; 1366 union dc_tiling_info tiling_info; 1367 struct dc_plane_dcc_param dcc; 1368 enum surface_pixel_format format; 1369 enum dc_rotation_angle rotation; 1370 enum plane_stereo_format stereo_format; 1371 enum dc_color_space color_space; 1372 bool horizontal_mirror; 1373 bool visible; 1374 bool per_pixel_alpha; 1375 bool pre_multiplied_alpha; 1376 bool global_alpha; 1377 int global_alpha_value; 1378 bool input_csc_enabled; 1379 int layer_index; 1380 enum chroma_cositing cositing; 1381 }; 1382 1383 #include "dc_stream.h" 1384 1385 struct dc_scratch_space { 1386 /* used to temporarily backup plane states of a stream during 1387 * dc update. The reason is that plane states are overwritten 1388 * with surface updates in dc update. Once they are overwritten 1389 * current state is no longer valid. We want to temporarily 1390 * store current value in plane states so we can still recover 1391 * a valid current state during dc update. 1392 */ 1393 struct dc_plane_state plane_states[MAX_SURFACES]; 1394 1395 struct dc_stream_state stream_state; 1396 }; 1397 1398 struct dc { 1399 struct dc_debug_options debug; 1400 struct dc_versions versions; 1401 struct dc_caps caps; 1402 struct dc_cap_funcs cap_funcs; 1403 struct dc_config config; 1404 struct dc_bounding_box_overrides bb_overrides; 1405 struct dc_bug_wa work_arounds; 1406 struct dc_context *ctx; 1407 struct dc_phy_addr_space_config vm_pa_config; 1408 1409 uint8_t link_count; 1410 struct dc_link *links[MAX_LINKS]; 1411 struct link_service *link_srv; 1412 1413 struct dc_state *current_state; 1414 struct resource_pool *res_pool; 1415 1416 struct clk_mgr *clk_mgr; 1417 1418 /* Display Engine Clock levels */ 1419 struct dm_pp_clock_levels sclk_lvls; 1420 1421 /* Inputs into BW and WM calculations. */ 1422 struct bw_calcs_dceip *bw_dceip; 1423 struct bw_calcs_vbios *bw_vbios; 1424 struct dcn_soc_bounding_box *dcn_soc; 1425 struct dcn_ip_params *dcn_ip; 1426 struct display_mode_lib dml; 1427 1428 /* HW functions */ 1429 struct hw_sequencer_funcs hwss; 1430 struct dce_hwseq *hwseq; 1431 1432 /* Require to optimize clocks and bandwidth for added/removed planes */ 1433 bool optimized_required; 1434 bool wm_optimized_required; 1435 bool idle_optimizations_allowed; 1436 bool enable_c20_dtm_b0; 1437 1438 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 1439 1440 /* FBC compressor */ 1441 struct compressor *fbc_compressor; 1442 1443 struct dc_debug_data debug_data; 1444 struct dpcd_vendor_signature vendor_signature; 1445 1446 const char *build_id; 1447 struct vm_helper *vm_helper; 1448 1449 uint32_t *dcn_reg_offsets; 1450 uint32_t *nbio_reg_offsets; 1451 uint32_t *clk_reg_offsets; 1452 1453 /* Scratch memory */ 1454 struct { 1455 struct { 1456 /* 1457 * For matching clock_limits table in driver with table 1458 * from PMFW. 1459 */ 1460 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1461 } update_bw_bounding_box; 1462 struct dc_scratch_space current_state; 1463 struct dc_scratch_space new_state; 1464 struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack 1465 } scratch; 1466 1467 struct dml2_configuration_options dml2_options; 1468 struct dml2_configuration_options dml2_tmp; 1469 enum dc_acpi_cm_power_state power_state; 1470 1471 }; 1472 1473 struct dc_scaling_info { 1474 struct rect src_rect; 1475 struct rect dst_rect; 1476 struct rect clip_rect; 1477 struct scaling_taps scaling_quality; 1478 }; 1479 1480 struct dc_fast_update { 1481 const struct dc_flip_addrs *flip_addr; 1482 const struct dc_gamma *gamma; 1483 const struct colorspace_transform *gamut_remap_matrix; 1484 const struct dc_csc_transform *input_csc_color_matrix; 1485 const struct fixed31_32 *coeff_reduction_factor; 1486 struct dc_transfer_func *out_transfer_func; 1487 struct dc_csc_transform *output_csc_transform; 1488 const struct dc_csc_transform *cursor_csc_color_matrix; 1489 }; 1490 1491 struct dc_surface_update { 1492 struct dc_plane_state *surface; 1493 1494 /* isr safe update parameters. null means no updates */ 1495 const struct dc_flip_addrs *flip_addr; 1496 const struct dc_plane_info *plane_info; 1497 const struct dc_scaling_info *scaling_info; 1498 struct fixed31_32 hdr_mult; 1499 /* following updates require alloc/sleep/spin that is not isr safe, 1500 * null means no updates 1501 */ 1502 const struct dc_gamma *gamma; 1503 const struct dc_transfer_func *in_transfer_func; 1504 1505 const struct dc_csc_transform *input_csc_color_matrix; 1506 const struct fixed31_32 *coeff_reduction_factor; 1507 const struct dc_transfer_func *func_shaper; 1508 const struct dc_3dlut *lut3d_func; 1509 const struct dc_transfer_func *blend_tf; 1510 const struct colorspace_transform *gamut_remap_matrix; 1511 /* 1512 * Color Transformations for pre-blend MCM (Shaper, 3DLUT, 1DLUT) 1513 * 1514 * change cm2_params.component_settings: Full update 1515 * change cm2_params.cm2_luts: Fast update 1516 */ 1517 struct dc_cm2_parameters *cm2_params; 1518 const struct dc_csc_transform *cursor_csc_color_matrix; 1519 unsigned int sdr_white_level_nits; 1520 }; 1521 1522 /* 1523 * Create a new surface with default parameters; 1524 */ 1525 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1526 void dc_gamma_release(struct dc_gamma **dc_gamma); 1527 struct dc_gamma *dc_create_gamma(void); 1528 1529 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1530 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1531 struct dc_transfer_func *dc_create_transfer_func(void); 1532 1533 struct dc_3dlut *dc_create_3dlut_func(void); 1534 void dc_3dlut_func_release(struct dc_3dlut *lut); 1535 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1536 1537 void dc_post_update_surfaces_to_stream( 1538 struct dc *dc); 1539 1540 #include "dc_stream.h" 1541 1542 /** 1543 * struct dc_validation_set - Struct to store surface/stream associations for validation 1544 */ 1545 struct dc_validation_set { 1546 /** 1547 * @stream: Stream state properties 1548 */ 1549 struct dc_stream_state *stream; 1550 1551 /** 1552 * @plane_states: Surface state 1553 */ 1554 struct dc_plane_state *plane_states[MAX_SURFACES]; 1555 1556 /** 1557 * @plane_count: Total of active planes 1558 */ 1559 uint8_t plane_count; 1560 }; 1561 1562 bool dc_validate_boot_timing(const struct dc *dc, 1563 const struct dc_sink *sink, 1564 struct dc_crtc_timing *crtc_timing); 1565 1566 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1567 1568 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1569 1570 enum dc_status dc_validate_with_context(struct dc *dc, 1571 const struct dc_validation_set set[], 1572 int set_count, 1573 struct dc_state *context, 1574 bool fast_validate); 1575 1576 bool dc_set_generic_gpio_for_stereo(bool enable, 1577 struct gpio_service *gpio_service); 1578 1579 /* 1580 * fast_validate: we return after determining if we can support the new state, 1581 * but before we populate the programming info 1582 */ 1583 enum dc_status dc_validate_global_state( 1584 struct dc *dc, 1585 struct dc_state *new_ctx, 1586 bool fast_validate); 1587 1588 bool dc_acquire_release_mpc_3dlut( 1589 struct dc *dc, bool acquire, 1590 struct dc_stream_state *stream, 1591 struct dc_3dlut **lut, 1592 struct dc_transfer_func **shaper); 1593 1594 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1595 void get_audio_check(struct audio_info *aud_modes, 1596 struct audio_check *aud_chk); 1597 1598 bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count); 1599 void populate_fast_updates(struct dc_fast_update *fast_update, 1600 struct dc_surface_update *srf_updates, 1601 int surface_count, 1602 struct dc_stream_update *stream_update); 1603 /* 1604 * Set up streams and links associated to drive sinks 1605 * The streams parameter is an absolute set of all active streams. 1606 * 1607 * After this call: 1608 * Phy, Encoder, Timing Generator are programmed and enabled. 1609 * New streams are enabled with blank stream; no memory read. 1610 */ 1611 enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params); 1612 1613 1614 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 1615 struct dc_stream_state *stream, 1616 int mpcc_inst); 1617 1618 1619 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1620 1621 void dc_set_disable_128b_132b_stream_overhead(bool disable); 1622 1623 /* The function returns minimum bandwidth required to drive a given timing 1624 * return - minimum required timing bandwidth in kbps. 1625 */ 1626 uint32_t dc_bandwidth_in_kbps_from_timing( 1627 const struct dc_crtc_timing *timing, 1628 const enum dc_link_encoding_format link_encoding); 1629 1630 /* Link Interfaces */ 1631 /* 1632 * A link contains one or more sinks and their connected status. 1633 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1634 */ 1635 struct dc_link { 1636 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1637 unsigned int sink_count; 1638 struct dc_sink *local_sink; 1639 unsigned int link_index; 1640 enum dc_connection_type type; 1641 enum signal_type connector_signal; 1642 enum dc_irq_source irq_source_hpd; 1643 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1644 1645 bool is_hpd_filter_disabled; 1646 bool dp_ss_off; 1647 1648 /** 1649 * @link_state_valid: 1650 * 1651 * If there is no link and local sink, this variable should be set to 1652 * false. Otherwise, it should be set to true; usually, the function 1653 * core_link_enable_stream sets this field to true. 1654 */ 1655 bool link_state_valid; 1656 bool aux_access_disabled; 1657 bool sync_lt_in_progress; 1658 bool skip_stream_reenable; 1659 bool is_internal_display; 1660 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1661 bool is_dig_mapping_flexible; 1662 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1663 bool is_hpd_pending; /* Indicates a new received hpd */ 1664 1665 /* USB4 DPIA links skip verifying link cap, instead performing the fallback method 1666 * for every link training. This is incompatible with DP LL compliance automation, 1667 * which expects the same link settings to be used every retry on a link loss. 1668 * This flag is used to skip the fallback when link loss occurs during automation. 1669 */ 1670 bool skip_fallback_on_link_loss; 1671 1672 bool edp_sink_present; 1673 1674 struct dp_trace dp_trace; 1675 1676 /* caps is the same as reported_link_cap. link_traing use 1677 * reported_link_cap. Will clean up. TODO 1678 */ 1679 struct dc_link_settings reported_link_cap; 1680 struct dc_link_settings verified_link_cap; 1681 struct dc_link_settings cur_link_settings; 1682 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1683 struct dc_link_settings preferred_link_setting; 1684 /* preferred_training_settings are override values that 1685 * come from DM. DM is responsible for the memory 1686 * management of the override pointers. 1687 */ 1688 struct dc_link_training_overrides preferred_training_settings; 1689 struct dp_audio_test_data audio_test_data; 1690 1691 uint8_t ddc_hw_inst; 1692 1693 uint8_t hpd_src; 1694 1695 uint8_t link_enc_hw_inst; 1696 /* DIG link encoder ID. Used as index in link encoder resource pool. 1697 * For links with fixed mapping to DIG, this is not changed after dc_link 1698 * object creation. 1699 */ 1700 enum engine_id eng_id; 1701 enum engine_id dpia_preferred_eng_id; 1702 1703 bool test_pattern_enabled; 1704 /* Pending/Current test pattern are only used to perform and track 1705 * FIXED_VS retimer test pattern/lane adjustment override state. 1706 * Pending allows link HWSS to differentiate PHY vs non-PHY pattern, 1707 * to perform specific lane adjust overrides before setting certain 1708 * PHY test patterns. In cases when lane adjust and set test pattern 1709 * calls are not performed atomically (i.e. performing link training), 1710 * pending_test_pattern will be invalid or contain a non-PHY test pattern 1711 * and current_test_pattern will contain required context for any future 1712 * set pattern/set lane adjust to transition between override state(s). 1713 * */ 1714 enum dp_test_pattern current_test_pattern; 1715 enum dp_test_pattern pending_test_pattern; 1716 1717 union compliance_test_state compliance_test_state; 1718 1719 void *priv; 1720 1721 struct ddc_service *ddc; 1722 1723 enum dp_panel_mode panel_mode; 1724 bool aux_mode; 1725 1726 /* Private to DC core */ 1727 1728 const struct dc *dc; 1729 1730 struct dc_context *ctx; 1731 1732 struct panel_cntl *panel_cntl; 1733 struct link_encoder *link_enc; 1734 struct graphics_object_id link_id; 1735 /* Endpoint type distinguishes display endpoints which do not have entries 1736 * in the BIOS connector table from those that do. Helps when tracking link 1737 * encoder to display endpoint assignments. 1738 */ 1739 enum display_endpoint_type ep_type; 1740 union ddi_channel_mapping ddi_channel_mapping; 1741 struct connector_device_tag_info device_tag; 1742 struct dpcd_caps dpcd_caps; 1743 uint32_t dongle_max_pix_clk; 1744 unsigned short chip_caps; 1745 unsigned int dpcd_sink_count; 1746 struct hdcp_caps hdcp_caps; 1747 enum edp_revision edp_revision; 1748 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1749 1750 struct psr_settings psr_settings; 1751 struct replay_settings replay_settings; 1752 1753 /* Drive settings read from integrated info table */ 1754 struct dc_lane_settings bios_forced_drive_settings; 1755 1756 /* Vendor specific LTTPR workaround variables */ 1757 uint8_t vendor_specific_lttpr_link_rate_wa; 1758 bool apply_vendor_specific_lttpr_link_rate_wa; 1759 1760 /* MST record stream using this link */ 1761 struct link_flags { 1762 bool dp_keep_receiver_powered; 1763 bool dp_skip_DID2; 1764 bool dp_skip_reset_segment; 1765 bool dp_skip_fs_144hz; 1766 bool dp_mot_reset_segment; 1767 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1768 bool dpia_mst_dsc_always_on; 1769 /* Forced DPIA into TBT3 compatibility mode. */ 1770 bool dpia_forced_tbt3_mode; 1771 bool dongle_mode_timing_override; 1772 bool blank_stream_on_ocs_change; 1773 bool read_dpcd204h_on_irq_hpd; 1774 bool disable_assr_for_uhbr; 1775 } wa_flags; 1776 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1777 1778 struct dc_link_status link_status; 1779 struct dprx_states dprx_states; 1780 1781 struct gpio *hpd_gpio; 1782 enum dc_link_fec_state fec_state; 1783 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1784 1785 struct dc_panel_config panel_config; 1786 struct phy_state phy_state; 1787 // BW ALLOCATON USB4 ONLY 1788 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 1789 bool skip_implict_edp_power_control; 1790 }; 1791 1792 /* Return an enumerated dc_link. 1793 * dc_link order is constant and determined at 1794 * boot time. They cannot be created or destroyed. 1795 * Use dc_get_caps() to get number of links. 1796 */ 1797 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 1798 1799 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 1800 bool dc_get_edp_link_panel_inst(const struct dc *dc, 1801 const struct dc_link *link, 1802 unsigned int *inst_out); 1803 1804 /* Return an array of link pointers to edp links. */ 1805 void dc_get_edp_links(const struct dc *dc, 1806 struct dc_link **edp_links, 1807 int *edp_num); 1808 1809 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link, 1810 bool powerOn); 1811 1812 /* The function initiates detection handshake over the given link. It first 1813 * determines if there are display connections over the link. If so it initiates 1814 * detection protocols supported by the connected receiver device. The function 1815 * contains protocol specific handshake sequences which are sometimes mandatory 1816 * to establish a proper connection between TX and RX. So it is always 1817 * recommended to call this function as the first link operation upon HPD event 1818 * or power up event. Upon completion, the function will update link structure 1819 * in place based on latest RX capabilities. The function may also cause dpms 1820 * to be reset to off for all currently enabled streams to the link. It is DM's 1821 * responsibility to serialize detection and DPMS updates. 1822 * 1823 * @reason - Indicate which event triggers this detection. dc may customize 1824 * detection flow depending on the triggering events. 1825 * return false - if detection is not fully completed. This could happen when 1826 * there is an unrecoverable error during detection or detection is partially 1827 * completed (detection has been delegated to dm mst manager ie. 1828 * link->connection_type == dc_connection_mst_branch when returning false). 1829 * return true - detection is completed, link has been fully updated with latest 1830 * detection result. 1831 */ 1832 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 1833 1834 struct dc_sink_init_data; 1835 1836 /* When link connection type is dc_connection_mst_branch, remote sink can be 1837 * added to the link. The interface creates a remote sink and associates it with 1838 * current link. The sink will be retained by link until remove remote sink is 1839 * called. 1840 * 1841 * @dc_link - link the remote sink will be added to. 1842 * @edid - byte array of EDID raw data. 1843 * @len - size of the edid in byte 1844 * @init_data - 1845 */ 1846 struct dc_sink *dc_link_add_remote_sink( 1847 struct dc_link *dc_link, 1848 const uint8_t *edid, 1849 int len, 1850 struct dc_sink_init_data *init_data); 1851 1852 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 1853 * @link - link the sink should be removed from 1854 * @sink - sink to be removed. 1855 */ 1856 void dc_link_remove_remote_sink( 1857 struct dc_link *link, 1858 struct dc_sink *sink); 1859 1860 /* Enable HPD interrupt handler for a given link */ 1861 void dc_link_enable_hpd(const struct dc_link *link); 1862 1863 /* Disable HPD interrupt handler for a given link */ 1864 void dc_link_disable_hpd(const struct dc_link *link); 1865 1866 /* determine if there is a sink connected to the link 1867 * 1868 * @type - dc_connection_single if connected, dc_connection_none otherwise. 1869 * return - false if an unexpected error occurs, true otherwise. 1870 * 1871 * NOTE: This function doesn't detect downstream sink connections i.e 1872 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 1873 * return dc_connection_single if the branch device is connected despite of 1874 * downstream sink's connection status. 1875 */ 1876 bool dc_link_detect_connection_type(struct dc_link *link, 1877 enum dc_connection_type *type); 1878 1879 /* query current hpd pin value 1880 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 1881 * 1882 */ 1883 bool dc_link_get_hpd_state(struct dc_link *link); 1884 1885 /* Getter for cached link status from given link */ 1886 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 1887 1888 /* enable/disable hardware HPD filter. 1889 * 1890 * @link - The link the HPD pin is associated with. 1891 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 1892 * handler once after no HPD change has been detected within dc default HPD 1893 * filtering interval since last HPD event. i.e if display keeps toggling hpd 1894 * pulses within default HPD interval, no HPD event will be received until HPD 1895 * toggles have stopped. Then HPD event will be queued to irq handler once after 1896 * dc default HPD filtering interval since last HPD event. 1897 * 1898 * @enable = false - disable hardware HPD filter. HPD event will be queued 1899 * immediately to irq handler after no HPD change has been detected within 1900 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 1901 */ 1902 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 1903 1904 /* submit i2c read/write payloads through ddc channel 1905 * @link_index - index to a link with ddc in i2c mode 1906 * @cmd - i2c command structure 1907 * return - true if success, false otherwise. 1908 */ 1909 bool dc_submit_i2c( 1910 struct dc *dc, 1911 uint32_t link_index, 1912 struct i2c_command *cmd); 1913 1914 /* submit i2c read/write payloads through oem channel 1915 * @link_index - index to a link with ddc in i2c mode 1916 * @cmd - i2c command structure 1917 * return - true if success, false otherwise. 1918 */ 1919 bool dc_submit_i2c_oem( 1920 struct dc *dc, 1921 struct i2c_command *cmd); 1922 1923 enum aux_return_code_type; 1924 /* Attempt to transfer the given aux payload. This function does not perform 1925 * retries or handle error states. The reply is returned in the payload->reply 1926 * and the result through operation_result. Returns the number of bytes 1927 * transferred,or -1 on a failure. 1928 */ 1929 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 1930 struct aux_payload *payload, 1931 enum aux_return_code_type *operation_result); 1932 1933 bool dc_is_oem_i2c_device_present( 1934 struct dc *dc, 1935 size_t slave_address 1936 ); 1937 1938 /* return true if the connected receiver supports the hdcp version */ 1939 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 1940 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 1941 1942 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 1943 * 1944 * TODO - When defer_handling is true the function will have a different purpose. 1945 * It no longer does complete hpd rx irq handling. We should create a separate 1946 * interface specifically for this case. 1947 * 1948 * Return: 1949 * true - Downstream port status changed. DM should call DC to do the 1950 * detection. 1951 * false - no change in Downstream port status. No further action required 1952 * from DM. 1953 */ 1954 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 1955 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 1956 bool defer_handling, bool *has_left_work); 1957 /* handle DP specs define test automation sequence*/ 1958 void dc_link_dp_handle_automated_test(struct dc_link *link); 1959 1960 /* handle DP Link loss sequence and try to recover RX link loss with best 1961 * effort 1962 */ 1963 void dc_link_dp_handle_link_loss(struct dc_link *link); 1964 1965 /* Determine if hpd rx irq should be handled or ignored 1966 * return true - hpd rx irq should be handled. 1967 * return false - it is safe to ignore hpd rx irq event 1968 */ 1969 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 1970 1971 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 1972 * @link - link the hpd irq data associated with 1973 * @hpd_irq_dpcd_data - input hpd irq data 1974 * return - true if hpd irq data indicates a link lost 1975 */ 1976 bool dc_link_check_link_loss_status(struct dc_link *link, 1977 union hpd_irq_data *hpd_irq_dpcd_data); 1978 1979 /* Read hpd rx irq data from a given link 1980 * @link - link where the hpd irq data should be read from 1981 * @irq_data - output hpd irq data 1982 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 1983 * read has failed. 1984 */ 1985 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 1986 struct dc_link *link, 1987 union hpd_irq_data *irq_data); 1988 1989 /* The function clears recorded DP RX states in the link. DM should call this 1990 * function when it is resuming from S3 power state to previously connected links. 1991 * 1992 * TODO - in the future we should consider to expand link resume interface to 1993 * support clearing previous rx states. So we don't have to rely on dm to call 1994 * this interface explicitly. 1995 */ 1996 void dc_link_clear_dprx_states(struct dc_link *link); 1997 1998 /* Destruct the mst topology of the link and reset the allocated payload table 1999 * 2000 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 2001 * still wants to reset MST topology on an unplug event */ 2002 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 2003 2004 /* The function calculates effective DP link bandwidth when a given link is 2005 * using the given link settings. 2006 * 2007 * return - total effective link bandwidth in kbps. 2008 */ 2009 uint32_t dc_link_bandwidth_kbps( 2010 const struct dc_link *link, 2011 const struct dc_link_settings *link_setting); 2012 2013 /* The function takes a snapshot of current link resource allocation state 2014 * @dc: pointer to dc of the dm calling this 2015 * @map: a dc link resource snapshot defined internally to dc. 2016 * 2017 * DM needs to capture a snapshot of current link resource allocation mapping 2018 * and store it in its persistent storage. 2019 * 2020 * Some of the link resource is using first come first serve policy. 2021 * The allocation mapping depends on original hotplug order. This information 2022 * is lost after driver is loaded next time. The snapshot is used in order to 2023 * restore link resource to its previous state so user will get consistent 2024 * link capability allocation across reboot. 2025 * 2026 */ 2027 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 2028 2029 /* This function restores link resource allocation state from a snapshot 2030 * @dc: pointer to dc of the dm calling this 2031 * @map: a dc link resource snapshot defined internally to dc. 2032 * 2033 * DM needs to call this function after initial link detection on boot and 2034 * before first commit streams to restore link resource allocation state 2035 * from previous boot session. 2036 * 2037 * Some of the link resource is using first come first serve policy. 2038 * The allocation mapping depends on original hotplug order. This information 2039 * is lost after driver is loaded next time. The snapshot is used in order to 2040 * restore link resource to its previous state so user will get consistent 2041 * link capability allocation across reboot. 2042 * 2043 */ 2044 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 2045 2046 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 2047 * interface i.e stream_update->dsc_config 2048 */ 2049 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 2050 2051 /* translate a raw link rate data to bandwidth in kbps */ 2052 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); 2053 2054 /* determine the optimal bandwidth given link and required bw. 2055 * @link - current detected link 2056 * @req_bw - requested bandwidth in kbps 2057 * @link_settings - returned most optimal link settings that can fit the 2058 * requested bandwidth 2059 * return - false if link can't support requested bandwidth, true if link 2060 * settings is found. 2061 */ 2062 bool dc_link_decide_edp_link_settings(struct dc_link *link, 2063 struct dc_link_settings *link_settings, 2064 uint32_t req_bw); 2065 2066 /* return the max dp link settings can be driven by the link without considering 2067 * connected RX device and its capability 2068 */ 2069 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 2070 struct dc_link_settings *max_link_enc_cap); 2071 2072 /* determine when the link is driving MST mode, what DP link channel coding 2073 * format will be used. The decision will remain unchanged until next HPD event. 2074 * 2075 * @link - a link with DP RX connection 2076 * return - if stream is committed to this link with MST signal type, type of 2077 * channel coding format dc will choose. 2078 */ 2079 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 2080 const struct dc_link *link); 2081 2082 /* get max dp link settings the link can enable with all things considered. (i.e 2083 * TX/RX/Cable capabilities and dp override policies. 2084 * 2085 * @link - a link with DP RX connection 2086 * return - max dp link settings the link can enable. 2087 * 2088 */ 2089 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 2090 2091 /* Get the highest encoding format that the link supports; highest meaning the 2092 * encoding format which supports the maximum bandwidth. 2093 * 2094 * @link - a link with DP RX connection 2095 * return - highest encoding format link supports. 2096 */ 2097 enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link); 2098 2099 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 2100 * to a link with dp connector signal type. 2101 * @link - a link with dp connector signal type 2102 * return - true if connected, false otherwise 2103 */ 2104 bool dc_link_is_dp_sink_present(struct dc_link *link); 2105 2106 /* Force DP lane settings update to main-link video signal and notify the change 2107 * to DP RX via DPCD. This is a debug interface used for video signal integrity 2108 * tuning purpose. The interface assumes link has already been enabled with DP 2109 * signal. 2110 * 2111 * @lt_settings - a container structure with desired hw_lane_settings 2112 */ 2113 void dc_link_set_drive_settings(struct dc *dc, 2114 struct link_training_settings *lt_settings, 2115 struct dc_link *link); 2116 2117 /* Enable a test pattern in Link or PHY layer in an active link for compliance 2118 * test or debugging purpose. The test pattern will remain until next un-plug. 2119 * 2120 * @link - active link with DP signal output enabled. 2121 * @test_pattern - desired test pattern to output. 2122 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 2123 * @test_pattern_color_space - for video test pattern choose a desired color 2124 * space. 2125 * @p_link_settings - For PHY pattern choose a desired link settings 2126 * @p_custom_pattern - some test pattern will require a custom input to 2127 * customize some pattern details. Otherwise keep it to NULL. 2128 * @cust_pattern_size - size of the custom pattern input. 2129 * 2130 */ 2131 bool dc_link_dp_set_test_pattern( 2132 struct dc_link *link, 2133 enum dp_test_pattern test_pattern, 2134 enum dp_test_pattern_color_space test_pattern_color_space, 2135 const struct link_training_settings *p_link_settings, 2136 const unsigned char *p_custom_pattern, 2137 unsigned int cust_pattern_size); 2138 2139 /* Force DP link settings to always use a specific value until reboot to a 2140 * specific link. If link has already been enabled, the interface will also 2141 * switch to desired link settings immediately. This is a debug interface to 2142 * generic dp issue trouble shooting. 2143 */ 2144 void dc_link_set_preferred_link_settings(struct dc *dc, 2145 struct dc_link_settings *link_setting, 2146 struct dc_link *link); 2147 2148 /* Force DP link to customize a specific link training behavior by overriding to 2149 * standard DP specs defined protocol. This is a debug interface to trouble shoot 2150 * display specific link training issues or apply some display specific 2151 * workaround in link training. 2152 * 2153 * @link_settings - if not NULL, force preferred link settings to the link. 2154 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 2155 * will apply this particular override in future link training. If NULL is 2156 * passed in, dc resets previous overrides. 2157 * NOTE: DM must keep the memory from override pointers until DM resets preferred 2158 * training settings. 2159 */ 2160 void dc_link_set_preferred_training_settings(struct dc *dc, 2161 struct dc_link_settings *link_setting, 2162 struct dc_link_training_overrides *lt_overrides, 2163 struct dc_link *link, 2164 bool skip_immediate_retrain); 2165 2166 /* return - true if FEC is supported with connected DP RX, false otherwise */ 2167 bool dc_link_is_fec_supported(const struct dc_link *link); 2168 2169 /* query FEC enablement policy to determine if FEC will be enabled by dc during 2170 * link enablement. 2171 * return - true if FEC should be enabled, false otherwise. 2172 */ 2173 bool dc_link_should_enable_fec(const struct dc_link *link); 2174 2175 /* determine lttpr mode the current link should be enabled with a specific link 2176 * settings. 2177 */ 2178 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 2179 struct dc_link_settings *link_setting); 2180 2181 /* Force DP RX to update its power state. 2182 * NOTE: this interface doesn't update dp main-link. Calling this function will 2183 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 2184 * RX power state back upon finish DM specific execution requiring DP RX in a 2185 * specific power state. 2186 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 2187 * state. 2188 */ 2189 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 2190 2191 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 2192 * current value read from extended receiver cap from 02200h - 0220Fh. 2193 * Some DP RX has problems of providing accurate DP receiver caps from extended 2194 * field, this interface is a workaround to revert link back to use base caps. 2195 */ 2196 void dc_link_overwrite_extended_receiver_cap( 2197 struct dc_link *link); 2198 2199 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 2200 bool wait_for_hpd); 2201 2202 /* Set backlight level of an embedded panel (eDP, LVDS). 2203 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 2204 * and 16 bit fractional, where 1.0 is max backlight value. 2205 */ 2206 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 2207 uint32_t backlight_pwm_u16_16, 2208 uint32_t frame_ramp); 2209 2210 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 2211 bool dc_link_set_backlight_level_nits(struct dc_link *link, 2212 bool isHDR, 2213 uint32_t backlight_millinits, 2214 uint32_t transition_time_in_ms); 2215 2216 bool dc_link_get_backlight_level_nits(struct dc_link *link, 2217 uint32_t *backlight_millinits, 2218 uint32_t *backlight_millinits_peak); 2219 2220 int dc_link_get_backlight_level(const struct dc_link *dc_link); 2221 2222 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 2223 2224 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 2225 bool wait, bool force_static, const unsigned int *power_opts); 2226 2227 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 2228 2229 bool dc_link_setup_psr(struct dc_link *dc_link, 2230 const struct dc_stream_state *stream, struct psr_config *psr_config, 2231 struct psr_context *psr_context); 2232 2233 /* 2234 * Communicate with DMUB to allow or disallow Panel Replay on the specified link: 2235 * 2236 * @link: pointer to the dc_link struct instance 2237 * @enable: enable(active) or disable(inactive) replay 2238 * @wait: state transition need to wait the active set completed. 2239 * @force_static: force disable(inactive) the replay 2240 * @power_opts: set power optimazation parameters to DMUB. 2241 * 2242 * return: allow Replay active will return true, else will return false. 2243 */ 2244 bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable, 2245 bool wait, bool force_static, const unsigned int *power_opts); 2246 2247 bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state); 2248 2249 /* On eDP links this function call will stall until T12 has elapsed. 2250 * If the panel is not in power off state, this function will return 2251 * immediately. 2252 */ 2253 bool dc_link_wait_for_t12(struct dc_link *link); 2254 2255 /* Determine if dp trace has been initialized to reflect upto date result * 2256 * return - true if trace is initialized and has valid data. False dp trace 2257 * doesn't have valid result. 2258 */ 2259 bool dc_dp_trace_is_initialized(struct dc_link *link); 2260 2261 /* Query a dp trace flag to indicate if the current dp trace data has been 2262 * logged before 2263 */ 2264 bool dc_dp_trace_is_logged(struct dc_link *link, 2265 bool in_detection); 2266 2267 /* Set dp trace flag to indicate whether DM has already logged the current dp 2268 * trace data. DM can set is_logged to true upon logging and check 2269 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 2270 */ 2271 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 2272 bool in_detection, 2273 bool is_logged); 2274 2275 /* Obtain driver time stamp for last dp link training end. The time stamp is 2276 * formatted based on dm_get_timestamp DM function. 2277 * @in_detection - true to get link training end time stamp of last link 2278 * training in detection sequence. false to get link training end time stamp 2279 * of last link training in commit (dpms) sequence 2280 */ 2281 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 2282 bool in_detection); 2283 2284 /* Get how many link training attempts dc has done with latest sequence. 2285 * @in_detection - true to get link training count of last link 2286 * training in detection sequence. false to get link training count of last link 2287 * training in commit (dpms) sequence 2288 */ 2289 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 2290 bool in_detection); 2291 2292 /* Get how many link loss has happened since last link training attempts */ 2293 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 2294 2295 /* 2296 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 2297 */ 2298 /* 2299 * Send a request from DP-Tx requesting to allocate BW remotely after 2300 * allocating it locally. This will get processed by CM and a CB function 2301 * will be called. 2302 * 2303 * @link: pointer to the dc_link struct instance 2304 * @req_bw: The requested bw in Kbyte to allocated 2305 * 2306 * return: none 2307 */ 2308 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 2309 2310 /* 2311 * Handle function for when the status of the Request above is complete. 2312 * We will find out the result of allocating on CM and update structs. 2313 * 2314 * @link: pointer to the dc_link struct instance 2315 * @bw: Allocated or Estimated BW depending on the result 2316 * @result: Response type 2317 * 2318 * return: none 2319 */ 2320 void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, 2321 uint8_t bw, uint8_t result); 2322 2323 /* 2324 * Handle the USB4 BW Allocation related functionality here: 2325 * Plug => Try to allocate max bw from timing parameters supported by the sink 2326 * Unplug => de-allocate bw 2327 * 2328 * @link: pointer to the dc_link struct instance 2329 * @peak_bw: Peak bw used by the link/sink 2330 * 2331 * return: allocated bw else return 0 2332 */ 2333 int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 2334 struct dc_link *link, int peak_bw); 2335 2336 /* 2337 * Validate the BW of all the valid DPIA links to make sure it doesn't exceed 2338 * available BW for each host router 2339 * 2340 * @dc: pointer to dc struct 2341 * @stream: pointer to all possible streams 2342 * @count: number of valid DPIA streams 2343 * 2344 * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE 2345 */ 2346 bool dc_link_dp_dpia_validate(struct dc *dc, const struct dc_stream_state *streams, 2347 const unsigned int count); 2348 2349 /* Sink Interfaces - A sink corresponds to a display output device */ 2350 2351 struct dc_container_id { 2352 // 128bit GUID in binary form 2353 unsigned char guid[16]; 2354 // 8 byte port ID -> ELD.PortID 2355 unsigned int portId[2]; 2356 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 2357 unsigned short manufacturerName; 2358 // 2 byte product code -> ELD.ProductCode 2359 unsigned short productCode; 2360 }; 2361 2362 2363 struct dc_sink_dsc_caps { 2364 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 2365 // 'false' if they are sink's DSC caps 2366 bool is_virtual_dpcd_dsc; 2367 // 'true' if MST topology supports DSC passthrough for sink 2368 // 'false' if MST topology does not support DSC passthrough 2369 bool is_dsc_passthrough_supported; 2370 struct dsc_dec_dpcd_caps dsc_dec_caps; 2371 }; 2372 2373 struct dc_sink_fec_caps { 2374 bool is_rx_fec_supported; 2375 bool is_topology_fec_supported; 2376 }; 2377 2378 struct scdc_caps { 2379 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 2380 union hdmi_scdc_device_id_data device_id; 2381 }; 2382 2383 /* 2384 * The sink structure contains EDID and other display device properties 2385 */ 2386 struct dc_sink { 2387 enum signal_type sink_signal; 2388 struct dc_edid dc_edid; /* raw edid */ 2389 struct dc_edid_caps edid_caps; /* parse display caps */ 2390 struct dc_container_id *dc_container_id; 2391 uint32_t dongle_max_pix_clk; 2392 void *priv; 2393 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 2394 bool converter_disable_audio; 2395 2396 struct scdc_caps scdc_caps; 2397 struct dc_sink_dsc_caps dsc_caps; 2398 struct dc_sink_fec_caps fec_caps; 2399 2400 bool is_vsc_sdp_colorimetry_supported; 2401 2402 /* private to DC core */ 2403 struct dc_link *link; 2404 struct dc_context *ctx; 2405 2406 uint32_t sink_id; 2407 2408 /* private to dc_sink.c */ 2409 // refcount must be the last member in dc_sink, since we want the 2410 // sink structure to be logically cloneable up to (but not including) 2411 // refcount 2412 struct kref refcount; 2413 }; 2414 2415 void dc_sink_retain(struct dc_sink *sink); 2416 void dc_sink_release(struct dc_sink *sink); 2417 2418 struct dc_sink_init_data { 2419 enum signal_type sink_signal; 2420 struct dc_link *link; 2421 uint32_t dongle_max_pix_clk; 2422 bool converter_disable_audio; 2423 }; 2424 2425 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 2426 2427 /* Newer interfaces */ 2428 struct dc_cursor { 2429 struct dc_plane_address address; 2430 struct dc_cursor_attributes attributes; 2431 }; 2432 2433 2434 /* Interrupt interfaces */ 2435 enum dc_irq_source dc_interrupt_to_irq_source( 2436 struct dc *dc, 2437 uint32_t src_id, 2438 uint32_t ext_id); 2439 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 2440 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 2441 enum dc_irq_source dc_get_hpd_irq_source_at_index( 2442 struct dc *dc, uint32_t link_index); 2443 2444 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 2445 2446 /* Power Interfaces */ 2447 2448 void dc_set_power_state( 2449 struct dc *dc, 2450 enum dc_acpi_cm_power_state power_state); 2451 void dc_resume(struct dc *dc); 2452 2453 void dc_power_down_on_boot(struct dc *dc); 2454 2455 /* 2456 * HDCP Interfaces 2457 */ 2458 enum hdcp_message_status dc_process_hdcp_msg( 2459 enum signal_type signal, 2460 struct dc_link *link, 2461 struct hdcp_protection_message *message_info); 2462 bool dc_is_dmcu_initialized(struct dc *dc); 2463 2464 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 2465 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 2466 2467 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, 2468 unsigned int pitch, 2469 unsigned int height, 2470 enum surface_pixel_format format, 2471 struct dc_cursor_attributes *cursor_attr); 2472 2473 #define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __func__) 2474 #define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__) 2475 2476 void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name); 2477 void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name); 2478 bool dc_dmub_is_ips_idle_state(struct dc *dc); 2479 2480 /* set min and max memory clock to lowest and highest DPM level, respectively */ 2481 void dc_unlock_memory_clock_frequency(struct dc *dc); 2482 2483 /* set min memory clock to the min required for current mode, max to maxDPM */ 2484 void dc_lock_memory_clock_frequency(struct dc *dc); 2485 2486 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 2487 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 2488 2489 /* cleanup on driver unload */ 2490 void dc_hardware_release(struct dc *dc); 2491 2492 /* disables fw based mclk switch */ 2493 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 2494 2495 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 2496 2497 bool dc_set_replay_allow_active(struct dc *dc, bool active); 2498 2499 bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips); 2500 2501 void dc_z10_restore(const struct dc *dc); 2502 void dc_z10_save_init(struct dc *dc); 2503 2504 bool dc_is_dmub_outbox_supported(struct dc *dc); 2505 bool dc_enable_dmub_notifications(struct dc *dc); 2506 2507 bool dc_abm_save_restore( 2508 struct dc *dc, 2509 struct dc_stream_state *stream, 2510 struct abm_save_restore *pData); 2511 2512 void dc_enable_dmub_outbox(struct dc *dc); 2513 2514 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 2515 uint32_t link_index, 2516 struct aux_payload *payload); 2517 2518 /* Get dc link index from dpia port index */ 2519 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 2520 uint8_t dpia_port_index); 2521 2522 bool dc_process_dmub_set_config_async(struct dc *dc, 2523 uint32_t link_index, 2524 struct set_config_cmd_payload *payload, 2525 struct dmub_notification *notify); 2526 2527 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 2528 uint32_t link_index, 2529 uint8_t mst_alloc_slots, 2530 uint8_t *mst_slots_in_use); 2531 2532 void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps); 2533 2534 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 2535 uint32_t hpd_int_enable); 2536 2537 void dc_print_dmub_diagnostic_data(const struct dc *dc); 2538 2539 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties); 2540 2541 struct dc_power_profile { 2542 int power_level; /* Lower is better */ 2543 }; 2544 2545 struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context); 2546 2547 unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context); 2548 2549 /* DSC Interfaces */ 2550 #include "dc_dsc.h" 2551 2552 /* Disable acc mode Interfaces */ 2553 void dc_disable_accelerated_mode(struct dc *dc); 2554 2555 bool dc_is_timing_changed(struct dc_stream_state *cur_stream, 2556 struct dc_stream_state *new_stream); 2557 2558 #endif /* DC_INTERFACE_H_ */ 2559