1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "dc_bios_types.h"
28 #include "dcn10_stream_encoder.h"
29 #include "reg_helper.h"
30 #include "hw_shared.h"
31 #include "link.h"
32 #include "dpcd_defs.h"
33 #include "dcn30/dcn30_afmt.h"
34
35 #define DC_LOGGER \
36 enc1->base.ctx->logger
37
38 #define REG(reg)\
39 (enc1->regs->reg)
40
41 #undef FN
42 #define FN(reg_name, field_name) \
43 enc1->se_shift->field_name, enc1->se_mask->field_name
44
45 #define VBI_LINE_0 0
46 #define DP_BLANK_MAX_RETRY 20
47 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
48
49
50 enum {
51 DP_MST_UPDATE_MAX_RETRY = 50
52 };
53
54 #define CTX \
55 enc1->base.ctx
56
enc1_update_generic_info_packet(struct dcn10_stream_encoder * enc1,uint32_t packet_index,const struct dc_info_packet * info_packet)57 void enc1_update_generic_info_packet(
58 struct dcn10_stream_encoder *enc1,
59 uint32_t packet_index,
60 const struct dc_info_packet *info_packet)
61 {
62 /* TODOFPGA Figure out a proper number for max_retries polling for lock
63 * use 50 for now.
64 */
65 uint32_t max_retries = 50;
66
67 /*we need turn on clock before programming AFMT block*/
68 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
69
70 if (packet_index >= 8)
71 ASSERT(0);
72
73 /* poll dig_update_lock is not locked -> asic internal signal
74 * assume otg master lock will unlock it
75 */
76 /* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
77 0, 10, max_retries);*/
78
79 /* check if HW reading GSP memory */
80 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
81 0, 10, max_retries);
82
83 /* HW does is not reading GSP memory not reading too long ->
84 * something wrong. clear GPS memory access and notify?
85 * hw SW is writing to GSP memory
86 */
87 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
88
89 /* choose which generic packet to use */
90 REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
91 AFMT_GENERIC_INDEX, packet_index);
92
93 /* write generic packet header
94 * (4th byte is for GENERIC0 only)
95 */
96 REG_SET_4(AFMT_GENERIC_HDR, 0,
97 AFMT_GENERIC_HB0, info_packet->hb0,
98 AFMT_GENERIC_HB1, info_packet->hb1,
99 AFMT_GENERIC_HB2, info_packet->hb2,
100 AFMT_GENERIC_HB3, info_packet->hb3);
101
102 /* write generic packet contents
103 * (we never use last 4 bytes)
104 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers
105 */
106 {
107 const uint32_t *content =
108 (const uint32_t *) &info_packet->sb[0];
109
110 REG_WRITE(AFMT_GENERIC_0, *content++);
111 REG_WRITE(AFMT_GENERIC_1, *content++);
112 REG_WRITE(AFMT_GENERIC_2, *content++);
113 REG_WRITE(AFMT_GENERIC_3, *content++);
114 REG_WRITE(AFMT_GENERIC_4, *content++);
115 REG_WRITE(AFMT_GENERIC_5, *content++);
116 REG_WRITE(AFMT_GENERIC_6, *content++);
117 REG_WRITE(AFMT_GENERIC_7, *content);
118 }
119
120 switch (packet_index) {
121 case 0:
122 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
123 AFMT_GENERIC0_IMMEDIATE_UPDATE, 1);
124 break;
125 case 1:
126 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
127 AFMT_GENERIC1_IMMEDIATE_UPDATE, 1);
128 break;
129 case 2:
130 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
131 AFMT_GENERIC2_IMMEDIATE_UPDATE, 1);
132 break;
133 case 3:
134 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
135 AFMT_GENERIC3_IMMEDIATE_UPDATE, 1);
136 break;
137 case 4:
138 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
139 AFMT_GENERIC4_IMMEDIATE_UPDATE, 1);
140 break;
141 case 5:
142 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
143 AFMT_GENERIC5_IMMEDIATE_UPDATE, 1);
144 break;
145 case 6:
146 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
147 AFMT_GENERIC6_IMMEDIATE_UPDATE, 1);
148 break;
149 case 7:
150 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
151 AFMT_GENERIC7_IMMEDIATE_UPDATE, 1);
152 break;
153 default:
154 break;
155 }
156 }
157
enc1_update_hdmi_info_packet(struct dcn10_stream_encoder * enc1,uint32_t packet_index,const struct dc_info_packet * info_packet)158 static void enc1_update_hdmi_info_packet(
159 struct dcn10_stream_encoder *enc1,
160 uint32_t packet_index,
161 const struct dc_info_packet *info_packet)
162 {
163 uint32_t cont, send, line;
164
165 if (info_packet->valid) {
166 enc1_update_generic_info_packet(
167 enc1,
168 packet_index,
169 info_packet);
170
171 /* enable transmission of packet(s) -
172 * packet transmission begins on the next frame
173 */
174 cont = 1;
175 /* send packet(s) every frame */
176 send = 1;
177 /* select line number to send packets on */
178 line = 2;
179 } else {
180 cont = 0;
181 send = 0;
182 line = 0;
183 }
184
185 /* choose which generic packet control to use */
186 switch (packet_index) {
187 case 0:
188 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
189 HDMI_GENERIC0_CONT, cont,
190 HDMI_GENERIC0_SEND, send,
191 HDMI_GENERIC0_LINE, line);
192 break;
193 case 1:
194 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
195 HDMI_GENERIC1_CONT, cont,
196 HDMI_GENERIC1_SEND, send,
197 HDMI_GENERIC1_LINE, line);
198 break;
199 case 2:
200 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
201 HDMI_GENERIC0_CONT, cont,
202 HDMI_GENERIC0_SEND, send,
203 HDMI_GENERIC0_LINE, line);
204 break;
205 case 3:
206 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
207 HDMI_GENERIC1_CONT, cont,
208 HDMI_GENERIC1_SEND, send,
209 HDMI_GENERIC1_LINE, line);
210 break;
211 case 4:
212 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
213 HDMI_GENERIC0_CONT, cont,
214 HDMI_GENERIC0_SEND, send,
215 HDMI_GENERIC0_LINE, line);
216 break;
217 case 5:
218 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
219 HDMI_GENERIC1_CONT, cont,
220 HDMI_GENERIC1_SEND, send,
221 HDMI_GENERIC1_LINE, line);
222 break;
223 case 6:
224 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
225 HDMI_GENERIC0_CONT, cont,
226 HDMI_GENERIC0_SEND, send,
227 HDMI_GENERIC0_LINE, line);
228 break;
229 case 7:
230 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
231 HDMI_GENERIC1_CONT, cont,
232 HDMI_GENERIC1_SEND, send,
233 HDMI_GENERIC1_LINE, line);
234 break;
235 default:
236 /* invalid HW packet index */
237 DC_LOG_WARNING(
238 "Invalid HW packet index: %s()\n",
239 __func__);
240 return;
241 }
242 }
243
244 /* setup stream encoder in dp mode */
enc1_stream_encoder_dp_set_stream_attribute(struct stream_encoder * enc,struct dc_crtc_timing * crtc_timing,enum dc_color_space output_color_space,bool use_vsc_sdp_for_colorimetry,uint32_t enable_sdp_splitting)245 void enc1_stream_encoder_dp_set_stream_attribute(
246 struct stream_encoder *enc,
247 struct dc_crtc_timing *crtc_timing,
248 enum dc_color_space output_color_space,
249 bool use_vsc_sdp_for_colorimetry,
250 uint32_t enable_sdp_splitting)
251 {
252 uint32_t h_active_start;
253 uint32_t v_active_start;
254 uint32_t misc0 = 0;
255 uint32_t misc1 = 0;
256 uint32_t h_blank;
257 uint32_t h_back_porch;
258 uint8_t synchronous_clock = 0; /* asynchronous mode */
259 uint8_t colorimetry_bpc;
260 uint8_t dp_pixel_encoding = 0;
261 uint8_t dp_component_depth = 0;
262
263 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
264 struct dc_crtc_timing hw_crtc_timing = *crtc_timing;
265
266 if (hw_crtc_timing.flags.INTERLACE) {
267 /*the input timing is in VESA spec format with Interlace flag =1*/
268 hw_crtc_timing.v_total /= 2;
269 hw_crtc_timing.v_border_top /= 2;
270 hw_crtc_timing.v_addressable /= 2;
271 hw_crtc_timing.v_border_bottom /= 2;
272 hw_crtc_timing.v_front_porch /= 2;
273 hw_crtc_timing.v_sync_width /= 2;
274 }
275
276
277 /* set pixel encoding */
278 switch (hw_crtc_timing.pixel_encoding) {
279 case PIXEL_ENCODING_YCBCR422:
280 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR422;
281 break;
282 case PIXEL_ENCODING_YCBCR444:
283 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR444;
284
285 if (hw_crtc_timing.flags.Y_ONLY)
286 if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666)
287 /* HW testing only, no use case yet.
288 * Color depth of Y-only could be
289 * 8, 10, 12, 16 bits
290 */
291 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_Y_ONLY;
292
293 /* Note: DP_MSA_MISC1 bit 7 is the indicator
294 * of Y-only mode.
295 * This bit is set in HW if register
296 * DP_PIXEL_ENCODING is programmed to 0x4
297 */
298 break;
299 case PIXEL_ENCODING_YCBCR420:
300 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR420;
301 break;
302 default:
303 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_RGB444;
304 break;
305 }
306
307 misc1 = REG_READ(DP_MSA_MISC);
308 /* For YCbCr420 and BT2020 Colorimetry Formats, VSC SDP shall be used.
309 * When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to indicate the
310 * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7,
311 * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care").
312 */
313 if (use_vsc_sdp_for_colorimetry)
314 misc1 = misc1 | 0x40;
315 else
316 misc1 = misc1 & ~0x40;
317
318 /* set color depth */
319 switch (hw_crtc_timing.display_color_depth) {
320 case COLOR_DEPTH_666:
321 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;
322 break;
323 case COLOR_DEPTH_888:
324 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_8BPC;
325 break;
326 case COLOR_DEPTH_101010:
327 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_10BPC;
328 break;
329 case COLOR_DEPTH_121212:
330 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_12BPC;
331 break;
332 case COLOR_DEPTH_161616:
333 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_16BPC;
334 break;
335 default:
336 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;
337 break;
338 }
339
340 /* Set DP pixel encoding and component depth */
341 REG_UPDATE_2(DP_PIXEL_FORMAT,
342 DP_PIXEL_ENCODING, dp_pixel_encoding,
343 DP_COMPONENT_DEPTH, dp_component_depth);
344
345 /* set dynamic range and YCbCr range */
346
347 switch (hw_crtc_timing.display_color_depth) {
348 case COLOR_DEPTH_666:
349 colorimetry_bpc = 0;
350 break;
351 case COLOR_DEPTH_888:
352 colorimetry_bpc = 1;
353 break;
354 case COLOR_DEPTH_101010:
355 colorimetry_bpc = 2;
356 break;
357 case COLOR_DEPTH_121212:
358 colorimetry_bpc = 3;
359 break;
360 default:
361 colorimetry_bpc = 0;
362 break;
363 }
364
365 misc0 = misc0 | synchronous_clock;
366 misc0 = colorimetry_bpc << 5;
367
368 switch (output_color_space) {
369 case COLOR_SPACE_SRGB:
370 misc1 = misc1 & ~0x80; /* bit7 = 0*/
371 break;
372 case COLOR_SPACE_SRGB_LIMITED:
373 misc0 = misc0 | 0x8; /* bit3=1 */
374 misc1 = misc1 & ~0x80; /* bit7 = 0*/
375 break;
376 case COLOR_SPACE_YCBCR601:
377 case COLOR_SPACE_YCBCR601_LIMITED:
378 misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
379 misc1 = misc1 & ~0x80; /* bit7 = 0*/
380 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
381 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
382 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
383 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
384 break;
385 case COLOR_SPACE_YCBCR709:
386 case COLOR_SPACE_YCBCR709_LIMITED:
387 misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
388 misc1 = misc1 & ~0x80; /* bit7 = 0*/
389 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
390 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
391 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
392 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
393 break;
394 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
395 case COLOR_SPACE_2020_RGB_FULLRANGE:
396 case COLOR_SPACE_2020_YCBCR_LIMITED:
397 case COLOR_SPACE_XR_RGB:
398 case COLOR_SPACE_MSREF_SCRGB:
399 case COLOR_SPACE_ADOBERGB:
400 case COLOR_SPACE_DCIP3:
401 case COLOR_SPACE_XV_YCC_709:
402 case COLOR_SPACE_XV_YCC_601:
403 case COLOR_SPACE_DISPLAYNATIVE:
404 case COLOR_SPACE_DOLBYVISION:
405 case COLOR_SPACE_APPCTRL:
406 case COLOR_SPACE_CUSTOMPOINTS:
407 case COLOR_SPACE_UNKNOWN:
408 case COLOR_SPACE_YCBCR709_BLACK:
409 default:
410 /* do nothing */
411 break;
412 }
413
414 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
415 REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */
416
417 /* dcn new register
418 * dc_crtc_timing is vesa dmt struct. data from edid
419 */
420 REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
421 DP_MSA_HTOTAL, hw_crtc_timing.h_total,
422 DP_MSA_VTOTAL, hw_crtc_timing.v_total);
423
424 /* calculate from vesa timing parameters
425 * h_active_start related to leading edge of sync
426 */
427
428 h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
429 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
430
431 h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
432 hw_crtc_timing.h_sync_width;
433
434 /* start at beginning of left border */
435 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
436
437
438 v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top -
439 hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
440 hw_crtc_timing.v_front_porch;
441
442
443 /* start at beginning of left border */
444 REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
445 DP_MSA_HSTART, h_active_start,
446 DP_MSA_VSTART, v_active_start);
447
448 REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
449 DP_MSA_HSYNCWIDTH,
450 hw_crtc_timing.h_sync_width,
451 DP_MSA_HSYNCPOLARITY,
452 !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY,
453 DP_MSA_VSYNCWIDTH,
454 hw_crtc_timing.v_sync_width,
455 DP_MSA_VSYNCPOLARITY,
456 !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY);
457
458 /* HWDITH include border or overscan */
459 REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
460 DP_MSA_HWIDTH, hw_crtc_timing.h_border_left +
461 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,
462 DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top +
463 hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom);
464 }
465
enc1_stream_encoder_set_stream_attribute_helper(struct dcn10_stream_encoder * enc1,struct dc_crtc_timing * crtc_timing)466 void enc1_stream_encoder_set_stream_attribute_helper(
467 struct dcn10_stream_encoder *enc1,
468 struct dc_crtc_timing *crtc_timing)
469 {
470 switch (crtc_timing->pixel_encoding) {
471 case PIXEL_ENCODING_YCBCR422:
472 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
473 break;
474 default:
475 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
476 break;
477 }
478 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
479 }
480
481 /* setup stream encoder in hdmi mode */
enc1_stream_encoder_hdmi_set_stream_attribute(struct stream_encoder * enc,struct dc_crtc_timing * crtc_timing,int actual_pix_clk_khz,bool enable_audio)482 void enc1_stream_encoder_hdmi_set_stream_attribute(
483 struct stream_encoder *enc,
484 struct dc_crtc_timing *crtc_timing,
485 int actual_pix_clk_khz,
486 bool enable_audio)
487 {
488 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
489 struct bp_encoder_control cntl = {0};
490
491 cntl.action = ENCODER_CONTROL_SETUP;
492 cntl.engine_id = enc1->base.id;
493 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
494 cntl.enable_dp_audio = enable_audio;
495 cntl.pixel_clock = actual_pix_clk_khz;
496 cntl.lanes_number = LANE_COUNT_FOUR;
497
498 if (enc1->base.bp->funcs->encoder_control(
499 enc1->base.bp, &cntl) != BP_RESULT_OK)
500 return;
501
502 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
503
504 /* setup HDMI engine */
505 REG_UPDATE_6(HDMI_CONTROL,
506 HDMI_PACKET_GEN_VERSION, 1,
507 HDMI_KEEPOUT_MODE, 1,
508 HDMI_DEEP_COLOR_ENABLE, 0,
509 HDMI_DATA_SCRAMBLE_EN, 0,
510 HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1,
511 HDMI_CLOCK_CHANNEL_RATE, 0);
512
513
514 switch (crtc_timing->display_color_depth) {
515 case COLOR_DEPTH_888:
516 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
517 DC_LOG_DEBUG("HDMI source set to 24BPP deep color depth\n");
518 break;
519 case COLOR_DEPTH_101010:
520 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
521 REG_UPDATE_2(HDMI_CONTROL,
522 HDMI_DEEP_COLOR_DEPTH, 1,
523 HDMI_DEEP_COLOR_ENABLE, 0);
524 DC_LOG_DEBUG("HDMI source 30BPP deep color depth" \
525 "disabled for YCBCR422 pixel encoding\n");
526 } else {
527 REG_UPDATE_2(HDMI_CONTROL,
528 HDMI_DEEP_COLOR_DEPTH, 1,
529 HDMI_DEEP_COLOR_ENABLE, 1);
530 DC_LOG_DEBUG("HDMI source 30BPP deep color depth" \
531 "enabled for YCBCR422 non-pixel encoding\n");
532 }
533 break;
534 case COLOR_DEPTH_121212:
535 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
536 REG_UPDATE_2(HDMI_CONTROL,
537 HDMI_DEEP_COLOR_DEPTH, 2,
538 HDMI_DEEP_COLOR_ENABLE, 0);
539 DC_LOG_DEBUG("HDMI source 36BPP deep color depth" \
540 "disabled for YCBCR422 pixel encoding\n");
541 } else {
542 REG_UPDATE_2(HDMI_CONTROL,
543 HDMI_DEEP_COLOR_DEPTH, 2,
544 HDMI_DEEP_COLOR_ENABLE, 1);
545 DC_LOG_DEBUG("HDMI source 36BPP deep color depth" \
546 "enabled for non-pixel YCBCR422 encoding\n");
547 }
548 break;
549 case COLOR_DEPTH_161616:
550 REG_UPDATE_2(HDMI_CONTROL,
551 HDMI_DEEP_COLOR_DEPTH, 3,
552 HDMI_DEEP_COLOR_ENABLE, 1);
553 DC_LOG_DEBUG("HDMI source deep color depth enabled in" \
554 "reserved mode\n");
555 break;
556 default:
557 break;
558 }
559
560 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
561 /* enable HDMI data scrambler
562 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
563 * Clock channel frequency is 1/4 of character rate.
564 */
565 REG_UPDATE_2(HDMI_CONTROL,
566 HDMI_DATA_SCRAMBLE_EN, 1,
567 HDMI_CLOCK_CHANNEL_RATE, 1);
568 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
569
570 /* TODO: New feature for DCE11, still need to implement */
571
572 /* enable HDMI data scrambler
573 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
574 * Clock channel frequency is the same
575 * as character rate
576 */
577 REG_UPDATE_2(HDMI_CONTROL,
578 HDMI_DATA_SCRAMBLE_EN, 1,
579 HDMI_CLOCK_CHANNEL_RATE, 0);
580 }
581
582
583 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
584 HDMI_GC_CONT, 1,
585 HDMI_GC_SEND, 1,
586 HDMI_NULL_SEND, 1);
587
588 REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);
589
590 /* following belongs to audio */
591 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
592
593 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
594
595 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
596 VBI_LINE_0 + 2);
597
598 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
599 }
600
601 /* setup stream encoder in dvi mode */
enc1_stream_encoder_dvi_set_stream_attribute(struct stream_encoder * enc,struct dc_crtc_timing * crtc_timing,bool is_dual_link)602 void enc1_stream_encoder_dvi_set_stream_attribute(
603 struct stream_encoder *enc,
604 struct dc_crtc_timing *crtc_timing,
605 bool is_dual_link)
606 {
607 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
608 struct bp_encoder_control cntl = {0};
609
610 cntl.action = ENCODER_CONTROL_SETUP;
611 cntl.engine_id = enc1->base.id;
612 cntl.signal = is_dual_link ?
613 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
614 cntl.enable_dp_audio = false;
615 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
616 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
617
618 if (enc1->base.bp->funcs->encoder_control(
619 enc1->base.bp, &cntl) != BP_RESULT_OK)
620 return;
621
622 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
623 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
624 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
625 }
626
enc1_stream_encoder_set_throttled_vcp_size(struct stream_encoder * enc,struct fixed31_32 avg_time_slots_per_mtp)627 void enc1_stream_encoder_set_throttled_vcp_size(
628 struct stream_encoder *enc,
629 struct fixed31_32 avg_time_slots_per_mtp)
630 {
631 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
632 uint32_t x = dc_fixpt_floor(
633 avg_time_slots_per_mtp);
634 uint32_t y = dc_fixpt_ceil(
635 dc_fixpt_shl(
636 dc_fixpt_sub_int(
637 avg_time_slots_per_mtp,
638 x),
639 26));
640
641 // If y rounds up to integer, carry it over to x.
642 if (y >> 26) {
643 x += 1;
644 y = 0;
645 }
646
647 REG_SET_2(DP_MSE_RATE_CNTL, 0,
648 DP_MSE_RATE_X, x,
649 DP_MSE_RATE_Y, y);
650
651 /* wait for update to be completed on the link */
652 /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
653 /* is reset to 0 (not pending) */
654 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
655 0,
656 10, DP_MST_UPDATE_MAX_RETRY);
657 }
658
enc1_stream_encoder_update_hdmi_info_packets(struct stream_encoder * enc,const struct encoder_info_frame * info_frame)659 static void enc1_stream_encoder_update_hdmi_info_packets(
660 struct stream_encoder *enc,
661 const struct encoder_info_frame *info_frame)
662 {
663 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
664
665 /* for bring up, disable dp double TODO */
666 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
667
668 /*Always add mandatory packets first followed by optional ones*/
669 enc1_update_hdmi_info_packet(enc1, 0, &info_frame->avi);
670 enc1_update_hdmi_info_packet(enc1, 1, &info_frame->hfvsif);
671 enc1_update_hdmi_info_packet(enc1, 2, &info_frame->gamut);
672 enc1_update_hdmi_info_packet(enc1, 3, &info_frame->vendor);
673 enc1_update_hdmi_info_packet(enc1, 4, &info_frame->spd);
674 enc1_update_hdmi_info_packet(enc1, 5, &info_frame->hdrsmd);
675 }
676
enc1_stream_encoder_stop_hdmi_info_packets(struct stream_encoder * enc)677 static void enc1_stream_encoder_stop_hdmi_info_packets(
678 struct stream_encoder *enc)
679 {
680 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
681
682 /* stop generic packets 0 & 1 on HDMI */
683 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
684 HDMI_GENERIC1_CONT, 0,
685 HDMI_GENERIC1_LINE, 0,
686 HDMI_GENERIC1_SEND, 0,
687 HDMI_GENERIC0_CONT, 0,
688 HDMI_GENERIC0_LINE, 0,
689 HDMI_GENERIC0_SEND, 0);
690
691 /* stop generic packets 2 & 3 on HDMI */
692 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
693 HDMI_GENERIC0_CONT, 0,
694 HDMI_GENERIC0_LINE, 0,
695 HDMI_GENERIC0_SEND, 0,
696 HDMI_GENERIC1_CONT, 0,
697 HDMI_GENERIC1_LINE, 0,
698 HDMI_GENERIC1_SEND, 0);
699
700 /* stop generic packets 2 & 3 on HDMI */
701 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
702 HDMI_GENERIC0_CONT, 0,
703 HDMI_GENERIC0_LINE, 0,
704 HDMI_GENERIC0_SEND, 0,
705 HDMI_GENERIC1_CONT, 0,
706 HDMI_GENERIC1_LINE, 0,
707 HDMI_GENERIC1_SEND, 0);
708
709 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,
710 HDMI_GENERIC0_CONT, 0,
711 HDMI_GENERIC0_LINE, 0,
712 HDMI_GENERIC0_SEND, 0,
713 HDMI_GENERIC1_CONT, 0,
714 HDMI_GENERIC1_LINE, 0,
715 HDMI_GENERIC1_SEND, 0);
716 }
717
enc1_stream_encoder_update_dp_info_packets(struct stream_encoder * enc,const struct encoder_info_frame * info_frame)718 void enc1_stream_encoder_update_dp_info_packets(
719 struct stream_encoder *enc,
720 const struct encoder_info_frame *info_frame)
721 {
722 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
723 uint32_t value = 0;
724
725 if (info_frame->vsc.valid)
726 enc1_update_generic_info_packet(
727 enc1,
728 0, /* packetIndex */
729 &info_frame->vsc);
730
731 /* VSC SDP at packetIndex 1 is used by PSR in DMCUB FW.
732 * Note that the enablement of GSP1 is not done below,
733 * it's done in FW.
734 */
735 if (info_frame->vsc.valid)
736 enc1_update_generic_info_packet(
737 enc1,
738 1, /* packetIndex */
739 &info_frame->vsc);
740
741 if (info_frame->spd.valid)
742 enc1_update_generic_info_packet(
743 enc1,
744 2, /* packetIndex */
745 &info_frame->spd);
746
747 if (info_frame->hdrsmd.valid)
748 enc1_update_generic_info_packet(
749 enc1,
750 3, /* packetIndex */
751 &info_frame->hdrsmd);
752
753 /* packetIndex 4 is used for send immediate sdp message, and please
754 * use other packetIndex (such as 5,6) for other info packet
755 */
756
757 if (info_frame->adaptive_sync.valid)
758 enc1_update_generic_info_packet(
759 enc1,
760 5, /* packetIndex */
761 &info_frame->adaptive_sync);
762
763 /* enable/disable transmission of packet(s).
764 * If enabled, packet transmission begins on the next frame
765 */
766 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
767 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
768 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
769 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, info_frame->adaptive_sync.valid);
770
771 /* This bit is the master enable bit.
772 * When enabling secondary stream engine,
773 * this master bit must also be set.
774 * This register shared with audio info frame.
775 * Therefore we need to enable master bit
776 * if at least on of the fields is not 0
777 */
778 value = REG_READ(DP_SEC_CNTL);
779 if (value)
780 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
781 }
782
enc1_stream_encoder_send_immediate_sdp_message(struct stream_encoder * enc,const uint8_t * custom_sdp_message,unsigned int sdp_message_size)783 void enc1_stream_encoder_send_immediate_sdp_message(
784 struct stream_encoder *enc,
785 const uint8_t *custom_sdp_message,
786 unsigned int sdp_message_size)
787 {
788 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
789 uint32_t value = 0;
790
791 /* TODOFPGA Figure out a proper number for max_retries polling for lock
792 * use 50 for now.
793 */
794 uint32_t max_retries = 50;
795
796 /* check if GSP4 is transmitted */
797 REG_WAIT(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING,
798 0, 10, max_retries);
799
800 /* disable GSP4 transmitting */
801 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 0);
802
803 /* transmit GSP4 at the earliest time in a frame */
804 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, 1);
805
806 /*we need turn on clock before programming AFMT block*/
807 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
808
809 /* check if HW reading GSP memory */
810 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
811 0, 10, max_retries);
812
813 /* HW does is not reading GSP memory not reading too long ->
814 * something wrong. clear GPS memory access and notify?
815 * hw SW is writing to GSP memory
816 */
817 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
818
819 /* use generic packet 4 for immediate sdp message */
820 REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
821 AFMT_GENERIC_INDEX, 4);
822
823 /* write generic packet header
824 * (4th byte is for GENERIC0 only)
825 */
826 REG_SET_4(AFMT_GENERIC_HDR, 0,
827 AFMT_GENERIC_HB0, custom_sdp_message[0],
828 AFMT_GENERIC_HB1, custom_sdp_message[1],
829 AFMT_GENERIC_HB2, custom_sdp_message[2],
830 AFMT_GENERIC_HB3, custom_sdp_message[3]);
831
832 /* write generic packet contents
833 * (we never use last 4 bytes)
834 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers
835 */
836 {
837 const uint32_t *content =
838 (const uint32_t *) &custom_sdp_message[4];
839
840 REG_WRITE(AFMT_GENERIC_0, *content++);
841 REG_WRITE(AFMT_GENERIC_1, *content++);
842 REG_WRITE(AFMT_GENERIC_2, *content++);
843 REG_WRITE(AFMT_GENERIC_3, *content++);
844 REG_WRITE(AFMT_GENERIC_4, *content++);
845 REG_WRITE(AFMT_GENERIC_5, *content++);
846 REG_WRITE(AFMT_GENERIC_6, *content++);
847 REG_WRITE(AFMT_GENERIC_7, *content);
848 }
849
850 /* check whether GENERIC4 registers double buffer update in immediate mode
851 * is pending
852 */
853 REG_WAIT(AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING,
854 0, 10, max_retries);
855
856 /* atomically update double-buffered GENERIC4 registers in immediate mode
857 * (update immediately)
858 */
859 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
860 AFMT_GENERIC4_IMMEDIATE_UPDATE, 1);
861
862 /* enable GSP4 transmitting */
863 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 1);
864
865 /* This bit is the master enable bit.
866 * When enabling secondary stream engine,
867 * this master bit must also be set.
868 * This register shared with audio info frame.
869 * Therefore we need to enable master bit
870 * if at least on of the fields is not 0
871 */
872 value = REG_READ(DP_SEC_CNTL);
873 if (value)
874 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
875 }
876
enc1_stream_encoder_stop_dp_info_packets(struct stream_encoder * enc)877 void enc1_stream_encoder_stop_dp_info_packets(
878 struct stream_encoder *enc)
879 {
880 /* stop generic packets on DP */
881 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
882 uint32_t value = 0;
883
884 REG_SET_10(DP_SEC_CNTL, 0,
885 DP_SEC_GSP0_ENABLE, 0,
886 DP_SEC_GSP1_ENABLE, 0,
887 DP_SEC_GSP2_ENABLE, 0,
888 DP_SEC_GSP3_ENABLE, 0,
889 DP_SEC_GSP4_ENABLE, 0,
890 DP_SEC_GSP5_ENABLE, 0,
891 DP_SEC_GSP6_ENABLE, 0,
892 DP_SEC_GSP7_ENABLE, 0,
893 DP_SEC_MPG_ENABLE, 0,
894 DP_SEC_STREAM_ENABLE, 0);
895
896 /* this register shared with audio info frame.
897 * therefore we need to keep master enabled
898 * if at least one of the fields is not 0 */
899 value = REG_READ(DP_SEC_CNTL);
900 if (value)
901 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
902
903 }
904
enc1_stream_encoder_dp_blank(struct dc_link * link,struct stream_encoder * enc)905 void enc1_stream_encoder_dp_blank(
906 struct dc_link *link,
907 struct stream_encoder *enc)
908 {
909 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
910 uint32_t reg1 = 0;
911 uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
912
913 /* Note: For CZ, we are changing driver default to disable
914 * stream deferred to next VBLANK. If results are positive, we
915 * will make the same change to all DCE versions. There are a
916 * handful of panels that cannot handle disable stream at
917 * HBLANK and will result in a white line flash across the
918 * screen on stream disable.
919 */
920 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1);
921 if ((reg1 & 0x1) == 0)
922 /*stream not enabled*/
923 return;
924 /* Specify the video stream disable point
925 * (2 = start of the next vertical blank)
926 */
927 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
928 /* Larger delay to wait until VBLANK - use max retry of
929 * 10us*10200=102ms. This covers 100.0ms of minimum 10 Hz mode +
930 * a little more because we may not trust delay accuracy.
931 */
932 max_retries = DP_BLANK_MAX_RETRY * 501;
933
934 /* disable DP stream */
935 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
936
937 link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_DP_VID_STREAM);
938
939 /* the encoder stops sending the video stream
940 * at the start of the vertical blanking.
941 * Poll for DP_VID_STREAM_STATUS == 0
942 */
943
944 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
945 0,
946 10, max_retries);
947
948 /* Tell the DP encoder to ignore timing from CRTC, must be done after
949 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
950 * complete, stream status will be stuck in video stream enabled state,
951 * i.e. DP_VID_STREAM_STATUS stuck at 1.
952 */
953
954 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
955
956 link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_FIFO_STEER_RESET);
957 }
958
959 /* output video stream to link encoder */
enc1_stream_encoder_dp_unblank(struct dc_link * link,struct stream_encoder * enc,const struct encoder_unblank_param * param)960 void enc1_stream_encoder_dp_unblank(
961 struct dc_link *link,
962 struct stream_encoder *enc,
963 const struct encoder_unblank_param *param)
964 {
965 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
966
967 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
968 uint32_t n_vid = 0x8000;
969 uint32_t m_vid;
970 uint32_t n_multiply = 0;
971 uint64_t m_vid_l = n_vid;
972
973 /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
974 if (param->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
975 /*this param->pixel_clk_khz is half of 444 rate for 420 already*/
976 n_multiply = 1;
977 }
978 /* M / N = Fstream / Flink
979 * m_vid / n_vid = pixel rate / link rate
980 */
981
982 m_vid_l *= param->timing.pix_clk_100hz / 10;
983 m_vid_l = div_u64(m_vid_l,
984 param->link_settings.link_rate
985 * LINK_RATE_REF_FREQ_IN_KHZ);
986
987 m_vid = (uint32_t) m_vid_l;
988
989 /* enable auto measurement */
990
991 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
992
993 /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
994 * therefore program initial value for Mvid and Nvid
995 */
996
997 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
998
999 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
1000
1001 REG_UPDATE_2(DP_VID_TIMING,
1002 DP_VID_M_N_GEN_EN, 1,
1003 DP_VID_N_MUL, n_multiply);
1004 }
1005
1006 /* set DIG_START to 0x1 to resync FIFO */
1007
1008 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
1009
1010 /* switch DP encoder to CRTC data */
1011
1012 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
1013
1014 /* wait 100us for DIG/DP logic to prime
1015 * (i.e. a few video lines)
1016 */
1017 udelay(100);
1018
1019 /* the hardware would start sending video at the start of the next DP
1020 * frame (i.e. rising edge of the vblank).
1021 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
1022 * register has no effect on enable transition! HW always guarantees
1023 * VID_STREAM enable at start of next frame, and this is not
1024 * programmable
1025 */
1026
1027 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
1028
1029 link->dc->link_srv->dp_trace_source_sequence(link,
1030 DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM);
1031 }
1032
enc1_stream_encoder_set_avmute(struct stream_encoder * enc,bool enable)1033 void enc1_stream_encoder_set_avmute(
1034 struct stream_encoder *enc,
1035 bool enable)
1036 {
1037 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1038 unsigned int value = enable ? 1 : 0;
1039
1040 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
1041 }
1042
enc1_reset_hdmi_stream_attribute(struct stream_encoder * enc)1043 void enc1_reset_hdmi_stream_attribute(
1044 struct stream_encoder *enc)
1045 {
1046 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1047
1048 REG_UPDATE_5(HDMI_CONTROL,
1049 HDMI_PACKET_GEN_VERSION, 1,
1050 HDMI_KEEPOUT_MODE, 1,
1051 HDMI_DEEP_COLOR_ENABLE, 0,
1052 HDMI_DATA_SCRAMBLE_EN, 0,
1053 HDMI_CLOCK_CHANNEL_RATE, 0);
1054 }
1055
1056
1057 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
1058 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
1059
1060 #include "include/audio_types.h"
1061
1062
1063 /* 25.2MHz/1.001*/
1064 /* 25.2MHz/1.001*/
1065 /* 25.2MHz*/
1066 /* 27MHz */
1067 /* 27MHz*1.001*/
1068 /* 27MHz*1.001*/
1069 /* 54MHz*/
1070 /* 54MHz*1.001*/
1071 /* 74.25MHz/1.001*/
1072 /* 74.25MHz*/
1073 /* 148.5MHz/1.001*/
1074 /* 148.5MHz*/
1075
1076 static const struct audio_clock_info audio_clock_info_table[16] = {
1077 {2517, 4576, 28125, 7007, 31250, 6864, 28125},
1078 {2518, 4576, 28125, 7007, 31250, 6864, 28125},
1079 {2520, 4096, 25200, 6272, 28000, 6144, 25200},
1080 {2700, 4096, 27000, 6272, 30000, 6144, 27000},
1081 {2702, 4096, 27027, 6272, 30030, 6144, 27027},
1082 {2703, 4096, 27027, 6272, 30030, 6144, 27027},
1083 {5400, 4096, 54000, 6272, 60000, 6144, 54000},
1084 {5405, 4096, 54054, 6272, 60060, 6144, 54054},
1085 {7417, 11648, 210937, 17836, 234375, 11648, 140625},
1086 {7425, 4096, 74250, 6272, 82500, 6144, 74250},
1087 {14835, 11648, 421875, 8918, 234375, 5824, 140625},
1088 {14850, 4096, 148500, 6272, 165000, 6144, 148500},
1089 {29670, 5824, 421875, 4459, 234375, 5824, 281250},
1090 {29700, 3072, 222750, 4704, 247500, 5120, 247500},
1091 {59340, 5824, 843750, 8918, 937500, 5824, 562500},
1092 {59400, 3072, 445500, 9408, 990000, 6144, 594000}
1093 };
1094
1095 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
1096 {2517, 9152, 84375, 7007, 48875, 9152, 56250},
1097 {2518, 9152, 84375, 7007, 48875, 9152, 56250},
1098 {2520, 4096, 37800, 6272, 42000, 6144, 37800},
1099 {2700, 4096, 40500, 6272, 45000, 6144, 40500},
1100 {2702, 8192, 81081, 6272, 45045, 8192, 54054},
1101 {2703, 8192, 81081, 6272, 45045, 8192, 54054},
1102 {5400, 4096, 81000, 6272, 90000, 6144, 81000},
1103 {5405, 4096, 81081, 6272, 90090, 6144, 81081},
1104 {7417, 11648, 316406, 17836, 351562, 11648, 210937},
1105 {7425, 4096, 111375, 6272, 123750, 6144, 111375},
1106 {14835, 11648, 632812, 17836, 703125, 11648, 421875},
1107 {14850, 4096, 222750, 6272, 247500, 6144, 222750},
1108 {29670, 5824, 632812, 8918, 703125, 5824, 421875},
1109 {29700, 4096, 445500, 4704, 371250, 5120, 371250}
1110 };
1111
1112 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
1113 {2517, 4576, 56250, 7007, 62500, 6864, 56250},
1114 {2518, 4576, 56250, 7007, 62500, 6864, 56250},
1115 {2520, 4096, 50400, 6272, 56000, 6144, 50400},
1116 {2700, 4096, 54000, 6272, 60000, 6144, 54000},
1117 {2702, 4096, 54054, 6267, 60060, 8192, 54054},
1118 {2703, 4096, 54054, 6272, 60060, 8192, 54054},
1119 {5400, 4096, 108000, 6272, 120000, 6144, 108000},
1120 {5405, 4096, 108108, 6272, 120120, 6144, 108108},
1121 {7417, 11648, 421875, 17836, 468750, 11648, 281250},
1122 {7425, 4096, 148500, 6272, 165000, 6144, 148500},
1123 {14835, 11648, 843750, 8918, 468750, 11648, 281250},
1124 {14850, 4096, 297000, 6272, 330000, 6144, 297000},
1125 {29670, 5824, 843750, 4459, 468750, 5824, 562500},
1126 {29700, 3072, 445500, 4704, 495000, 5120, 495000}
1127
1128
1129 };
1130
speakers_to_channels(struct audio_speaker_flags speaker_flags)1131 static union audio_cea_channels speakers_to_channels(
1132 struct audio_speaker_flags speaker_flags)
1133 {
1134 union audio_cea_channels cea_channels = {0};
1135
1136 /* these are one to one */
1137 cea_channels.channels.FL = speaker_flags.FL_FR;
1138 cea_channels.channels.FR = speaker_flags.FL_FR;
1139 cea_channels.channels.LFE = speaker_flags.LFE;
1140 cea_channels.channels.FC = speaker_flags.FC;
1141
1142 /* if Rear Left and Right exist move RC speaker to channel 7
1143 * otherwise to channel 5
1144 */
1145 if (speaker_flags.RL_RR) {
1146 cea_channels.channels.RL_RC = speaker_flags.RL_RR;
1147 cea_channels.channels.RR = speaker_flags.RL_RR;
1148 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
1149 } else {
1150 cea_channels.channels.RL_RC = speaker_flags.RC;
1151 }
1152
1153 /* FRONT Left Right Center and REAR Left Right Center are exclusive */
1154 if (speaker_flags.FLC_FRC) {
1155 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
1156 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
1157 } else {
1158 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
1159 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
1160 }
1161
1162 return cea_channels;
1163 }
1164
get_audio_clock_info(enum dc_color_depth color_depth,uint32_t crtc_pixel_clock_100Hz,uint32_t actual_pixel_clock_100Hz,struct audio_clock_info * audio_clock_info)1165 void get_audio_clock_info(
1166 enum dc_color_depth color_depth,
1167 uint32_t crtc_pixel_clock_100Hz,
1168 uint32_t actual_pixel_clock_100Hz,
1169 struct audio_clock_info *audio_clock_info)
1170 {
1171 const struct audio_clock_info *clock_info;
1172 uint32_t index;
1173 uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100;
1174 uint32_t audio_array_size;
1175
1176 switch (color_depth) {
1177 case COLOR_DEPTH_161616:
1178 clock_info = audio_clock_info_table_48bpc;
1179 audio_array_size = ARRAY_SIZE(
1180 audio_clock_info_table_48bpc);
1181 break;
1182 case COLOR_DEPTH_121212:
1183 clock_info = audio_clock_info_table_36bpc;
1184 audio_array_size = ARRAY_SIZE(
1185 audio_clock_info_table_36bpc);
1186 break;
1187 default:
1188 clock_info = audio_clock_info_table;
1189 audio_array_size = ARRAY_SIZE(
1190 audio_clock_info_table);
1191 break;
1192 }
1193
1194 if (clock_info != NULL) {
1195 /* search for exact pixel clock in table */
1196 for (index = 0; index < audio_array_size; index++) {
1197 if (clock_info[index].pixel_clock_in_10khz >
1198 crtc_pixel_clock_in_10khz)
1199 break; /* not match */
1200 else if (clock_info[index].pixel_clock_in_10khz ==
1201 crtc_pixel_clock_in_10khz) {
1202 /* match found */
1203 *audio_clock_info = clock_info[index];
1204 return;
1205 }
1206 }
1207 }
1208
1209 /* not found */
1210 if (actual_pixel_clock_100Hz == 0)
1211 actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz;
1212
1213 /* See HDMI spec the table entry under
1214 * pixel clock of "Other". */
1215 audio_clock_info->pixel_clock_in_10khz =
1216 actual_pixel_clock_100Hz / 100;
1217 audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10;
1218 audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10;
1219 audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10;
1220
1221 audio_clock_info->n_32khz = 4096;
1222 audio_clock_info->n_44khz = 6272;
1223 audio_clock_info->n_48khz = 6144;
1224 }
1225
enc1_se_audio_setup(struct stream_encoder * enc,unsigned int az_inst,struct audio_info * audio_info)1226 static void enc1_se_audio_setup(
1227 struct stream_encoder *enc,
1228 unsigned int az_inst,
1229 struct audio_info *audio_info)
1230 {
1231 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1232
1233 uint32_t channels = 0;
1234
1235 ASSERT(audio_info);
1236 if (audio_info == NULL)
1237 /* This should not happen.it does so we don't get BSOD*/
1238 return;
1239
1240 channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
1241
1242 /* setup the audio stream source select (audio -> dig mapping) */
1243 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);
1244
1245 /* Channel allocation */
1246 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
1247 }
1248
enc1_se_setup_hdmi_audio(struct stream_encoder * enc,const struct audio_crtc_info * crtc_info)1249 static void enc1_se_setup_hdmi_audio(
1250 struct stream_encoder *enc,
1251 const struct audio_crtc_info *crtc_info)
1252 {
1253 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1254
1255 struct audio_clock_info audio_clock_info = {0};
1256
1257 /* HDMI_AUDIO_PACKET_CONTROL */
1258 REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL,
1259 HDMI_AUDIO_DELAY_EN, 1);
1260
1261 /* AFMT_AUDIO_PACKET_CONTROL */
1262 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1263
1264 /* AFMT_AUDIO_PACKET_CONTROL2 */
1265 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1266 AFMT_AUDIO_LAYOUT_OVRD, 0,
1267 AFMT_60958_OSF_OVRD, 0);
1268
1269 /* HDMI_ACR_PACKET_CONTROL */
1270 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
1271 HDMI_ACR_AUTO_SEND, 1,
1272 HDMI_ACR_SOURCE, 0,
1273 HDMI_ACR_AUDIO_PRIORITY, 0);
1274
1275 /* Program audio clock sample/regeneration parameters */
1276 get_audio_clock_info(crtc_info->color_depth,
1277 crtc_info->requested_pixel_clock_100Hz,
1278 crtc_info->calculated_pixel_clock_100Hz,
1279 &audio_clock_info);
1280 DC_LOG_HW_AUDIO(
1281 "\n%s:Input::requested_pixel_clock_100Hz = %d" \
1282 "calculated_pixel_clock_100Hz = %d \n", __func__, \
1283 crtc_info->requested_pixel_clock_100Hz, \
1284 crtc_info->calculated_pixel_clock_100Hz);
1285
1286 /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
1287 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
1288
1289 /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
1290 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
1291
1292 /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
1293 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
1294
1295 /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
1296 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
1297
1298 /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
1299 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
1300
1301 /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
1302 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
1303
1304 /* Video driver cannot know in advance which sample rate will
1305 * be used by HD Audio driver
1306 * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
1307 * programmed below in interruppt callback
1308 */
1309
1310 /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
1311 * AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK
1312 */
1313 REG_UPDATE_2(AFMT_60958_0,
1314 AFMT_60958_CS_CHANNEL_NUMBER_L, 1,
1315 AFMT_60958_CS_CLOCK_ACCURACY, 0);
1316
1317 /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
1318 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1319
1320 /* AFMT_60958_2 now keep this settings until
1321 * Programming guide comes out
1322 */
1323 REG_UPDATE_6(AFMT_60958_2,
1324 AFMT_60958_CS_CHANNEL_NUMBER_2, 3,
1325 AFMT_60958_CS_CHANNEL_NUMBER_3, 4,
1326 AFMT_60958_CS_CHANNEL_NUMBER_4, 5,
1327 AFMT_60958_CS_CHANNEL_NUMBER_5, 6,
1328 AFMT_60958_CS_CHANNEL_NUMBER_6, 7,
1329 AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1330 }
1331
enc1_se_setup_dp_audio(struct stream_encoder * enc)1332 static void enc1_se_setup_dp_audio(
1333 struct stream_encoder *enc)
1334 {
1335 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1336
1337 /* --- DP Audio packet configurations --- */
1338
1339 /* ATP Configuration */
1340 REG_SET(DP_SEC_AUD_N, 0,
1341 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
1342
1343 /* Async/auto-calc timestamp mode */
1344 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
1345 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
1346
1347 /* --- The following are the registers
1348 * copied from the SetupHDMI ---
1349 */
1350
1351 /* AFMT_AUDIO_PACKET_CONTROL */
1352 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1353
1354 /* AFMT_AUDIO_PACKET_CONTROL2 */
1355 /* Program the ATP and AIP next */
1356 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1357 AFMT_AUDIO_LAYOUT_OVRD, 0,
1358 AFMT_60958_OSF_OVRD, 0);
1359
1360 /* AFMT_INFOFRAME_CONTROL0 */
1361 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1362
1363 /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1364 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
1365 }
1366
enc1_se_enable_audio_clock(struct stream_encoder * enc,bool enable)1367 void enc1_se_enable_audio_clock(
1368 struct stream_encoder *enc,
1369 bool enable)
1370 {
1371 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1372
1373 if (REG(AFMT_CNTL) == 0)
1374 return; /* DCE8/10 does not have this register */
1375
1376 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
1377
1378 /* wait for AFMT clock to turn on,
1379 * expectation: this should complete in 1-2 reads
1380 *
1381 * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
1382 *
1383 * TODO: wait for clock_on does not work well. May need HW
1384 * program sequence. But audio seems work normally even without wait
1385 * for clock_on status change
1386 */
1387 }
1388
enc1_se_enable_dp_audio(struct stream_encoder * enc)1389 void enc1_se_enable_dp_audio(
1390 struct stream_encoder *enc)
1391 {
1392 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1393
1394 /* Enable Audio packets */
1395 REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1396
1397 /* Program the ATP and AIP next */
1398 REG_UPDATE_2(DP_SEC_CNTL,
1399 DP_SEC_ATP_ENABLE, 1,
1400 DP_SEC_AIP_ENABLE, 1);
1401
1402 /* Program STREAM_ENABLE after all the other enables. */
1403 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1404 }
1405
enc1_se_disable_dp_audio(struct stream_encoder * enc)1406 static void enc1_se_disable_dp_audio(
1407 struct stream_encoder *enc)
1408 {
1409 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1410 uint32_t value = 0;
1411
1412 /* Disable Audio packets */
1413 REG_UPDATE_5(DP_SEC_CNTL,
1414 DP_SEC_ASP_ENABLE, 0,
1415 DP_SEC_ATP_ENABLE, 0,
1416 DP_SEC_AIP_ENABLE, 0,
1417 DP_SEC_ACM_ENABLE, 0,
1418 DP_SEC_STREAM_ENABLE, 0);
1419
1420 /* This register shared with encoder info frame. Therefore we need to
1421 * keep master enabled if at least on of the fields is not 0
1422 */
1423 value = REG_READ(DP_SEC_CNTL);
1424 if (value != 0)
1425 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1426
1427 }
1428
enc1_se_audio_mute_control(struct stream_encoder * enc,bool mute)1429 void enc1_se_audio_mute_control(
1430 struct stream_encoder *enc,
1431 bool mute)
1432 {
1433 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1434
1435 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
1436 }
1437
enc1_se_dp_audio_setup(struct stream_encoder * enc,unsigned int az_inst,struct audio_info * info)1438 void enc1_se_dp_audio_setup(
1439 struct stream_encoder *enc,
1440 unsigned int az_inst,
1441 struct audio_info *info)
1442 {
1443 enc1_se_audio_setup(enc, az_inst, info);
1444 }
1445
enc1_se_dp_audio_enable(struct stream_encoder * enc)1446 void enc1_se_dp_audio_enable(
1447 struct stream_encoder *enc)
1448 {
1449 enc1_se_enable_audio_clock(enc, true);
1450 enc1_se_setup_dp_audio(enc);
1451 enc1_se_enable_dp_audio(enc);
1452 }
1453
enc1_se_dp_audio_disable(struct stream_encoder * enc)1454 void enc1_se_dp_audio_disable(
1455 struct stream_encoder *enc)
1456 {
1457 enc1_se_disable_dp_audio(enc);
1458 enc1_se_enable_audio_clock(enc, false);
1459 }
1460
enc1_se_hdmi_audio_setup(struct stream_encoder * enc,unsigned int az_inst,struct audio_info * info,struct audio_crtc_info * audio_crtc_info)1461 void enc1_se_hdmi_audio_setup(
1462 struct stream_encoder *enc,
1463 unsigned int az_inst,
1464 struct audio_info *info,
1465 struct audio_crtc_info *audio_crtc_info)
1466 {
1467 enc1_se_enable_audio_clock(enc, true);
1468 enc1_se_setup_hdmi_audio(enc, audio_crtc_info);
1469 enc1_se_audio_setup(enc, az_inst, info);
1470 }
1471
enc1_se_hdmi_audio_disable(struct stream_encoder * enc)1472 void enc1_se_hdmi_audio_disable(
1473 struct stream_encoder *enc)
1474 {
1475 if (enc->afmt && enc->afmt->funcs->afmt_powerdown)
1476 enc->afmt->funcs->afmt_powerdown(enc->afmt);
1477
1478 enc1_se_enable_audio_clock(enc, false);
1479 }
1480
1481
enc1_setup_stereo_sync(struct stream_encoder * enc,int tg_inst,bool enable)1482 void enc1_setup_stereo_sync(
1483 struct stream_encoder *enc,
1484 int tg_inst, bool enable)
1485 {
1486 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1487 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
1488 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
1489 }
1490
enc1_dig_connect_to_otg(struct stream_encoder * enc,int tg_inst)1491 void enc1_dig_connect_to_otg(
1492 struct stream_encoder *enc,
1493 int tg_inst)
1494 {
1495 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1496
1497 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
1498 }
1499
enc1_dig_source_otg(struct stream_encoder * enc)1500 unsigned int enc1_dig_source_otg(
1501 struct stream_encoder *enc)
1502 {
1503 uint32_t tg_inst = 0;
1504 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1505
1506 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
1507
1508 return tg_inst;
1509 }
1510
enc1_stream_encoder_dp_get_pixel_format(struct stream_encoder * enc,enum dc_pixel_encoding * encoding,enum dc_color_depth * depth)1511 bool enc1_stream_encoder_dp_get_pixel_format(
1512 struct stream_encoder *enc,
1513 enum dc_pixel_encoding *encoding,
1514 enum dc_color_depth *depth)
1515 {
1516 uint32_t hw_encoding = 0;
1517 uint32_t hw_depth = 0;
1518 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1519
1520 if (enc == NULL ||
1521 encoding == NULL ||
1522 depth == NULL)
1523 return false;
1524
1525 REG_GET_2(DP_PIXEL_FORMAT,
1526 DP_PIXEL_ENCODING, &hw_encoding,
1527 DP_COMPONENT_DEPTH, &hw_depth);
1528
1529 switch (hw_depth) {
1530 case DP_COMPONENT_PIXEL_DEPTH_6BPC:
1531 *depth = COLOR_DEPTH_666;
1532 break;
1533 case DP_COMPONENT_PIXEL_DEPTH_8BPC:
1534 *depth = COLOR_DEPTH_888;
1535 break;
1536 case DP_COMPONENT_PIXEL_DEPTH_10BPC:
1537 *depth = COLOR_DEPTH_101010;
1538 break;
1539 case DP_COMPONENT_PIXEL_DEPTH_12BPC:
1540 *depth = COLOR_DEPTH_121212;
1541 break;
1542 case DP_COMPONENT_PIXEL_DEPTH_16BPC:
1543 *depth = COLOR_DEPTH_161616;
1544 break;
1545 default:
1546 *depth = COLOR_DEPTH_UNDEFINED;
1547 break;
1548 }
1549
1550 switch (hw_encoding) {
1551 case DP_PIXEL_ENCODING_TYPE_RGB444:
1552 *encoding = PIXEL_ENCODING_RGB;
1553 break;
1554 case DP_PIXEL_ENCODING_TYPE_YCBCR422:
1555 *encoding = PIXEL_ENCODING_YCBCR422;
1556 break;
1557 case DP_PIXEL_ENCODING_TYPE_YCBCR444:
1558 case DP_PIXEL_ENCODING_TYPE_Y_ONLY:
1559 *encoding = PIXEL_ENCODING_YCBCR444;
1560 break;
1561 case DP_PIXEL_ENCODING_TYPE_YCBCR420:
1562 *encoding = PIXEL_ENCODING_YCBCR420;
1563 break;
1564 default:
1565 *encoding = PIXEL_ENCODING_UNDEFINED;
1566 break;
1567 }
1568 return true;
1569 }
1570
1571 static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
1572 .dp_set_stream_attribute =
1573 enc1_stream_encoder_dp_set_stream_attribute,
1574 .hdmi_set_stream_attribute =
1575 enc1_stream_encoder_hdmi_set_stream_attribute,
1576 .dvi_set_stream_attribute =
1577 enc1_stream_encoder_dvi_set_stream_attribute,
1578 .set_throttled_vcp_size =
1579 enc1_stream_encoder_set_throttled_vcp_size,
1580 .update_hdmi_info_packets =
1581 enc1_stream_encoder_update_hdmi_info_packets,
1582 .stop_hdmi_info_packets =
1583 enc1_stream_encoder_stop_hdmi_info_packets,
1584 .update_dp_info_packets =
1585 enc1_stream_encoder_update_dp_info_packets,
1586 .send_immediate_sdp_message =
1587 enc1_stream_encoder_send_immediate_sdp_message,
1588 .stop_dp_info_packets =
1589 enc1_stream_encoder_stop_dp_info_packets,
1590 .dp_blank =
1591 enc1_stream_encoder_dp_blank,
1592 .dp_unblank =
1593 enc1_stream_encoder_dp_unblank,
1594 .audio_mute_control = enc1_se_audio_mute_control,
1595
1596 .dp_audio_setup = enc1_se_dp_audio_setup,
1597 .dp_audio_enable = enc1_se_dp_audio_enable,
1598 .dp_audio_disable = enc1_se_dp_audio_disable,
1599
1600 .hdmi_audio_setup = enc1_se_hdmi_audio_setup,
1601 .hdmi_audio_disable = enc1_se_hdmi_audio_disable,
1602 .setup_stereo_sync = enc1_setup_stereo_sync,
1603 .set_avmute = enc1_stream_encoder_set_avmute,
1604 .dig_connect_to_otg = enc1_dig_connect_to_otg,
1605 .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
1606 .dig_source_otg = enc1_dig_source_otg,
1607
1608 .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format,
1609 };
1610
dcn10_stream_encoder_construct(struct dcn10_stream_encoder * enc1,struct dc_context * ctx,struct dc_bios * bp,enum engine_id eng_id,const struct dcn10_stream_enc_registers * regs,const struct dcn10_stream_encoder_shift * se_shift,const struct dcn10_stream_encoder_mask * se_mask)1611 void dcn10_stream_encoder_construct(
1612 struct dcn10_stream_encoder *enc1,
1613 struct dc_context *ctx,
1614 struct dc_bios *bp,
1615 enum engine_id eng_id,
1616 const struct dcn10_stream_enc_registers *regs,
1617 const struct dcn10_stream_encoder_shift *se_shift,
1618 const struct dcn10_stream_encoder_mask *se_mask)
1619 {
1620 enc1->base.funcs = &dcn10_str_enc_funcs;
1621 enc1->base.ctx = ctx;
1622 enc1->base.id = eng_id;
1623 enc1->base.bp = bp;
1624 enc1->regs = regs;
1625 enc1->se_shift = se_shift;
1626 enc1->se_mask = se_mask;
1627 enc1->base.stream_enc_inst = eng_id - ENGINE_ID_DIGA;
1628 }
1629
1630