1 /*
2 * Performance events x86 architecture header
3 *
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
11 *
12 * For licencing details see kernel-base/COPYING
13 */
14
15 #include <linux/perf_event.h>
16
17 #include <asm/fpu/xstate.h>
18 #include <asm/intel_ds.h>
19 #include <asm/cpu.h>
20
21 /* To enable MSR tracing please use the generic trace points. */
22
23 /*
24 * | NHM/WSM | SNB |
25 * register -------------------------------
26 * | HT | no HT | HT | no HT |
27 *-----------------------------------------
28 * offcore | core | core | cpu | core |
29 * lbr_sel | core | core | cpu | core |
30 * ld_lat | cpu | core | cpu | core |
31 *-----------------------------------------
32 *
33 * Given that there is a small number of shared regs,
34 * we can pre-allocate their slot in the per-cpu
35 * per-core reg tables.
36 */
37 enum extra_reg_type {
38 EXTRA_REG_NONE = -1, /* not used */
39
40 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */
41 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */
42 EXTRA_REG_LBR = 2, /* lbr_select */
43 EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */
44 EXTRA_REG_FE = 4, /* fe_* */
45 EXTRA_REG_SNOOP_0 = 5, /* snoop response 0 */
46 EXTRA_REG_SNOOP_1 = 6, /* snoop response 1 */
47
48 EXTRA_REG_MAX /* number of entries needed */
49 };
50
51 struct event_constraint {
52 union {
53 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
54 u64 idxmsk64;
55 };
56 u64 code;
57 u64 cmask;
58 int weight;
59 int overlap;
60 int flags;
61 unsigned int size;
62 };
63
constraint_match(struct event_constraint * c,u64 ecode)64 static inline bool constraint_match(struct event_constraint *c, u64 ecode)
65 {
66 return ((ecode & c->cmask) - c->code) <= (u64)c->size;
67 }
68
69 #define PERF_ARCH(name, val) \
70 PERF_X86_EVENT_##name = val,
71
72 /*
73 * struct hw_perf_event.flags flags
74 */
75 enum {
76 #include "perf_event_flags.h"
77 };
78
79 #undef PERF_ARCH
80
81 #define PERF_ARCH(name, val) \
82 static_assert((PERF_X86_EVENT_##name & PERF_EVENT_FLAG_ARCH) == \
83 PERF_X86_EVENT_##name);
84
85 #include "perf_event_flags.h"
86
87 #undef PERF_ARCH
88
is_topdown_count(struct perf_event * event)89 static inline bool is_topdown_count(struct perf_event *event)
90 {
91 return event->hw.flags & PERF_X86_EVENT_TOPDOWN;
92 }
93
is_metric_event(struct perf_event * event)94 static inline bool is_metric_event(struct perf_event *event)
95 {
96 u64 config = event->attr.config;
97
98 return ((config & ARCH_PERFMON_EVENTSEL_EVENT) == 0) &&
99 ((config & INTEL_ARCH_EVENT_MASK) >= INTEL_TD_METRIC_RETIRING) &&
100 ((config & INTEL_ARCH_EVENT_MASK) <= INTEL_TD_METRIC_MAX);
101 }
102
is_slots_event(struct perf_event * event)103 static inline bool is_slots_event(struct perf_event *event)
104 {
105 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_TD_SLOTS;
106 }
107
is_topdown_event(struct perf_event * event)108 static inline bool is_topdown_event(struct perf_event *event)
109 {
110 return is_metric_event(event) || is_slots_event(event);
111 }
112
113 int is_x86_event(struct perf_event *event);
114
check_leader_group(struct perf_event * leader,int flags)115 static inline bool check_leader_group(struct perf_event *leader, int flags)
116 {
117 return is_x86_event(leader) ? !!(leader->hw.flags & flags) : false;
118 }
119
is_branch_counters_group(struct perf_event * event)120 static inline bool is_branch_counters_group(struct perf_event *event)
121 {
122 return check_leader_group(event->group_leader, PERF_X86_EVENT_BRANCH_COUNTERS);
123 }
124
125 struct amd_nb {
126 int nb_id; /* NorthBridge id */
127 int refcnt; /* reference count */
128 struct perf_event *owners[X86_PMC_IDX_MAX];
129 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
130 };
131
132 #define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1)
133 #define PEBS_PMI_AFTER_EACH_RECORD BIT_ULL(60)
134 #define PEBS_OUTPUT_OFFSET 61
135 #define PEBS_OUTPUT_MASK (3ull << PEBS_OUTPUT_OFFSET)
136 #define PEBS_OUTPUT_PT (1ull << PEBS_OUTPUT_OFFSET)
137 #define PEBS_VIA_PT_MASK (PEBS_OUTPUT_PT | PEBS_PMI_AFTER_EACH_RECORD)
138
139 /*
140 * Flags PEBS can handle without an PMI.
141 *
142 * TID can only be handled by flushing at context switch.
143 * REGS_USER can be handled for events limited to ring 3.
144 *
145 */
146 #define LARGE_PEBS_FLAGS \
147 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \
148 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \
149 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \
150 PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \
151 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \
152 PERF_SAMPLE_PERIOD | PERF_SAMPLE_CODE_PAGE_SIZE | \
153 PERF_SAMPLE_WEIGHT_TYPE)
154
155 #define PEBS_GP_REGS \
156 ((1ULL << PERF_REG_X86_AX) | \
157 (1ULL << PERF_REG_X86_BX) | \
158 (1ULL << PERF_REG_X86_CX) | \
159 (1ULL << PERF_REG_X86_DX) | \
160 (1ULL << PERF_REG_X86_DI) | \
161 (1ULL << PERF_REG_X86_SI) | \
162 (1ULL << PERF_REG_X86_SP) | \
163 (1ULL << PERF_REG_X86_BP) | \
164 (1ULL << PERF_REG_X86_IP) | \
165 (1ULL << PERF_REG_X86_FLAGS) | \
166 (1ULL << PERF_REG_X86_R8) | \
167 (1ULL << PERF_REG_X86_R9) | \
168 (1ULL << PERF_REG_X86_R10) | \
169 (1ULL << PERF_REG_X86_R11) | \
170 (1ULL << PERF_REG_X86_R12) | \
171 (1ULL << PERF_REG_X86_R13) | \
172 (1ULL << PERF_REG_X86_R14) | \
173 (1ULL << PERF_REG_X86_R15))
174
175 /*
176 * Per register state.
177 */
178 struct er_account {
179 raw_spinlock_t lock; /* per-core: protect structure */
180 u64 config; /* extra MSR config */
181 u64 reg; /* extra MSR number */
182 atomic_t ref; /* reference count */
183 };
184
185 /*
186 * Per core/cpu state
187 *
188 * Used to coordinate shared registers between HT threads or
189 * among events on a single PMU.
190 */
191 struct intel_shared_regs {
192 struct er_account regs[EXTRA_REG_MAX];
193 int refcnt; /* per-core: #HT threads */
194 unsigned core_id; /* per-core: core id */
195 };
196
197 enum intel_excl_state_type {
198 INTEL_EXCL_UNUSED = 0, /* counter is unused */
199 INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */
200 INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */
201 };
202
203 struct intel_excl_states {
204 enum intel_excl_state_type state[X86_PMC_IDX_MAX];
205 bool sched_started; /* true if scheduling has started */
206 };
207
208 struct intel_excl_cntrs {
209 raw_spinlock_t lock;
210
211 struct intel_excl_states states[2];
212
213 union {
214 u16 has_exclusive[2];
215 u32 exclusive_present;
216 };
217
218 int refcnt; /* per-core: #HT threads */
219 unsigned core_id; /* per-core: core id */
220 };
221
222 struct x86_perf_task_context;
223 #define MAX_LBR_ENTRIES 32
224
225 enum {
226 LBR_FORMAT_32 = 0x00,
227 LBR_FORMAT_LIP = 0x01,
228 LBR_FORMAT_EIP = 0x02,
229 LBR_FORMAT_EIP_FLAGS = 0x03,
230 LBR_FORMAT_EIP_FLAGS2 = 0x04,
231 LBR_FORMAT_INFO = 0x05,
232 LBR_FORMAT_TIME = 0x06,
233 LBR_FORMAT_INFO2 = 0x07,
234 LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_INFO2,
235 };
236
237 enum {
238 X86_PERF_KFREE_SHARED = 0,
239 X86_PERF_KFREE_EXCL = 1,
240 X86_PERF_KFREE_MAX
241 };
242
243 struct cpu_hw_events {
244 /*
245 * Generic x86 PMC bits
246 */
247 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
248 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
249 unsigned long dirty[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
250 int enabled;
251
252 int n_events; /* the # of events in the below arrays */
253 int n_added; /* the # last events in the below arrays;
254 they've never been enabled yet */
255 int n_txn; /* the # last events in the below arrays;
256 added in the current transaction */
257 int n_txn_pair;
258 int n_txn_metric;
259 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
260 u64 tags[X86_PMC_IDX_MAX];
261
262 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
263 struct event_constraint *event_constraint[X86_PMC_IDX_MAX];
264
265 int n_excl; /* the number of exclusive events */
266
267 unsigned int txn_flags;
268 int is_fake;
269
270 /*
271 * Intel DebugStore bits
272 */
273 struct debug_store *ds;
274 void *ds_pebs_vaddr;
275 void *ds_bts_vaddr;
276 u64 pebs_enabled;
277 int n_pebs;
278 int n_large_pebs;
279 int n_pebs_via_pt;
280 int pebs_output;
281
282 /* Current super set of events hardware configuration */
283 u64 pebs_data_cfg;
284 u64 active_pebs_data_cfg;
285 int pebs_record_size;
286
287 /* Intel Fixed counter configuration */
288 u64 fixed_ctrl_val;
289 u64 active_fixed_ctrl_val;
290
291 /*
292 * Intel LBR bits
293 */
294 int lbr_users;
295 int lbr_pebs_users;
296 struct perf_branch_stack lbr_stack;
297 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
298 u64 lbr_counters[MAX_LBR_ENTRIES]; /* branch stack extra */
299 union {
300 struct er_account *lbr_sel;
301 struct er_account *lbr_ctl;
302 };
303 u64 br_sel;
304 void *last_task_ctx;
305 int last_log_id;
306 int lbr_select;
307 void *lbr_xsave;
308
309 /*
310 * Intel host/guest exclude bits
311 */
312 u64 intel_ctrl_guest_mask;
313 u64 intel_ctrl_host_mask;
314 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX];
315
316 /*
317 * Intel checkpoint mask
318 */
319 u64 intel_cp_status;
320
321 /*
322 * manage shared (per-core, per-cpu) registers
323 * used on Intel NHM/WSM/SNB
324 */
325 struct intel_shared_regs *shared_regs;
326 /*
327 * manage exclusive counter access between hyperthread
328 */
329 struct event_constraint *constraint_list; /* in enable order */
330 struct intel_excl_cntrs *excl_cntrs;
331 int excl_thread_id; /* 0 or 1 */
332
333 /*
334 * SKL TSX_FORCE_ABORT shadow
335 */
336 u64 tfa_shadow;
337
338 /*
339 * Perf Metrics
340 */
341 /* number of accepted metrics events */
342 int n_metric;
343
344 /*
345 * AMD specific bits
346 */
347 struct amd_nb *amd_nb;
348 int brs_active; /* BRS is enabled */
349
350 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
351 u64 perf_ctr_virt_mask;
352 int n_pair; /* Large increment events */
353
354 void *kfree_on_online[X86_PERF_KFREE_MAX];
355
356 struct pmu *pmu;
357 };
358
359 #define __EVENT_CONSTRAINT_RANGE(c, e, n, m, w, o, f) { \
360 { .idxmsk64 = (n) }, \
361 .code = (c), \
362 .size = (e) - (c), \
363 .cmask = (m), \
364 .weight = (w), \
365 .overlap = (o), \
366 .flags = f, \
367 }
368
369 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) \
370 __EVENT_CONSTRAINT_RANGE(c, c, n, m, w, o, f)
371
372 #define EVENT_CONSTRAINT(c, n, m) \
373 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)
374
375 /*
376 * The constraint_match() function only works for 'simple' event codes
377 * and not for extended (AMD64_EVENTSEL_EVENT) events codes.
378 */
379 #define EVENT_CONSTRAINT_RANGE(c, e, n, m) \
380 __EVENT_CONSTRAINT_RANGE(c, e, n, m, HWEIGHT(n), 0, 0)
381
382 #define INTEL_EXCLEVT_CONSTRAINT(c, n) \
383 __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\
384 0, PERF_X86_EVENT_EXCL)
385
386 /*
387 * The overlap flag marks event constraints with overlapping counter
388 * masks. This is the case if the counter mask of such an event is not
389 * a subset of any other counter mask of a constraint with an equal or
390 * higher weight, e.g.:
391 *
392 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
393 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
394 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
395 *
396 * The event scheduler may not select the correct counter in the first
397 * cycle because it needs to know which subsequent events will be
398 * scheduled. It may fail to schedule the events then. So we set the
399 * overlap flag for such constraints to give the scheduler a hint which
400 * events to select for counter rescheduling.
401 *
402 * Care must be taken as the rescheduling algorithm is O(n!) which
403 * will increase scheduling cycles for an over-committed system
404 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros
405 * and its counter masks must be kept at a minimum.
406 */
407 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \
408 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0)
409
410 /*
411 * Constraint on the Event code.
412 */
413 #define INTEL_EVENT_CONSTRAINT(c, n) \
414 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
415
416 /*
417 * Constraint on a range of Event codes
418 */
419 #define INTEL_EVENT_CONSTRAINT_RANGE(c, e, n) \
420 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT)
421
422 /*
423 * Constraint on the Event code + UMask + fixed-mask
424 *
425 * filter mask to validate fixed counter events.
426 * the following filters disqualify for fixed counters:
427 * - inv
428 * - edge
429 * - cnt-mask
430 * - in_tx
431 * - in_tx_checkpointed
432 * The other filters are supported by fixed counters.
433 * The any-thread option is supported starting with v3.
434 */
435 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)
436 #define FIXED_EVENT_CONSTRAINT(c, n) \
437 EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS)
438
439 /*
440 * The special metric counters do not actually exist. They are calculated from
441 * the combination of the FxCtr3 + MSR_PERF_METRICS.
442 *
443 * The special metric counters are mapped to a dummy offset for the scheduler.
444 * The sharing between multiple users of the same metric without multiplexing
445 * is not allowed, even though the hardware supports that in principle.
446 */
447
448 #define METRIC_EVENT_CONSTRAINT(c, n) \
449 EVENT_CONSTRAINT(c, (1ULL << (INTEL_PMC_IDX_METRIC_BASE + n)), \
450 INTEL_ARCH_EVENT_MASK)
451
452 /*
453 * Constraint on the Event code + UMask
454 */
455 #define INTEL_UEVENT_CONSTRAINT(c, n) \
456 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
457
458 /* Constraint on specific umask bit only + event */
459 #define INTEL_UBIT_EVENT_CONSTRAINT(c, n) \
460 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c))
461
462 /* Like UEVENT_CONSTRAINT, but match flags too */
463 #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \
464 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
465
466 #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \
467 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
468 HWEIGHT(n), 0, PERF_X86_EVENT_EXCL)
469
470 #define INTEL_PLD_CONSTRAINT(c, n) \
471 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
472 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT)
473
474 #define INTEL_PSD_CONSTRAINT(c, n) \
475 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
476 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_STLAT)
477
478 #define INTEL_PST_CONSTRAINT(c, n) \
479 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
480 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST)
481
482 #define INTEL_HYBRID_LAT_CONSTRAINT(c, n) \
483 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
484 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID)
485
486 #define INTEL_HYBRID_LDLAT_CONSTRAINT(c, n) \
487 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
488 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID|PERF_X86_EVENT_PEBS_LD_HSW)
489
490 #define INTEL_HYBRID_STLAT_CONSTRAINT(c, n) \
491 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
492 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID|PERF_X86_EVENT_PEBS_ST_HSW)
493
494 /* Event constraint, but match on all event flags too. */
495 #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \
496 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS)
497
498 #define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \
499 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS)
500
501 /* Check only flags, but allow all event/umask */
502 #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \
503 EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS)
504
505 /* Check flags and event code, and set the HSW store flag */
506 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \
507 __EVENT_CONSTRAINT(code, n, \
508 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
509 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
510
511 /* Check flags and event code, and set the HSW load flag */
512 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \
513 __EVENT_CONSTRAINT(code, n, \
514 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
515 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
516
517 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(code, end, n) \
518 __EVENT_CONSTRAINT_RANGE(code, end, n, \
519 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
520 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
521
522 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \
523 __EVENT_CONSTRAINT(code, n, \
524 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
525 HWEIGHT(n), 0, \
526 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
527
528 /* Check flags and event code/umask, and set the HSW store flag */
529 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \
530 __EVENT_CONSTRAINT(code, n, \
531 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
532 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
533
534 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \
535 __EVENT_CONSTRAINT(code, n, \
536 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
537 HWEIGHT(n), 0, \
538 PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL)
539
540 /* Check flags and event code/umask, and set the HSW load flag */
541 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \
542 __EVENT_CONSTRAINT(code, n, \
543 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
544 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
545
546 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \
547 __EVENT_CONSTRAINT(code, n, \
548 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
549 HWEIGHT(n), 0, \
550 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
551
552 /* Check flags and event code/umask, and set the HSW N/A flag */
553 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \
554 __EVENT_CONSTRAINT(code, n, \
555 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
556 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW)
557
558
559 /*
560 * We define the end marker as having a weight of -1
561 * to enable blacklisting of events using a counter bitmask
562 * of zero and thus a weight of zero.
563 * The end marker has a weight that cannot possibly be
564 * obtained from counting the bits in the bitmask.
565 */
566 #define EVENT_CONSTRAINT_END { .weight = -1 }
567
568 /*
569 * Check for end marker with weight == -1
570 */
571 #define for_each_event_constraint(e, c) \
572 for ((e) = (c); (e)->weight != -1; (e)++)
573
574 /*
575 * Extra registers for specific events.
576 *
577 * Some events need large masks and require external MSRs.
578 * Those extra MSRs end up being shared for all events on
579 * a PMU and sometimes between PMU of sibling HT threads.
580 * In either case, the kernel needs to handle conflicting
581 * accesses to those extra, shared, regs. The data structure
582 * to manage those registers is stored in cpu_hw_event.
583 */
584 struct extra_reg {
585 unsigned int event;
586 unsigned int msr;
587 u64 config_mask;
588 u64 valid_mask;
589 int idx; /* per_xxx->regs[] reg index */
590 bool extra_msr_access;
591 };
592
593 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
594 .event = (e), \
595 .msr = (ms), \
596 .config_mask = (m), \
597 .valid_mask = (vm), \
598 .idx = EXTRA_REG_##i, \
599 .extra_msr_access = true, \
600 }
601
602 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
603 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
604
605 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \
606 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \
607 ARCH_PERFMON_EVENTSEL_UMASK, vm, idx)
608
609 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \
610 INTEL_UEVENT_EXTRA_REG(c, \
611 MSR_PEBS_LD_LAT_THRESHOLD, \
612 0xffff, \
613 LDLAT)
614
615 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
616
617 union perf_capabilities {
618 struct {
619 u64 lbr_format:6;
620 u64 pebs_trap:1;
621 u64 pebs_arch_reg:1;
622 u64 pebs_format:4;
623 u64 smm_freeze:1;
624 /*
625 * PMU supports separate counter range for writing
626 * values > 32bit.
627 */
628 u64 full_width_write:1;
629 u64 pebs_baseline:1;
630 u64 perf_metrics:1;
631 u64 pebs_output_pt_available:1;
632 u64 pebs_timing_info:1;
633 u64 anythread_deprecated:1;
634 };
635 u64 capabilities;
636 };
637
638 struct x86_pmu_quirk {
639 struct x86_pmu_quirk *next;
640 void (*func)(void);
641 };
642
643 union x86_pmu_config {
644 struct {
645 u64 event:8,
646 umask:8,
647 usr:1,
648 os:1,
649 edge:1,
650 pc:1,
651 interrupt:1,
652 __reserved1:1,
653 en:1,
654 inv:1,
655 cmask:8,
656 event2:4,
657 __reserved2:4,
658 go:1,
659 ho:1;
660 } bits;
661 u64 value;
662 };
663
664 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value
665
666 enum {
667 x86_lbr_exclusive_lbr,
668 x86_lbr_exclusive_bts,
669 x86_lbr_exclusive_pt,
670 x86_lbr_exclusive_max,
671 };
672
673 #define PERF_PEBS_DATA_SOURCE_MAX 0x100
674 #define PERF_PEBS_DATA_SOURCE_MASK (PERF_PEBS_DATA_SOURCE_MAX - 1)
675 #define PERF_PEBS_DATA_SOURCE_GRT_MAX 0x10
676 #define PERF_PEBS_DATA_SOURCE_GRT_MASK (PERF_PEBS_DATA_SOURCE_GRT_MAX - 1)
677
678 enum hybrid_cpu_type {
679 HYBRID_INTEL_NONE,
680 HYBRID_INTEL_ATOM = 0x20,
681 HYBRID_INTEL_CORE = 0x40,
682 };
683
684 enum hybrid_pmu_type {
685 not_hybrid,
686 hybrid_small = BIT(0),
687 hybrid_big = BIT(1),
688
689 hybrid_big_small = hybrid_big | hybrid_small, /* only used for matching */
690 };
691
692 #define X86_HYBRID_PMU_ATOM_IDX 0
693 #define X86_HYBRID_PMU_CORE_IDX 1
694
695 #define X86_HYBRID_NUM_PMUS 2
696
697 struct x86_hybrid_pmu {
698 struct pmu pmu;
699 const char *name;
700 enum hybrid_pmu_type pmu_type;
701 cpumask_t supported_cpus;
702 union perf_capabilities intel_cap;
703 u64 intel_ctrl;
704 u64 pebs_events_mask;
705 u64 config_mask;
706 union {
707 u64 cntr_mask64;
708 unsigned long cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
709 };
710 union {
711 u64 fixed_cntr_mask64;
712 unsigned long fixed_cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
713 };
714 struct event_constraint unconstrained;
715
716 u64 hw_cache_event_ids
717 [PERF_COUNT_HW_CACHE_MAX]
718 [PERF_COUNT_HW_CACHE_OP_MAX]
719 [PERF_COUNT_HW_CACHE_RESULT_MAX];
720 u64 hw_cache_extra_regs
721 [PERF_COUNT_HW_CACHE_MAX]
722 [PERF_COUNT_HW_CACHE_OP_MAX]
723 [PERF_COUNT_HW_CACHE_RESULT_MAX];
724 struct event_constraint *event_constraints;
725 struct event_constraint *pebs_constraints;
726 struct extra_reg *extra_regs;
727
728 unsigned int late_ack :1,
729 mid_ack :1,
730 enabled_ack :1;
731
732 u64 pebs_data_source[PERF_PEBS_DATA_SOURCE_MAX];
733 };
734
hybrid_pmu(struct pmu * pmu)735 static __always_inline struct x86_hybrid_pmu *hybrid_pmu(struct pmu *pmu)
736 {
737 return container_of(pmu, struct x86_hybrid_pmu, pmu);
738 }
739
740 extern struct static_key_false perf_is_hybrid;
741 #define is_hybrid() static_branch_unlikely(&perf_is_hybrid)
742
743 #define hybrid(_pmu, _field) \
744 (*({ \
745 typeof(&x86_pmu._field) __Fp = &x86_pmu._field; \
746 \
747 if (is_hybrid() && (_pmu)) \
748 __Fp = &hybrid_pmu(_pmu)->_field; \
749 \
750 __Fp; \
751 }))
752
753 #define hybrid_var(_pmu, _var) \
754 (*({ \
755 typeof(&_var) __Fp = &_var; \
756 \
757 if (is_hybrid() && (_pmu)) \
758 __Fp = &hybrid_pmu(_pmu)->_var; \
759 \
760 __Fp; \
761 }))
762
763 #define hybrid_bit(_pmu, _field) \
764 ({ \
765 bool __Fp = x86_pmu._field; \
766 \
767 if (is_hybrid() && (_pmu)) \
768 __Fp = hybrid_pmu(_pmu)->_field; \
769 \
770 __Fp; \
771 })
772
773 /*
774 * struct x86_pmu - generic x86 pmu
775 */
776 struct x86_pmu {
777 /*
778 * Generic x86 PMC bits
779 */
780 const char *name;
781 int version;
782 int (*handle_irq)(struct pt_regs *);
783 void (*disable_all)(void);
784 void (*enable_all)(int added);
785 void (*enable)(struct perf_event *);
786 void (*disable)(struct perf_event *);
787 void (*assign)(struct perf_event *event, int idx);
788 void (*add)(struct perf_event *);
789 void (*del)(struct perf_event *);
790 void (*read)(struct perf_event *event);
791 int (*set_period)(struct perf_event *event);
792 u64 (*update)(struct perf_event *event);
793 int (*hw_config)(struct perf_event *event);
794 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
795 unsigned eventsel;
796 unsigned perfctr;
797 unsigned fixedctr;
798 int (*addr_offset)(int index, bool eventsel);
799 int (*rdpmc_index)(int index);
800 u64 (*event_map)(int);
801 int max_events;
802 u64 config_mask;
803 union {
804 u64 cntr_mask64;
805 unsigned long cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
806 };
807 union {
808 u64 fixed_cntr_mask64;
809 unsigned long fixed_cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
810 };
811 int cntval_bits;
812 u64 cntval_mask;
813 union {
814 unsigned long events_maskl;
815 unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)];
816 };
817 int events_mask_len;
818 int apic;
819 u64 max_period;
820 struct event_constraint *
821 (*get_event_constraints)(struct cpu_hw_events *cpuc,
822 int idx,
823 struct perf_event *event);
824
825 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
826 struct perf_event *event);
827
828 void (*start_scheduling)(struct cpu_hw_events *cpuc);
829
830 void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr);
831
832 void (*stop_scheduling)(struct cpu_hw_events *cpuc);
833
834 struct event_constraint *event_constraints;
835 struct x86_pmu_quirk *quirks;
836 void (*limit_period)(struct perf_event *event, s64 *l);
837
838 /* PMI handler bits */
839 unsigned int late_ack :1,
840 mid_ack :1,
841 enabled_ack :1;
842 /*
843 * sysfs attrs
844 */
845 int attr_rdpmc_broken;
846 int attr_rdpmc;
847 struct attribute **format_attrs;
848
849 ssize_t (*events_sysfs_show)(char *page, u64 config);
850 const struct attribute_group **attr_update;
851
852 unsigned long attr_freeze_on_smi;
853
854 /*
855 * CPU Hotplug hooks
856 */
857 int (*cpu_prepare)(int cpu);
858 void (*cpu_starting)(int cpu);
859 void (*cpu_dying)(int cpu);
860 void (*cpu_dead)(int cpu);
861
862 void (*check_microcode)(void);
863 void (*sched_task)(struct perf_event_pmu_context *pmu_ctx,
864 bool sched_in);
865
866 /*
867 * Intel Arch Perfmon v2+
868 */
869 u64 intel_ctrl;
870 union perf_capabilities intel_cap;
871
872 /*
873 * Intel DebugStore bits
874 */
875 unsigned int bts :1,
876 bts_active :1,
877 pebs :1,
878 pebs_active :1,
879 pebs_broken :1,
880 pebs_prec_dist :1,
881 pebs_no_tlb :1,
882 pebs_no_isolation :1,
883 pebs_block :1,
884 pebs_ept :1;
885 int pebs_record_size;
886 int pebs_buffer_size;
887 u64 pebs_events_mask;
888 void (*drain_pebs)(struct pt_regs *regs, struct perf_sample_data *data);
889 struct event_constraint *pebs_constraints;
890 void (*pebs_aliases)(struct perf_event *event);
891 u64 (*pebs_latency_data)(struct perf_event *event, u64 status);
892 unsigned long large_pebs_flags;
893 u64 rtm_abort_event;
894 u64 pebs_capable;
895
896 /*
897 * Intel LBR
898 */
899 unsigned int lbr_tos, lbr_from, lbr_to,
900 lbr_info, lbr_nr; /* LBR base regs and size */
901 union {
902 u64 lbr_sel_mask; /* LBR_SELECT valid bits */
903 u64 lbr_ctl_mask; /* LBR_CTL valid bits */
904 };
905 union {
906 const int *lbr_sel_map; /* lbr_select mappings */
907 int *lbr_ctl_map; /* LBR_CTL mappings */
908 };
909 bool lbr_double_abort; /* duplicated lbr aborts */
910 bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */
911
912 unsigned int lbr_has_info:1;
913 unsigned int lbr_has_tsx:1;
914 unsigned int lbr_from_flags:1;
915 unsigned int lbr_to_cycles:1;
916
917 /*
918 * Intel Architectural LBR CPUID Enumeration
919 */
920 unsigned int lbr_depth_mask:8;
921 unsigned int lbr_deep_c_reset:1;
922 unsigned int lbr_lip:1;
923 unsigned int lbr_cpl:1;
924 unsigned int lbr_filter:1;
925 unsigned int lbr_call_stack:1;
926 unsigned int lbr_mispred:1;
927 unsigned int lbr_timed_lbr:1;
928 unsigned int lbr_br_type:1;
929 unsigned int lbr_counters:4;
930
931 void (*lbr_reset)(void);
932 void (*lbr_read)(struct cpu_hw_events *cpuc);
933 void (*lbr_save)(void *ctx);
934 void (*lbr_restore)(void *ctx);
935
936 /*
937 * Intel PT/LBR/BTS are exclusive
938 */
939 atomic_t lbr_exclusive[x86_lbr_exclusive_max];
940
941 /*
942 * Intel perf metrics
943 */
944 int num_topdown_events;
945
946 /*
947 * perf task context (i.e. struct perf_event_pmu_context::task_ctx_data)
948 * switch helper to bridge calls from perf/core to perf/x86.
949 * See struct pmu::swap_task_ctx() usage for examples;
950 */
951 void (*swap_task_ctx)(struct perf_event_pmu_context *prev_epc,
952 struct perf_event_pmu_context *next_epc);
953
954 /*
955 * AMD bits
956 */
957 unsigned int amd_nb_constraints : 1;
958 u64 perf_ctr_pair_en;
959
960 /*
961 * Extra registers for events
962 */
963 struct extra_reg *extra_regs;
964 unsigned int flags;
965
966 /*
967 * Intel host/guest support (KVM)
968 */
969 struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr, void *data);
970
971 /*
972 * Check period value for PERF_EVENT_IOC_PERIOD ioctl.
973 */
974 int (*check_period) (struct perf_event *event, u64 period);
975
976 int (*aux_output_match) (struct perf_event *event);
977
978 void (*filter)(struct pmu *pmu, int cpu, bool *ret);
979 /*
980 * Hybrid support
981 *
982 * Most PMU capabilities are the same among different hybrid PMUs.
983 * The global x86_pmu saves the architecture capabilities, which
984 * are available for all PMUs. The hybrid_pmu only includes the
985 * unique capabilities.
986 */
987 int num_hybrid_pmus;
988 struct x86_hybrid_pmu *hybrid_pmu;
989 enum hybrid_cpu_type (*get_hybrid_cpu_type) (void);
990 };
991
992 struct x86_perf_task_context_opt {
993 int lbr_callstack_users;
994 int lbr_stack_state;
995 int log_id;
996 };
997
998 struct x86_perf_task_context {
999 u64 lbr_sel;
1000 int tos;
1001 int valid_lbrs;
1002 struct x86_perf_task_context_opt opt;
1003 struct lbr_entry lbr[MAX_LBR_ENTRIES];
1004 };
1005
1006 struct x86_perf_task_context_arch_lbr {
1007 struct x86_perf_task_context_opt opt;
1008 struct lbr_entry entries[];
1009 };
1010
1011 /*
1012 * Add padding to guarantee the 64-byte alignment of the state buffer.
1013 *
1014 * The structure is dynamically allocated. The size of the LBR state may vary
1015 * based on the number of LBR registers.
1016 *
1017 * Do not put anything after the LBR state.
1018 */
1019 struct x86_perf_task_context_arch_lbr_xsave {
1020 struct x86_perf_task_context_opt opt;
1021
1022 union {
1023 struct xregs_state xsave;
1024 struct {
1025 struct fxregs_state i387;
1026 struct xstate_header header;
1027 struct arch_lbr_state lbr;
1028 } __attribute__ ((packed, aligned (XSAVE_ALIGNMENT)));
1029 };
1030 };
1031
1032 #define x86_add_quirk(func_) \
1033 do { \
1034 static struct x86_pmu_quirk __quirk __initdata = { \
1035 .func = func_, \
1036 }; \
1037 __quirk.next = x86_pmu.quirks; \
1038 x86_pmu.quirks = &__quirk; \
1039 } while (0)
1040
1041 /*
1042 * x86_pmu flags
1043 */
1044 #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */
1045 #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */
1046 #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */
1047 #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */
1048 #define PMU_FL_PEBS_ALL 0x10 /* all events are valid PEBS events */
1049 #define PMU_FL_TFA 0x20 /* deal with TSX force abort */
1050 #define PMU_FL_PAIR 0x40 /* merge counters for large incr. events */
1051 #define PMU_FL_INSTR_LATENCY 0x80 /* Support Instruction Latency in PEBS Memory Info Record */
1052 #define PMU_FL_MEM_LOADS_AUX 0x100 /* Require an auxiliary event for the complete memory info */
1053 #define PMU_FL_RETIRE_LATENCY 0x200 /* Support Retire Latency in PEBS */
1054 #define PMU_FL_BR_CNTR 0x400 /* Support branch counter logging */
1055
1056 #define EVENT_VAR(_id) event_attr_##_id
1057 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr
1058
1059 #define EVENT_ATTR(_name, _id) \
1060 static struct perf_pmu_events_attr EVENT_VAR(_id) = { \
1061 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
1062 .id = PERF_COUNT_HW_##_id, \
1063 .event_str = NULL, \
1064 };
1065
1066 #define EVENT_ATTR_STR(_name, v, str) \
1067 static struct perf_pmu_events_attr event_attr_##v = { \
1068 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
1069 .id = 0, \
1070 .event_str = str, \
1071 };
1072
1073 #define EVENT_ATTR_STR_HT(_name, v, noht, ht) \
1074 static struct perf_pmu_events_ht_attr event_attr_##v = { \
1075 .attr = __ATTR(_name, 0444, events_ht_sysfs_show, NULL),\
1076 .id = 0, \
1077 .event_str_noht = noht, \
1078 .event_str_ht = ht, \
1079 }
1080
1081 #define EVENT_ATTR_STR_HYBRID(_name, v, str, _pmu) \
1082 static struct perf_pmu_events_hybrid_attr event_attr_##v = { \
1083 .attr = __ATTR(_name, 0444, events_hybrid_sysfs_show, NULL),\
1084 .id = 0, \
1085 .event_str = str, \
1086 .pmu_type = _pmu, \
1087 }
1088
1089 #define FORMAT_HYBRID_PTR(_id) (&format_attr_hybrid_##_id.attr.attr)
1090
1091 #define FORMAT_ATTR_HYBRID(_name, _pmu) \
1092 static struct perf_pmu_format_hybrid_attr format_attr_hybrid_##_name = {\
1093 .attr = __ATTR_RO(_name), \
1094 .pmu_type = _pmu, \
1095 }
1096
1097 struct pmu *x86_get_pmu(unsigned int cpu);
1098 extern struct x86_pmu x86_pmu __read_mostly;
1099
1100 DECLARE_STATIC_CALL(x86_pmu_set_period, *x86_pmu.set_period);
1101 DECLARE_STATIC_CALL(x86_pmu_update, *x86_pmu.update);
1102 DECLARE_STATIC_CALL(x86_pmu_drain_pebs, *x86_pmu.drain_pebs);
1103
task_context_opt(void * ctx)1104 static __always_inline struct x86_perf_task_context_opt *task_context_opt(void *ctx)
1105 {
1106 if (static_cpu_has(X86_FEATURE_ARCH_LBR))
1107 return &((struct x86_perf_task_context_arch_lbr *)ctx)->opt;
1108
1109 return &((struct x86_perf_task_context *)ctx)->opt;
1110 }
1111
x86_pmu_has_lbr_callstack(void)1112 static inline bool x86_pmu_has_lbr_callstack(void)
1113 {
1114 return x86_pmu.lbr_sel_map &&
1115 x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0;
1116 }
1117
1118 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
1119 DECLARE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1120
1121 int x86_perf_event_set_period(struct perf_event *event);
1122
1123 /*
1124 * Generalized hw caching related hw_event table, filled
1125 * in on a per model basis. A value of 0 means
1126 * 'not supported', -1 means 'hw_event makes no sense on
1127 * this CPU', any other value means the raw hw_event
1128 * ID.
1129 */
1130
1131 #define C(x) PERF_COUNT_HW_CACHE_##x
1132
1133 extern u64 __read_mostly hw_cache_event_ids
1134 [PERF_COUNT_HW_CACHE_MAX]
1135 [PERF_COUNT_HW_CACHE_OP_MAX]
1136 [PERF_COUNT_HW_CACHE_RESULT_MAX];
1137 extern u64 __read_mostly hw_cache_extra_regs
1138 [PERF_COUNT_HW_CACHE_MAX]
1139 [PERF_COUNT_HW_CACHE_OP_MAX]
1140 [PERF_COUNT_HW_CACHE_RESULT_MAX];
1141
1142 u64 x86_perf_event_update(struct perf_event *event);
1143
x86_pmu_config_addr(int index)1144 static inline unsigned int x86_pmu_config_addr(int index)
1145 {
1146 return x86_pmu.eventsel + (x86_pmu.addr_offset ?
1147 x86_pmu.addr_offset(index, true) : index);
1148 }
1149
x86_pmu_event_addr(int index)1150 static inline unsigned int x86_pmu_event_addr(int index)
1151 {
1152 return x86_pmu.perfctr + (x86_pmu.addr_offset ?
1153 x86_pmu.addr_offset(index, false) : index);
1154 }
1155
x86_pmu_fixed_ctr_addr(int index)1156 static inline unsigned int x86_pmu_fixed_ctr_addr(int index)
1157 {
1158 return x86_pmu.fixedctr + (x86_pmu.addr_offset ?
1159 x86_pmu.addr_offset(index, false) : index);
1160 }
1161
x86_pmu_rdpmc_index(int index)1162 static inline int x86_pmu_rdpmc_index(int index)
1163 {
1164 return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index;
1165 }
1166
1167 bool check_hw_exists(struct pmu *pmu, unsigned long *cntr_mask,
1168 unsigned long *fixed_cntr_mask);
1169
1170 int x86_add_exclusive(unsigned int what);
1171
1172 void x86_del_exclusive(unsigned int what);
1173
1174 int x86_reserve_hardware(void);
1175
1176 void x86_release_hardware(void);
1177
1178 int x86_pmu_max_precise(void);
1179
1180 void hw_perf_lbr_event_destroy(struct perf_event *event);
1181
1182 int x86_setup_perfctr(struct perf_event *event);
1183
1184 int x86_pmu_hw_config(struct perf_event *event);
1185
1186 void x86_pmu_disable_all(void);
1187
has_amd_brs(struct hw_perf_event * hwc)1188 static inline bool has_amd_brs(struct hw_perf_event *hwc)
1189 {
1190 return hwc->flags & PERF_X86_EVENT_AMD_BRS;
1191 }
1192
is_counter_pair(struct hw_perf_event * hwc)1193 static inline bool is_counter_pair(struct hw_perf_event *hwc)
1194 {
1195 return hwc->flags & PERF_X86_EVENT_PAIR;
1196 }
1197
__x86_pmu_enable_event(struct hw_perf_event * hwc,u64 enable_mask)1198 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
1199 u64 enable_mask)
1200 {
1201 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
1202
1203 if (hwc->extra_reg.reg)
1204 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
1205
1206 /*
1207 * Add enabled Merge event on next counter
1208 * if large increment event being enabled on this counter
1209 */
1210 if (is_counter_pair(hwc))
1211 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en);
1212
1213 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
1214 }
1215
1216 void x86_pmu_enable_all(int added);
1217
1218 int perf_assign_events(struct event_constraint **constraints, int n,
1219 int wmin, int wmax, int gpmax, int *assign);
1220 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);
1221
1222 void x86_pmu_stop(struct perf_event *event, int flags);
1223
x86_pmu_disable_event(struct perf_event * event)1224 static inline void x86_pmu_disable_event(struct perf_event *event)
1225 {
1226 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
1227 struct hw_perf_event *hwc = &event->hw;
1228
1229 wrmsrl(hwc->config_base, hwc->config & ~disable_mask);
1230
1231 if (is_counter_pair(hwc))
1232 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), 0);
1233 }
1234
1235 void x86_pmu_enable_event(struct perf_event *event);
1236
1237 int x86_pmu_handle_irq(struct pt_regs *regs);
1238
1239 void x86_pmu_show_pmu_cap(struct pmu *pmu);
1240
x86_pmu_num_counters(struct pmu * pmu)1241 static inline int x86_pmu_num_counters(struct pmu *pmu)
1242 {
1243 return hweight64(hybrid(pmu, cntr_mask64));
1244 }
1245
x86_pmu_max_num_counters(struct pmu * pmu)1246 static inline int x86_pmu_max_num_counters(struct pmu *pmu)
1247 {
1248 return fls64(hybrid(pmu, cntr_mask64));
1249 }
1250
x86_pmu_num_counters_fixed(struct pmu * pmu)1251 static inline int x86_pmu_num_counters_fixed(struct pmu *pmu)
1252 {
1253 return hweight64(hybrid(pmu, fixed_cntr_mask64));
1254 }
1255
x86_pmu_max_num_counters_fixed(struct pmu * pmu)1256 static inline int x86_pmu_max_num_counters_fixed(struct pmu *pmu)
1257 {
1258 return fls64(hybrid(pmu, fixed_cntr_mask64));
1259 }
1260
x86_pmu_get_event_config(struct perf_event * event)1261 static inline u64 x86_pmu_get_event_config(struct perf_event *event)
1262 {
1263 return event->attr.config & hybrid(event->pmu, config_mask);
1264 }
1265
1266 extern struct event_constraint emptyconstraint;
1267
1268 extern struct event_constraint unconstrained;
1269
kernel_ip(unsigned long ip)1270 static inline bool kernel_ip(unsigned long ip)
1271 {
1272 #ifdef CONFIG_X86_32
1273 return ip > PAGE_OFFSET;
1274 #else
1275 return (long)ip < 0;
1276 #endif
1277 }
1278
1279 /*
1280 * Not all PMUs provide the right context information to place the reported IP
1281 * into full context. Specifically segment registers are typically not
1282 * supplied.
1283 *
1284 * Assuming the address is a linear address (it is for IBS), we fake the CS and
1285 * vm86 mode using the known zero-based code segment and 'fix up' the registers
1286 * to reflect this.
1287 *
1288 * Intel PEBS/LBR appear to typically provide the effective address, nothing
1289 * much we can do about that but pray and treat it like a linear address.
1290 */
set_linear_ip(struct pt_regs * regs,unsigned long ip)1291 static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip)
1292 {
1293 regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS;
1294 if (regs->flags & X86_VM_MASK)
1295 regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK);
1296 regs->ip = ip;
1297 }
1298
1299 /*
1300 * x86control flow change classification
1301 * x86control flow changes include branches, interrupts, traps, faults
1302 */
1303 enum {
1304 X86_BR_NONE = 0, /* unknown */
1305
1306 X86_BR_USER = 1 << 0, /* branch target is user */
1307 X86_BR_KERNEL = 1 << 1, /* branch target is kernel */
1308
1309 X86_BR_CALL = 1 << 2, /* call */
1310 X86_BR_RET = 1 << 3, /* return */
1311 X86_BR_SYSCALL = 1 << 4, /* syscall */
1312 X86_BR_SYSRET = 1 << 5, /* syscall return */
1313 X86_BR_INT = 1 << 6, /* sw interrupt */
1314 X86_BR_IRET = 1 << 7, /* return from interrupt */
1315 X86_BR_JCC = 1 << 8, /* conditional */
1316 X86_BR_JMP = 1 << 9, /* jump */
1317 X86_BR_IRQ = 1 << 10,/* hw interrupt or trap or fault */
1318 X86_BR_IND_CALL = 1 << 11,/* indirect calls */
1319 X86_BR_ABORT = 1 << 12,/* transaction abort */
1320 X86_BR_IN_TX = 1 << 13,/* in transaction */
1321 X86_BR_NO_TX = 1 << 14,/* not in transaction */
1322 X86_BR_ZERO_CALL = 1 << 15,/* zero length call */
1323 X86_BR_CALL_STACK = 1 << 16,/* call stack */
1324 X86_BR_IND_JMP = 1 << 17,/* indirect jump */
1325
1326 X86_BR_TYPE_SAVE = 1 << 18,/* indicate to save branch type */
1327
1328 };
1329
1330 #define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL)
1331 #define X86_BR_ANYTX (X86_BR_NO_TX | X86_BR_IN_TX)
1332
1333 #define X86_BR_ANY \
1334 (X86_BR_CALL |\
1335 X86_BR_RET |\
1336 X86_BR_SYSCALL |\
1337 X86_BR_SYSRET |\
1338 X86_BR_INT |\
1339 X86_BR_IRET |\
1340 X86_BR_JCC |\
1341 X86_BR_JMP |\
1342 X86_BR_IRQ |\
1343 X86_BR_ABORT |\
1344 X86_BR_IND_CALL |\
1345 X86_BR_IND_JMP |\
1346 X86_BR_ZERO_CALL)
1347
1348 #define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY)
1349
1350 #define X86_BR_ANY_CALL \
1351 (X86_BR_CALL |\
1352 X86_BR_IND_CALL |\
1353 X86_BR_ZERO_CALL |\
1354 X86_BR_SYSCALL |\
1355 X86_BR_IRQ |\
1356 X86_BR_INT)
1357
1358 int common_branch_type(int type);
1359 int branch_type(unsigned long from, unsigned long to, int abort);
1360 int branch_type_fused(unsigned long from, unsigned long to, int abort,
1361 int *offset);
1362
1363 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event);
1364 ssize_t intel_event_sysfs_show(char *page, u64 config);
1365
1366 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
1367 char *page);
1368 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1369 char *page);
1370 ssize_t events_hybrid_sysfs_show(struct device *dev,
1371 struct device_attribute *attr,
1372 char *page);
1373
fixed_counter_disabled(int i,struct pmu * pmu)1374 static inline bool fixed_counter_disabled(int i, struct pmu *pmu)
1375 {
1376 u64 intel_ctrl = hybrid(pmu, intel_ctrl);
1377
1378 return !(intel_ctrl >> (i + INTEL_PMC_IDX_FIXED));
1379 }
1380
1381 #ifdef CONFIG_CPU_SUP_AMD
1382
1383 int amd_pmu_init(void);
1384
1385 int amd_pmu_lbr_init(void);
1386 void amd_pmu_lbr_reset(void);
1387 void amd_pmu_lbr_read(void);
1388 void amd_pmu_lbr_add(struct perf_event *event);
1389 void amd_pmu_lbr_del(struct perf_event *event);
1390 void amd_pmu_lbr_sched_task(struct perf_event_pmu_context *pmu_ctx, bool sched_in);
1391 void amd_pmu_lbr_enable_all(void);
1392 void amd_pmu_lbr_disable_all(void);
1393 int amd_pmu_lbr_hw_config(struct perf_event *event);
1394
__amd_pmu_lbr_disable(void)1395 static __always_inline void __amd_pmu_lbr_disable(void)
1396 {
1397 u64 dbg_ctl, dbg_extn_cfg;
1398
1399 rdmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg);
1400 wrmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg & ~DBG_EXTN_CFG_LBRV2EN);
1401
1402 if (cpu_feature_enabled(X86_FEATURE_AMD_LBR_PMC_FREEZE)) {
1403 rdmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl);
1404 wrmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl & ~DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
1405 }
1406 }
1407
1408 #ifdef CONFIG_PERF_EVENTS_AMD_BRS
1409
1410 #define AMD_FAM19H_BRS_EVENT 0xc4 /* RETIRED_TAKEN_BRANCH_INSTRUCTIONS */
1411
1412 int amd_brs_init(void);
1413 void amd_brs_disable(void);
1414 void amd_brs_enable(void);
1415 void amd_brs_enable_all(void);
1416 void amd_brs_disable_all(void);
1417 void amd_brs_drain(void);
1418 void amd_brs_lopwr_init(void);
1419 int amd_brs_hw_config(struct perf_event *event);
1420 void amd_brs_reset(void);
1421
amd_pmu_brs_add(struct perf_event * event)1422 static inline void amd_pmu_brs_add(struct perf_event *event)
1423 {
1424 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1425
1426 perf_sched_cb_inc(event->pmu);
1427 cpuc->lbr_users++;
1428 /*
1429 * No need to reset BRS because it is reset
1430 * on brs_enable() and it is saturating
1431 */
1432 }
1433
amd_pmu_brs_del(struct perf_event * event)1434 static inline void amd_pmu_brs_del(struct perf_event *event)
1435 {
1436 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1437
1438 cpuc->lbr_users--;
1439 WARN_ON_ONCE(cpuc->lbr_users < 0);
1440
1441 perf_sched_cb_dec(event->pmu);
1442 }
1443
1444 void amd_pmu_brs_sched_task(struct perf_event_pmu_context *pmu_ctx, bool sched_in);
1445 #else
amd_brs_init(void)1446 static inline int amd_brs_init(void)
1447 {
1448 return 0;
1449 }
amd_brs_disable(void)1450 static inline void amd_brs_disable(void) {}
amd_brs_enable(void)1451 static inline void amd_brs_enable(void) {}
amd_brs_drain(void)1452 static inline void amd_brs_drain(void) {}
amd_brs_lopwr_init(void)1453 static inline void amd_brs_lopwr_init(void) {}
amd_brs_disable_all(void)1454 static inline void amd_brs_disable_all(void) {}
amd_brs_hw_config(struct perf_event * event)1455 static inline int amd_brs_hw_config(struct perf_event *event)
1456 {
1457 return 0;
1458 }
amd_brs_reset(void)1459 static inline void amd_brs_reset(void) {}
1460
amd_pmu_brs_add(struct perf_event * event)1461 static inline void amd_pmu_brs_add(struct perf_event *event)
1462 {
1463 }
1464
amd_pmu_brs_del(struct perf_event * event)1465 static inline void amd_pmu_brs_del(struct perf_event *event)
1466 {
1467 }
1468
amd_pmu_brs_sched_task(struct perf_event_pmu_context * pmu_ctx,bool sched_in)1469 static inline void amd_pmu_brs_sched_task(struct perf_event_pmu_context *pmu_ctx, bool sched_in)
1470 {
1471 }
1472
amd_brs_enable_all(void)1473 static inline void amd_brs_enable_all(void)
1474 {
1475 }
1476
1477 #endif
1478
1479 #else /* CONFIG_CPU_SUP_AMD */
1480
amd_pmu_init(void)1481 static inline int amd_pmu_init(void)
1482 {
1483 return 0;
1484 }
1485
amd_brs_init(void)1486 static inline int amd_brs_init(void)
1487 {
1488 return -EOPNOTSUPP;
1489 }
1490
amd_brs_drain(void)1491 static inline void amd_brs_drain(void)
1492 {
1493 }
1494
amd_brs_enable_all(void)1495 static inline void amd_brs_enable_all(void)
1496 {
1497 }
1498
amd_brs_disable_all(void)1499 static inline void amd_brs_disable_all(void)
1500 {
1501 }
1502 #endif /* CONFIG_CPU_SUP_AMD */
1503
is_pebs_pt(struct perf_event * event)1504 static inline int is_pebs_pt(struct perf_event *event)
1505 {
1506 return !!(event->hw.flags & PERF_X86_EVENT_PEBS_VIA_PT);
1507 }
1508
1509 #ifdef CONFIG_CPU_SUP_INTEL
1510
intel_pmu_has_bts_period(struct perf_event * event,u64 period)1511 static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period)
1512 {
1513 struct hw_perf_event *hwc = &event->hw;
1514 unsigned int hw_event, bts_event;
1515
1516 if (event->attr.freq)
1517 return false;
1518
1519 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1520 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
1521
1522 return hw_event == bts_event && period == 1;
1523 }
1524
intel_pmu_has_bts(struct perf_event * event)1525 static inline bool intel_pmu_has_bts(struct perf_event *event)
1526 {
1527 struct hw_perf_event *hwc = &event->hw;
1528
1529 return intel_pmu_has_bts_period(event, hwc->sample_period);
1530 }
1531
__intel_pmu_pebs_disable_all(void)1532 static __always_inline void __intel_pmu_pebs_disable_all(void)
1533 {
1534 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1535 }
1536
__intel_pmu_arch_lbr_disable(void)1537 static __always_inline void __intel_pmu_arch_lbr_disable(void)
1538 {
1539 wrmsrl(MSR_ARCH_LBR_CTL, 0);
1540 }
1541
__intel_pmu_lbr_disable(void)1542 static __always_inline void __intel_pmu_lbr_disable(void)
1543 {
1544 u64 debugctl;
1545
1546 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1547 debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
1548 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1549 }
1550
1551 int intel_pmu_save_and_restart(struct perf_event *event);
1552
1553 struct event_constraint *
1554 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
1555 struct perf_event *event);
1556
1557 extern int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu);
1558 extern void intel_cpuc_finish(struct cpu_hw_events *cpuc);
1559
1560 int intel_pmu_init(void);
1561
1562 void init_debug_store_on_cpu(int cpu);
1563
1564 void fini_debug_store_on_cpu(int cpu);
1565
1566 void release_ds_buffers(void);
1567
1568 void reserve_ds_buffers(void);
1569
1570 void release_lbr_buffers(void);
1571
1572 void reserve_lbr_buffers(void);
1573
1574 extern struct event_constraint bts_constraint;
1575 extern struct event_constraint vlbr_constraint;
1576
1577 void intel_pmu_enable_bts(u64 config);
1578
1579 void intel_pmu_disable_bts(void);
1580
1581 int intel_pmu_drain_bts_buffer(void);
1582
1583 u64 grt_latency_data(struct perf_event *event, u64 status);
1584
1585 u64 cmt_latency_data(struct perf_event *event, u64 status);
1586
1587 u64 lnl_latency_data(struct perf_event *event, u64 status);
1588
1589 extern struct event_constraint intel_core2_pebs_event_constraints[];
1590
1591 extern struct event_constraint intel_atom_pebs_event_constraints[];
1592
1593 extern struct event_constraint intel_slm_pebs_event_constraints[];
1594
1595 extern struct event_constraint intel_glm_pebs_event_constraints[];
1596
1597 extern struct event_constraint intel_glp_pebs_event_constraints[];
1598
1599 extern struct event_constraint intel_grt_pebs_event_constraints[];
1600
1601 extern struct event_constraint intel_nehalem_pebs_event_constraints[];
1602
1603 extern struct event_constraint intel_westmere_pebs_event_constraints[];
1604
1605 extern struct event_constraint intel_snb_pebs_event_constraints[];
1606
1607 extern struct event_constraint intel_ivb_pebs_event_constraints[];
1608
1609 extern struct event_constraint intel_hsw_pebs_event_constraints[];
1610
1611 extern struct event_constraint intel_bdw_pebs_event_constraints[];
1612
1613 extern struct event_constraint intel_skl_pebs_event_constraints[];
1614
1615 extern struct event_constraint intel_icl_pebs_event_constraints[];
1616
1617 extern struct event_constraint intel_glc_pebs_event_constraints[];
1618
1619 extern struct event_constraint intel_lnc_pebs_event_constraints[];
1620
1621 struct event_constraint *intel_pebs_constraints(struct perf_event *event);
1622
1623 void intel_pmu_pebs_add(struct perf_event *event);
1624
1625 void intel_pmu_pebs_del(struct perf_event *event);
1626
1627 void intel_pmu_pebs_enable(struct perf_event *event);
1628
1629 void intel_pmu_pebs_disable(struct perf_event *event);
1630
1631 void intel_pmu_pebs_enable_all(void);
1632
1633 void intel_pmu_pebs_disable_all(void);
1634
1635 void intel_pmu_pebs_sched_task(struct perf_event_pmu_context *pmu_ctx, bool sched_in);
1636
1637 void intel_pmu_drain_pebs_buffer(void);
1638
1639 void intel_pmu_store_pebs_lbrs(struct lbr_entry *lbr);
1640
1641 void intel_ds_init(void);
1642
1643 void intel_pmu_lbr_save_brstack(struct perf_sample_data *data,
1644 struct cpu_hw_events *cpuc,
1645 struct perf_event *event);
1646
1647 void intel_pmu_lbr_swap_task_ctx(struct perf_event_pmu_context *prev_epc,
1648 struct perf_event_pmu_context *next_epc);
1649
1650 void intel_pmu_lbr_sched_task(struct perf_event_pmu_context *pmu_ctx, bool sched_in);
1651
1652 u64 lbr_from_signext_quirk_wr(u64 val);
1653
1654 void intel_pmu_lbr_reset(void);
1655
1656 void intel_pmu_lbr_reset_32(void);
1657
1658 void intel_pmu_lbr_reset_64(void);
1659
1660 void intel_pmu_lbr_add(struct perf_event *event);
1661
1662 void intel_pmu_lbr_del(struct perf_event *event);
1663
1664 void intel_pmu_lbr_enable_all(bool pmi);
1665
1666 void intel_pmu_lbr_disable_all(void);
1667
1668 void intel_pmu_lbr_read(void);
1669
1670 void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc);
1671
1672 void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc);
1673
1674 void intel_pmu_lbr_save(void *ctx);
1675
1676 void intel_pmu_lbr_restore(void *ctx);
1677
1678 void intel_pmu_lbr_init_core(void);
1679
1680 void intel_pmu_lbr_init_nhm(void);
1681
1682 void intel_pmu_lbr_init_atom(void);
1683
1684 void intel_pmu_lbr_init_slm(void);
1685
1686 void intel_pmu_lbr_init_snb(void);
1687
1688 void intel_pmu_lbr_init_hsw(void);
1689
1690 void intel_pmu_lbr_init_skl(void);
1691
1692 void intel_pmu_lbr_init_knl(void);
1693
1694 void intel_pmu_lbr_init(void);
1695
1696 void intel_pmu_arch_lbr_init(void);
1697
1698 void intel_pmu_pebs_data_source_nhm(void);
1699
1700 void intel_pmu_pebs_data_source_skl(bool pmem);
1701
1702 void intel_pmu_pebs_data_source_adl(void);
1703
1704 void intel_pmu_pebs_data_source_grt(void);
1705
1706 void intel_pmu_pebs_data_source_mtl(void);
1707
1708 void intel_pmu_pebs_data_source_cmt(void);
1709
1710 void intel_pmu_pebs_data_source_lnl(void);
1711
1712 int intel_pmu_setup_lbr_filter(struct perf_event *event);
1713
1714 void intel_pt_interrupt(void);
1715
1716 int intel_bts_interrupt(void);
1717
1718 void intel_bts_enable_local(void);
1719
1720 void intel_bts_disable_local(void);
1721
1722 int p4_pmu_init(void);
1723
1724 int p6_pmu_init(void);
1725
1726 int knc_pmu_init(void);
1727
is_ht_workaround_enabled(void)1728 static inline int is_ht_workaround_enabled(void)
1729 {
1730 return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED);
1731 }
1732
intel_pmu_pebs_mask(u64 cntr_mask)1733 static inline u64 intel_pmu_pebs_mask(u64 cntr_mask)
1734 {
1735 return MAX_PEBS_EVENTS_MASK & cntr_mask;
1736 }
1737
intel_pmu_max_num_pebs(struct pmu * pmu)1738 static inline int intel_pmu_max_num_pebs(struct pmu *pmu)
1739 {
1740 static_assert(MAX_PEBS_EVENTS == 32);
1741 return fls((u32)hybrid(pmu, pebs_events_mask));
1742 }
1743
1744 #else /* CONFIG_CPU_SUP_INTEL */
1745
reserve_ds_buffers(void)1746 static inline void reserve_ds_buffers(void)
1747 {
1748 }
1749
release_ds_buffers(void)1750 static inline void release_ds_buffers(void)
1751 {
1752 }
1753
release_lbr_buffers(void)1754 static inline void release_lbr_buffers(void)
1755 {
1756 }
1757
reserve_lbr_buffers(void)1758 static inline void reserve_lbr_buffers(void)
1759 {
1760 }
1761
intel_pmu_init(void)1762 static inline int intel_pmu_init(void)
1763 {
1764 return 0;
1765 }
1766
intel_cpuc_prepare(struct cpu_hw_events * cpuc,int cpu)1767 static inline int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
1768 {
1769 return 0;
1770 }
1771
intel_cpuc_finish(struct cpu_hw_events * cpuc)1772 static inline void intel_cpuc_finish(struct cpu_hw_events *cpuc)
1773 {
1774 }
1775
is_ht_workaround_enabled(void)1776 static inline int is_ht_workaround_enabled(void)
1777 {
1778 return 0;
1779 }
1780 #endif /* CONFIG_CPU_SUP_INTEL */
1781
1782 #if ((defined CONFIG_CPU_SUP_CENTAUR) || (defined CONFIG_CPU_SUP_ZHAOXIN))
1783 int zhaoxin_pmu_init(void);
1784 #else
zhaoxin_pmu_init(void)1785 static inline int zhaoxin_pmu_init(void)
1786 {
1787 return 0;
1788 }
1789 #endif /*CONFIG_CPU_SUP_CENTAUR or CONFIG_CPU_SUP_ZHAOXIN*/
1790