1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __KVM_X86_VMX_H
3 #define __KVM_X86_VMX_H
4
5 #include <linux/kvm_host.h>
6
7 #include <asm/kvm.h>
8 #include <asm/intel_pt.h>
9 #include <asm/perf_event.h>
10 #include <asm/posted_intr.h>
11
12 #include "capabilities.h"
13 #include "../kvm_cache_regs.h"
14 #include "vmcs.h"
15 #include "vmx_ops.h"
16 #include "../cpuid.h"
17 #include "run_flags.h"
18 #include "../mmu.h"
19
20 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
21
22 #ifdef CONFIG_X86_64
23 #define MAX_NR_USER_RETURN_MSRS 7
24 #else
25 #define MAX_NR_USER_RETURN_MSRS 4
26 #endif
27
28 #define MAX_NR_LOADSTORE_MSRS 8
29
30 struct vmx_msrs {
31 unsigned int nr;
32 struct vmx_msr_entry val[MAX_NR_LOADSTORE_MSRS];
33 };
34
35 struct vmx_uret_msr {
36 bool load_into_hardware;
37 u64 data;
38 u64 mask;
39 };
40
41 enum segment_cache_field {
42 SEG_FIELD_SEL = 0,
43 SEG_FIELD_BASE = 1,
44 SEG_FIELD_LIMIT = 2,
45 SEG_FIELD_AR = 3,
46
47 SEG_FIELD_NR = 4
48 };
49
50 #define RTIT_ADDR_RANGE 4
51
52 struct pt_ctx {
53 u64 ctl;
54 u64 status;
55 u64 output_base;
56 u64 output_mask;
57 u64 cr3_match;
58 u64 addr_a[RTIT_ADDR_RANGE];
59 u64 addr_b[RTIT_ADDR_RANGE];
60 };
61
62 struct pt_desc {
63 u64 ctl_bitmask;
64 u32 num_address_ranges;
65 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
66 struct pt_ctx host;
67 struct pt_ctx guest;
68 };
69
70 union vmx_exit_reason {
71 struct {
72 u32 basic : 16;
73 u32 reserved16 : 1;
74 u32 reserved17 : 1;
75 u32 reserved18 : 1;
76 u32 reserved19 : 1;
77 u32 reserved20 : 1;
78 u32 reserved21 : 1;
79 u32 reserved22 : 1;
80 u32 reserved23 : 1;
81 u32 reserved24 : 1;
82 u32 reserved25 : 1;
83 u32 bus_lock_detected : 1;
84 u32 enclave_mode : 1;
85 u32 smi_pending_mtf : 1;
86 u32 smi_from_vmx_root : 1;
87 u32 reserved30 : 1;
88 u32 failed_vmentry : 1;
89 };
90 u32 full;
91 };
92
93 struct lbr_desc {
94 /* Basic info about guest LBR records. */
95 struct x86_pmu_lbr records;
96
97 /*
98 * Emulate LBR feature via passthrough LBR registers when the
99 * per-vcpu guest LBR event is scheduled on the current pcpu.
100 *
101 * The records may be inaccurate if the host reclaims the LBR.
102 */
103 struct perf_event *event;
104
105 /* True if LBRs are marked as not intercepted in the MSR bitmap */
106 bool msr_passthrough;
107 };
108
109 extern struct x86_pmu_lbr vmx_lbr_caps;
110
111 /*
112 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
113 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
114 */
115 struct nested_vmx {
116 /* Has the level1 guest done vmxon? */
117 bool vmxon;
118 gpa_t vmxon_ptr;
119 bool pml_full;
120
121 /* The guest-physical address of the current VMCS L1 keeps for L2 */
122 gpa_t current_vmptr;
123 /*
124 * Cache of the guest's VMCS, existing outside of guest memory.
125 * Loaded from guest memory during VMPTRLD. Flushed to guest
126 * memory during VMCLEAR and VMPTRLD.
127 */
128 struct vmcs12 *cached_vmcs12;
129 /*
130 * Cache of the guest's shadow VMCS, existing outside of guest
131 * memory. Loaded from guest memory during VM entry. Flushed
132 * to guest memory during VM exit.
133 */
134 struct vmcs12 *cached_shadow_vmcs12;
135
136 /*
137 * GPA to HVA cache for accessing vmcs12->vmcs_link_pointer
138 */
139 struct gfn_to_hva_cache shadow_vmcs12_cache;
140
141 /*
142 * GPA to HVA cache for VMCS12
143 */
144 struct gfn_to_hva_cache vmcs12_cache;
145
146 /*
147 * Indicates if the shadow vmcs or enlightened vmcs must be updated
148 * with the data held by struct vmcs12.
149 */
150 bool need_vmcs12_to_shadow_sync;
151 bool dirty_vmcs12;
152
153 /*
154 * Indicates whether MSR bitmap for L2 needs to be rebuilt due to
155 * changes in MSR bitmap for L1 or switching to a different L2. Note,
156 * this flag can only be used reliably in conjunction with a paravirt L1
157 * which informs L0 whether any changes to MSR bitmap for L2 were done
158 * on its side.
159 */
160 bool force_msr_bitmap_recalc;
161
162 /*
163 * Indicates lazily loaded guest state has not yet been decached from
164 * vmcs02.
165 */
166 bool need_sync_vmcs02_to_vmcs12_rare;
167
168 /*
169 * vmcs02 has been initialized, i.e. state that is constant for
170 * vmcs02 has been written to the backing VMCS. Initialization
171 * is delayed until L1 actually attempts to run a nested VM.
172 */
173 bool vmcs02_initialized;
174
175 bool change_vmcs01_virtual_apic_mode;
176 bool reload_vmcs01_apic_access_page;
177 bool update_vmcs01_cpu_dirty_logging;
178 bool update_vmcs01_apicv_status;
179 bool update_vmcs01_hwapic_isr;
180
181 /*
182 * Enlightened VMCS has been enabled. It does not mean that L1 has to
183 * use it. However, VMX features available to L1 will be limited based
184 * on what the enlightened VMCS supports.
185 */
186 bool enlightened_vmcs_enabled;
187
188 /* L2 must run next, and mustn't decide to exit to L1. */
189 bool nested_run_pending;
190
191 /* Pending MTF VM-exit into L1. */
192 bool mtf_pending;
193
194 struct loaded_vmcs vmcs02;
195
196 /*
197 * Guest pages referred to in the vmcs02 with host-physical
198 * pointers, so we must keep them pinned while L2 runs.
199 */
200 struct kvm_host_map apic_access_page_map;
201 struct kvm_host_map virtual_apic_map;
202 struct kvm_host_map pi_desc_map;
203
204 struct kvm_host_map msr_bitmap_map;
205
206 struct pi_desc *pi_desc;
207 bool pi_pending;
208 u16 posted_intr_nv;
209
210 struct hrtimer preemption_timer;
211 u64 preemption_timer_deadline;
212 bool has_preemption_timer_deadline;
213 bool preemption_timer_expired;
214
215 /*
216 * Used to snapshot MSRs that are conditionally loaded on VM-Enter in
217 * order to propagate the guest's pre-VM-Enter value into vmcs02. For
218 * emulation of VMLAUNCH/VMRESUME, the snapshot will be of L1's value.
219 * For KVM_SET_NESTED_STATE, the snapshot is of L2's value, _if_
220 * userspace restores MSRs before nested state. If userspace restores
221 * MSRs after nested state, the snapshot holds garbage, but KVM can't
222 * detect that, and the garbage value in vmcs02 will be overwritten by
223 * MSR restoration in any case.
224 */
225 u64 pre_vmenter_debugctl;
226 u64 pre_vmenter_bndcfgs;
227
228 /* to migrate it to L1 if L2 writes to L1's CR8 directly */
229 int l1_tpr_threshold;
230
231 u16 vpid02;
232 u16 last_vpid;
233
234 struct nested_vmx_msrs msrs;
235
236 /* SMM related state */
237 struct {
238 /* in VMX operation on SMM entry? */
239 bool vmxon;
240 /* in guest mode on SMM entry? */
241 bool guest_mode;
242 } smm;
243
244 #ifdef CONFIG_KVM_HYPERV
245 gpa_t hv_evmcs_vmptr;
246 struct kvm_host_map hv_evmcs_map;
247 struct hv_enlightened_vmcs *hv_evmcs;
248 #endif
249 };
250
251 struct vcpu_vmx {
252 struct kvm_vcpu vcpu;
253 u8 fail;
254 u8 x2apic_msr_bitmap_mode;
255
256 /*
257 * If true, host state has been stored in vmx->loaded_vmcs for
258 * the CPU registers that only need to be switched when transitioning
259 * to/from the kernel, and the registers have been loaded with guest
260 * values. If false, host state is loaded in the CPU registers
261 * and vmx->loaded_vmcs->host_state is invalid.
262 */
263 bool guest_state_loaded;
264
265 unsigned long exit_qualification;
266 u32 exit_intr_info;
267 u32 idt_vectoring_info;
268 ulong rflags;
269
270 /*
271 * User return MSRs are always emulated when enabled in the guest, but
272 * only loaded into hardware when necessary, e.g. SYSCALL #UDs outside
273 * of 64-bit mode or if EFER.SCE=1, thus the SYSCALL MSRs don't need to
274 * be loaded into hardware if those conditions aren't met.
275 */
276 struct vmx_uret_msr guest_uret_msrs[MAX_NR_USER_RETURN_MSRS];
277 bool guest_uret_msrs_loaded;
278 #ifdef CONFIG_X86_64
279 u64 msr_host_kernel_gs_base;
280 u64 msr_guest_kernel_gs_base;
281 #endif
282
283 u64 spec_ctrl;
284 u32 msr_ia32_umwait_control;
285
286 /*
287 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
288 * non-nested (L1) guest, it always points to vmcs01. For a nested
289 * guest (L2), it points to a different VMCS.
290 */
291 struct loaded_vmcs vmcs01;
292 struct loaded_vmcs *loaded_vmcs;
293
294 struct msr_autoload {
295 struct vmx_msrs guest;
296 struct vmx_msrs host;
297 } msr_autoload;
298
299 struct msr_autostore {
300 struct vmx_msrs guest;
301 } msr_autostore;
302
303 struct {
304 int vm86_active;
305 ulong save_rflags;
306 struct kvm_segment segs[8];
307 } rmode;
308 struct {
309 u32 bitmask; /* 4 bits per segment (1 bit per field) */
310 struct kvm_save_segment {
311 u16 selector;
312 unsigned long base;
313 u32 limit;
314 u32 ar;
315 } seg[8];
316 } segment_cache;
317 int vpid;
318 bool emulation_required;
319
320 union vmx_exit_reason exit_reason;
321
322 /* Posted interrupt descriptor */
323 struct pi_desc pi_desc;
324
325 /* Used if this vCPU is waiting for PI notification wakeup. */
326 struct list_head pi_wakeup_list;
327
328 /* Support for a guest hypervisor (nested VMX) */
329 struct nested_vmx nested;
330
331 /* Dynamic PLE window. */
332 unsigned int ple_window;
333 bool ple_window_dirty;
334
335 /* Support for PML */
336 #define PML_ENTITY_NUM 512
337 struct page *pml_pg;
338
339 /* apic deadline value in host tsc */
340 u64 hv_deadline_tsc;
341
342 /*
343 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
344 * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included
345 * in msr_ia32_feature_control_valid_bits.
346 */
347 u64 msr_ia32_feature_control;
348 u64 msr_ia32_feature_control_valid_bits;
349 /* SGX Launch Control public key hash */
350 u64 msr_ia32_sgxlepubkeyhash[4];
351 u64 msr_ia32_mcu_opt_ctrl;
352 bool disable_fb_clear;
353
354 struct pt_desc pt_desc;
355 struct lbr_desc lbr_desc;
356
357 /* Save desired MSR intercept (read: pass-through) state */
358 #define MAX_POSSIBLE_PASSTHROUGH_MSRS 16
359 struct {
360 DECLARE_BITMAP(read, MAX_POSSIBLE_PASSTHROUGH_MSRS);
361 DECLARE_BITMAP(write, MAX_POSSIBLE_PASSTHROUGH_MSRS);
362 } shadow_msr_intercept;
363
364 /* ve_info must be page aligned. */
365 struct vmx_ve_information *ve_info;
366 };
367
368 struct kvm_vmx {
369 struct kvm kvm;
370
371 unsigned int tss_addr;
372 bool ept_identity_pagetable_done;
373 gpa_t ept_identity_map_addr;
374 /* Posted Interrupt Descriptor (PID) table for IPI virtualization */
375 u64 *pid_table;
376 };
377
378 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
379 struct loaded_vmcs *buddy);
380 int allocate_vpid(void);
381 void free_vpid(int vpid);
382 void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
383 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
384 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
385 unsigned long fs_base, unsigned long gs_base);
386 int vmx_get_cpl(struct kvm_vcpu *vcpu);
387 bool vmx_emulation_required(struct kvm_vcpu *vcpu);
388 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
389 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
390 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
391 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
392 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
393 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
394 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
395 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
396 void ept_save_pdptrs(struct kvm_vcpu *vcpu);
397 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
398 void __vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
399 u64 construct_eptp(struct kvm_vcpu *vcpu, hpa_t root_hpa, int root_level);
400
401 bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu);
402 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu);
403 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu);
404 bool __vmx_interrupt_blocked(struct kvm_vcpu *vcpu);
405 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu);
406 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
407 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
408 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
409 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr);
410 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu);
411 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp);
412 void vmx_spec_ctrl_restore_host(struct vcpu_vmx *vmx, unsigned int flags);
413 unsigned int __vmx_vcpu_run_flags(struct vcpu_vmx *vmx);
414 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs,
415 unsigned int flags);
416 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr);
417 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu);
418
419 void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type);
420 void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type);
421
422 u64 vmx_get_l2_tsc_offset(struct kvm_vcpu *vcpu);
423 u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu);
424
425 gva_t vmx_get_untagged_addr(struct kvm_vcpu *vcpu, gva_t gva, unsigned int flags);
426
vmx_set_intercept_for_msr(struct kvm_vcpu * vcpu,u32 msr,int type,bool value)427 static inline void vmx_set_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr,
428 int type, bool value)
429 {
430 if (value)
431 vmx_enable_intercept_for_msr(vcpu, msr, type);
432 else
433 vmx_disable_intercept_for_msr(vcpu, msr, type);
434 }
435
436 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu);
437
438 u64 vmx_get_supported_debugctl(struct kvm_vcpu *vcpu, bool host_initiated);
439 bool vmx_is_valid_debugctl(struct kvm_vcpu *vcpu, u64 data, bool host_initiated);
440
vmx_guest_debugctl_write(struct kvm_vcpu * vcpu,u64 val)441 static inline void vmx_guest_debugctl_write(struct kvm_vcpu *vcpu, u64 val)
442 {
443 WARN_ON_ONCE(val & DEBUGCTLMSR_FREEZE_IN_SMM);
444
445 val |= vcpu->arch.host_debugctl & DEBUGCTLMSR_FREEZE_IN_SMM;
446 vmcs_write64(GUEST_IA32_DEBUGCTL, val);
447 }
448
vmx_guest_debugctl_read(void)449 static inline u64 vmx_guest_debugctl_read(void)
450 {
451 return vmcs_read64(GUEST_IA32_DEBUGCTL) & ~DEBUGCTLMSR_FREEZE_IN_SMM;
452 }
453
vmx_reload_guest_debugctl(struct kvm_vcpu * vcpu)454 static inline void vmx_reload_guest_debugctl(struct kvm_vcpu *vcpu)
455 {
456 u64 val = vmcs_read64(GUEST_IA32_DEBUGCTL);
457
458 if (!((val ^ vcpu->arch.host_debugctl) & DEBUGCTLMSR_FREEZE_IN_SMM))
459 return;
460
461 vmx_guest_debugctl_write(vcpu, val & ~DEBUGCTLMSR_FREEZE_IN_SMM);
462 }
463
464 /*
465 * Note, early Intel manuals have the write-low and read-high bitmap offsets
466 * the wrong way round. The bitmaps control MSRs 0x00000000-0x00001fff and
467 * 0xc0000000-0xc0001fff. The former (low) uses bytes 0-0x3ff for reads and
468 * 0x800-0xbff for writes. The latter (high) uses 0x400-0x7ff for reads and
469 * 0xc00-0xfff for writes. MSRs not covered by either of the ranges always
470 * VM-Exit.
471 */
472 #define __BUILD_VMX_MSR_BITMAP_HELPER(rtype, action, bitop, access, base) \
473 static inline rtype vmx_##action##_msr_bitmap_##access(unsigned long *bitmap, \
474 u32 msr) \
475 { \
476 int f = sizeof(unsigned long); \
477 \
478 if (msr <= 0x1fff) \
479 return bitop##_bit(msr, bitmap + base / f); \
480 else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) \
481 return bitop##_bit(msr & 0x1fff, bitmap + (base + 0x400) / f); \
482 return (rtype)true; \
483 }
484 #define BUILD_VMX_MSR_BITMAP_HELPERS(ret_type, action, bitop) \
485 __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, read, 0x0) \
486 __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, write, 0x800)
487
BUILD_VMX_MSR_BITMAP_HELPERS(bool,test,test)488 BUILD_VMX_MSR_BITMAP_HELPERS(bool, test, test)
489 BUILD_VMX_MSR_BITMAP_HELPERS(void, clear, __clear)
490 BUILD_VMX_MSR_BITMAP_HELPERS(void, set, __set)
491
492 static inline u8 vmx_get_rvi(void)
493 {
494 return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
495 }
496
497 #define __KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS \
498 (VM_ENTRY_LOAD_DEBUG_CONTROLS)
499 #ifdef CONFIG_X86_64
500 #define KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS \
501 (__KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS | \
502 VM_ENTRY_IA32E_MODE)
503 #else
504 #define KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS \
505 __KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS
506 #endif
507 #define KVM_OPTIONAL_VMX_VM_ENTRY_CONTROLS \
508 (VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | \
509 VM_ENTRY_LOAD_IA32_PAT | \
510 VM_ENTRY_LOAD_IA32_EFER | \
511 VM_ENTRY_LOAD_BNDCFGS | \
512 VM_ENTRY_PT_CONCEAL_PIP | \
513 VM_ENTRY_LOAD_IA32_RTIT_CTL)
514
515 #define __KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \
516 (VM_EXIT_SAVE_DEBUG_CONTROLS | \
517 VM_EXIT_ACK_INTR_ON_EXIT)
518 #ifdef CONFIG_X86_64
519 #define KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \
520 (__KVM_REQUIRED_VMX_VM_EXIT_CONTROLS | \
521 VM_EXIT_HOST_ADDR_SPACE_SIZE)
522 #else
523 #define KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \
524 __KVM_REQUIRED_VMX_VM_EXIT_CONTROLS
525 #endif
526 #define KVM_OPTIONAL_VMX_VM_EXIT_CONTROLS \
527 (VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | \
528 VM_EXIT_SAVE_IA32_PAT | \
529 VM_EXIT_LOAD_IA32_PAT | \
530 VM_EXIT_SAVE_IA32_EFER | \
531 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | \
532 VM_EXIT_LOAD_IA32_EFER | \
533 VM_EXIT_CLEAR_BNDCFGS | \
534 VM_EXIT_PT_CONCEAL_PIP | \
535 VM_EXIT_CLEAR_IA32_RTIT_CTL)
536
537 #define KVM_REQUIRED_VMX_PIN_BASED_VM_EXEC_CONTROL \
538 (PIN_BASED_EXT_INTR_MASK | \
539 PIN_BASED_NMI_EXITING)
540 #define KVM_OPTIONAL_VMX_PIN_BASED_VM_EXEC_CONTROL \
541 (PIN_BASED_VIRTUAL_NMIS | \
542 PIN_BASED_POSTED_INTR | \
543 PIN_BASED_VMX_PREEMPTION_TIMER)
544
545 #define __KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL \
546 (CPU_BASED_HLT_EXITING | \
547 CPU_BASED_CR3_LOAD_EXITING | \
548 CPU_BASED_CR3_STORE_EXITING | \
549 CPU_BASED_UNCOND_IO_EXITING | \
550 CPU_BASED_MOV_DR_EXITING | \
551 CPU_BASED_USE_TSC_OFFSETTING | \
552 CPU_BASED_MWAIT_EXITING | \
553 CPU_BASED_MONITOR_EXITING | \
554 CPU_BASED_INVLPG_EXITING | \
555 CPU_BASED_RDPMC_EXITING | \
556 CPU_BASED_INTR_WINDOW_EXITING)
557
558 #ifdef CONFIG_X86_64
559 #define KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL \
560 (__KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL | \
561 CPU_BASED_CR8_LOAD_EXITING | \
562 CPU_BASED_CR8_STORE_EXITING)
563 #else
564 #define KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL \
565 __KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL
566 #endif
567
568 #define KVM_OPTIONAL_VMX_CPU_BASED_VM_EXEC_CONTROL \
569 (CPU_BASED_RDTSC_EXITING | \
570 CPU_BASED_TPR_SHADOW | \
571 CPU_BASED_USE_IO_BITMAPS | \
572 CPU_BASED_MONITOR_TRAP_FLAG | \
573 CPU_BASED_USE_MSR_BITMAPS | \
574 CPU_BASED_NMI_WINDOW_EXITING | \
575 CPU_BASED_PAUSE_EXITING | \
576 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS | \
577 CPU_BASED_ACTIVATE_TERTIARY_CONTROLS)
578
579 #define KVM_REQUIRED_VMX_SECONDARY_VM_EXEC_CONTROL 0
580 #define KVM_OPTIONAL_VMX_SECONDARY_VM_EXEC_CONTROL \
581 (SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | \
582 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | \
583 SECONDARY_EXEC_WBINVD_EXITING | \
584 SECONDARY_EXEC_ENABLE_VPID | \
585 SECONDARY_EXEC_ENABLE_EPT | \
586 SECONDARY_EXEC_UNRESTRICTED_GUEST | \
587 SECONDARY_EXEC_PAUSE_LOOP_EXITING | \
588 SECONDARY_EXEC_DESC | \
589 SECONDARY_EXEC_ENABLE_RDTSCP | \
590 SECONDARY_EXEC_ENABLE_INVPCID | \
591 SECONDARY_EXEC_APIC_REGISTER_VIRT | \
592 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | \
593 SECONDARY_EXEC_SHADOW_VMCS | \
594 SECONDARY_EXEC_ENABLE_XSAVES | \
595 SECONDARY_EXEC_RDSEED_EXITING | \
596 SECONDARY_EXEC_RDRAND_EXITING | \
597 SECONDARY_EXEC_ENABLE_PML | \
598 SECONDARY_EXEC_TSC_SCALING | \
599 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | \
600 SECONDARY_EXEC_PT_USE_GPA | \
601 SECONDARY_EXEC_PT_CONCEAL_VMX | \
602 SECONDARY_EXEC_ENABLE_VMFUNC | \
603 SECONDARY_EXEC_BUS_LOCK_DETECTION | \
604 SECONDARY_EXEC_NOTIFY_VM_EXITING | \
605 SECONDARY_EXEC_ENCLS_EXITING | \
606 SECONDARY_EXEC_EPT_VIOLATION_VE)
607
608 #define KVM_REQUIRED_VMX_TERTIARY_VM_EXEC_CONTROL 0
609 #define KVM_OPTIONAL_VMX_TERTIARY_VM_EXEC_CONTROL \
610 (TERTIARY_EXEC_IPI_VIRT)
611
612 #define BUILD_CONTROLS_SHADOW(lname, uname, bits) \
613 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u##bits val) \
614 { \
615 if (vmx->loaded_vmcs->controls_shadow.lname != val) { \
616 vmcs_write##bits(uname, val); \
617 vmx->loaded_vmcs->controls_shadow.lname = val; \
618 } \
619 } \
620 static inline u##bits __##lname##_controls_get(struct loaded_vmcs *vmcs) \
621 { \
622 return vmcs->controls_shadow.lname; \
623 } \
624 static inline u##bits lname##_controls_get(struct vcpu_vmx *vmx) \
625 { \
626 return __##lname##_controls_get(vmx->loaded_vmcs); \
627 } \
628 static __always_inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u##bits val) \
629 { \
630 BUILD_BUG_ON(!(val & (KVM_REQUIRED_VMX_##uname | KVM_OPTIONAL_VMX_##uname))); \
631 lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \
632 } \
633 static __always_inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u##bits val) \
634 { \
635 BUILD_BUG_ON(!(val & (KVM_REQUIRED_VMX_##uname | KVM_OPTIONAL_VMX_##uname))); \
636 lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \
637 }
638 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS, 32)
639 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS, 32)
640 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL, 32)
641 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL, 32)
642 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL, 32)
643 BUILD_CONTROLS_SHADOW(tertiary_exec, TERTIARY_VM_EXEC_CONTROL, 64)
644
645 /*
646 * VMX_REGS_LAZY_LOAD_SET - The set of registers that will be updated in the
647 * cache on demand. Other registers not listed here are synced to
648 * the cache immediately after VM-Exit.
649 */
650 #define VMX_REGS_LAZY_LOAD_SET ((1 << VCPU_REGS_RIP) | \
651 (1 << VCPU_REGS_RSP) | \
652 (1 << VCPU_EXREG_RFLAGS) | \
653 (1 << VCPU_EXREG_PDPTR) | \
654 (1 << VCPU_EXREG_SEGMENTS) | \
655 (1 << VCPU_EXREG_CR0) | \
656 (1 << VCPU_EXREG_CR3) | \
657 (1 << VCPU_EXREG_CR4) | \
658 (1 << VCPU_EXREG_EXIT_INFO_1) | \
659 (1 << VCPU_EXREG_EXIT_INFO_2))
660
vmx_l1_guest_owned_cr0_bits(void)661 static inline unsigned long vmx_l1_guest_owned_cr0_bits(void)
662 {
663 unsigned long bits = KVM_POSSIBLE_CR0_GUEST_BITS;
664
665 /*
666 * CR0.WP needs to be intercepted when KVM is shadowing legacy paging
667 * in order to construct shadow PTEs with the correct protections.
668 * Note! CR0.WP technically can be passed through to the guest if
669 * paging is disabled, but checking CR0.PG would generate a cyclical
670 * dependency of sorts due to forcing the caller to ensure CR0 holds
671 * the correct value prior to determining which CR0 bits can be owned
672 * by L1. Keep it simple and limit the optimization to EPT.
673 */
674 if (!enable_ept)
675 bits &= ~X86_CR0_WP;
676 return bits;
677 }
678
to_kvm_vmx(struct kvm * kvm)679 static __always_inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
680 {
681 return container_of(kvm, struct kvm_vmx, kvm);
682 }
683
to_vmx(struct kvm_vcpu * vcpu)684 static __always_inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
685 {
686 return container_of(vcpu, struct vcpu_vmx, vcpu);
687 }
688
vcpu_to_lbr_desc(struct kvm_vcpu * vcpu)689 static inline struct lbr_desc *vcpu_to_lbr_desc(struct kvm_vcpu *vcpu)
690 {
691 return &to_vmx(vcpu)->lbr_desc;
692 }
693
vcpu_to_lbr_records(struct kvm_vcpu * vcpu)694 static inline struct x86_pmu_lbr *vcpu_to_lbr_records(struct kvm_vcpu *vcpu)
695 {
696 return &vcpu_to_lbr_desc(vcpu)->records;
697 }
698
intel_pmu_lbr_is_enabled(struct kvm_vcpu * vcpu)699 static inline bool intel_pmu_lbr_is_enabled(struct kvm_vcpu *vcpu)
700 {
701 return !!vcpu_to_lbr_records(vcpu)->nr;
702 }
703
704 void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu);
705 int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu);
706 void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu);
707
vmx_get_exit_qual(struct kvm_vcpu * vcpu)708 static __always_inline unsigned long vmx_get_exit_qual(struct kvm_vcpu *vcpu)
709 {
710 struct vcpu_vmx *vmx = to_vmx(vcpu);
711
712 if (!kvm_register_test_and_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1))
713 vmx->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
714
715 return vmx->exit_qualification;
716 }
717
vmx_get_intr_info(struct kvm_vcpu * vcpu)718 static __always_inline u32 vmx_get_intr_info(struct kvm_vcpu *vcpu)
719 {
720 struct vcpu_vmx *vmx = to_vmx(vcpu);
721
722 if (!kvm_register_test_and_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2))
723 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
724
725 return vmx->exit_intr_info;
726 }
727
728 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags);
729 void free_vmcs(struct vmcs *vmcs);
730 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
731 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
732 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);
733
alloc_vmcs(bool shadow)734 static inline struct vmcs *alloc_vmcs(bool shadow)
735 {
736 return alloc_vmcs_cpu(shadow, raw_smp_processor_id(),
737 GFP_KERNEL_ACCOUNT);
738 }
739
vmx_has_waitpkg(struct vcpu_vmx * vmx)740 static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx)
741 {
742 return secondary_exec_controls_get(vmx) &
743 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
744 }
745
vmx_need_pf_intercept(struct kvm_vcpu * vcpu)746 static inline bool vmx_need_pf_intercept(struct kvm_vcpu *vcpu)
747 {
748 if (!enable_ept)
749 return true;
750
751 return allow_smaller_maxphyaddr &&
752 cpuid_maxphyaddr(vcpu) < kvm_host.maxphyaddr;
753 }
754
is_unrestricted_guest(struct kvm_vcpu * vcpu)755 static inline bool is_unrestricted_guest(struct kvm_vcpu *vcpu)
756 {
757 return enable_unrestricted_guest && (!is_guest_mode(vcpu) ||
758 (secondary_exec_controls_get(to_vmx(vcpu)) &
759 SECONDARY_EXEC_UNRESTRICTED_GUEST));
760 }
761
762 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu);
vmx_guest_state_valid(struct kvm_vcpu * vcpu)763 static inline bool vmx_guest_state_valid(struct kvm_vcpu *vcpu)
764 {
765 return is_unrestricted_guest(vcpu) || __vmx_guest_state_valid(vcpu);
766 }
767
768 void dump_vmcs(struct kvm_vcpu *vcpu);
769
vmx_get_instr_info_reg2(u32 vmx_instr_info)770 static inline int vmx_get_instr_info_reg2(u32 vmx_instr_info)
771 {
772 return (vmx_instr_info >> 28) & 0xf;
773 }
774
vmx_can_use_ipiv(struct kvm_vcpu * vcpu)775 static inline bool vmx_can_use_ipiv(struct kvm_vcpu *vcpu)
776 {
777 return lapic_in_kernel(vcpu) && enable_ipiv;
778 }
779
vmx_segment_cache_clear(struct vcpu_vmx * vmx)780 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
781 {
782 vmx->segment_cache.bitmask = 0;
783 }
784
785 #endif /* __KVM_X86_VMX_H */
786