1 /* SPDX-License-Identifier: GPL-2.0 */
2
3 /*
4 * xHCI host controller driver
5 *
6 * Copyright (C) 2008 Intel Corp.
7 *
8 * Author: Sarah Sharp
9 * Some code borrowed from the Linux EHCI driver.
10 */
11
12 #ifndef __LINUX_XHCI_HCD_H
13 #define __LINUX_XHCI_HCD_H
14
15 #include <linux/usb.h>
16 #include <linux/timer.h>
17 #include <linux/kernel.h>
18 #include <linux/usb/hcd.h>
19 #include <linux/io-64-nonatomic-lo-hi.h>
20 #include <linux/io-64-nonatomic-hi-lo.h>
21 #include <linux/android_kabi.h>
22
23 /* Code sharing between pci-quirks and xhci hcd */
24 #include "xhci-ext-caps.h"
25 #include "pci-quirks.h"
26
27 #include "xhci-port.h"
28 #include "xhci-caps.h"
29
30 /* max buffer size for trace and debug messages */
31 #define XHCI_MSG_MAX 500
32
33 /* xHCI PCI Configuration Registers */
34 #define XHCI_SBRN_OFFSET (0x60)
35
36 /* Max number of USB devices for any host controller - limit in section 6.1 */
37 #define MAX_HC_SLOTS 256
38 /* Section 5.3.3 - MaxPorts */
39 #define MAX_HC_PORTS 127
40
41 /*
42 * xHCI register interface.
43 * This corresponds to the eXtensible Host Controller Interface (xHCI)
44 * Revision 0.95 specification
45 */
46
47 /**
48 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
49 * @hc_capbase: length of the capabilities register and HC version number
50 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
51 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
52 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
53 * @hcc_params: HCCPARAMS - Capability Parameters
54 * @db_off: DBOFF - Doorbell array offset
55 * @run_regs_off: RTSOFF - Runtime register space offset
56 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only
57 */
58 struct xhci_cap_regs {
59 __le32 hc_capbase;
60 __le32 hcs_params1;
61 __le32 hcs_params2;
62 __le32 hcs_params3;
63 __le32 hcc_params;
64 __le32 db_off;
65 __le32 run_regs_off;
66 __le32 hcc_params2; /* xhci 1.1 */
67 /* Reserved up to (CAPLENGTH - 0x1C) */
68 };
69
70 /* Number of registers per port */
71 #define NUM_PORT_REGS 4
72
73 #define PORTSC 0
74 #define PORTPMSC 1
75 #define PORTLI 2
76 #define PORTHLPMC 3
77
78 /**
79 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
80 * @command: USBCMD - xHC command register
81 * @status: USBSTS - xHC status register
82 * @page_size: This indicates the page size that the host controller
83 * supports. If bit n is set, the HC supports a page size
84 * of 2^(n+12), up to a 128MB page size.
85 * 4K is the minimum page size.
86 * @cmd_ring: CRP - 64-bit Command Ring Pointer
87 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
88 * @config_reg: CONFIG - Configure Register
89 * @port_status_base: PORTSCn - base address for Port Status and Control
90 * Each port has a Port Status and Control register,
91 * followed by a Port Power Management Status and Control
92 * register, a Port Link Info register, and a reserved
93 * register.
94 * @port_power_base: PORTPMSCn - base address for
95 * Port Power Management Status and Control
96 * @port_link_base: PORTLIn - base address for Port Link Info (current
97 * Link PM state and control) for USB 2.1 and USB 3.0
98 * devices.
99 */
100 struct xhci_op_regs {
101 __le32 command;
102 __le32 status;
103 __le32 page_size;
104 __le32 reserved1;
105 __le32 reserved2;
106 __le32 dev_notification;
107 __le64 cmd_ring;
108 /* rsvd: offset 0x20-2F */
109 __le32 reserved3[4];
110 __le64 dcbaa_ptr;
111 __le32 config_reg;
112 /* rsvd: offset 0x3C-3FF */
113 __le32 reserved4[241];
114 /* port 1 registers, which serve as a base address for other ports */
115 __le32 port_status_base;
116 __le32 port_power_base;
117 __le32 port_link_base;
118 __le32 reserved5;
119 /* registers for ports 2-255 */
120 __le32 reserved6[NUM_PORT_REGS*254];
121 };
122
123 /* USBCMD - USB command - command bitmasks */
124 /* start/stop HC execution - do not write unless HC is halted*/
125 #define CMD_RUN XHCI_CMD_RUN
126 /* Reset HC - resets internal HC state machine and all registers (except
127 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
128 * The xHCI driver must reinitialize the xHC after setting this bit.
129 */
130 #define CMD_RESET (1 << 1)
131 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
132 #define CMD_EIE XHCI_CMD_EIE
133 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
134 #define CMD_HSEIE XHCI_CMD_HSEIE
135 /* bits 4:6 are reserved (and should be preserved on writes). */
136 /* light reset (port status stays unchanged) - reset completed when this is 0 */
137 #define CMD_LRESET (1 << 7)
138 /* host controller save/restore state. */
139 #define CMD_CSS (1 << 8)
140 #define CMD_CRS (1 << 9)
141 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
142 #define CMD_EWE XHCI_CMD_EWE
143 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
144 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
145 * '0' means the xHC can power it off if all ports are in the disconnect,
146 * disabled, or powered-off state.
147 */
148 #define CMD_PM_INDEX (1 << 11)
149 /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */
150 #define CMD_ETE (1 << 14)
151 /* bits 15:31 are reserved (and should be preserved on writes). */
152
153 #define XHCI_RESET_LONG_USEC (10 * 1000 * 1000)
154 #define XHCI_RESET_SHORT_USEC (250 * 1000)
155
156 /* IMAN - Interrupt Management Register */
157 #define IMAN_IE (1 << 1)
158 #define IMAN_IP (1 << 0)
159
160 /* USBSTS - USB status - status bitmasks */
161 /* HC not running - set to 1 when run/stop bit is cleared. */
162 #define STS_HALT XHCI_STS_HALT
163 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
164 #define STS_FATAL (1 << 2)
165 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
166 #define STS_EINT (1 << 3)
167 /* port change detect */
168 #define STS_PORT (1 << 4)
169 /* bits 5:7 reserved and zeroed */
170 /* save state status - '1' means xHC is saving state */
171 #define STS_SAVE (1 << 8)
172 /* restore state status - '1' means xHC is restoring state */
173 #define STS_RESTORE (1 << 9)
174 /* true: save or restore error */
175 #define STS_SRE (1 << 10)
176 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
177 #define STS_CNR XHCI_STS_CNR
178 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
179 #define STS_HCE (1 << 12)
180 /* bits 13:31 reserved and should be preserved */
181
182 /*
183 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
184 * Generate a device notification event when the HC sees a transaction with a
185 * notification type that matches a bit set in this bit field.
186 */
187 #define DEV_NOTE_MASK (0xffff)
188 #define ENABLE_DEV_NOTE(x) (1 << (x))
189 /* Most of the device notification types should only be used for debug.
190 * SW does need to pay attention to function wake notifications.
191 */
192 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
193
194 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
195 /* bit 0 is the command ring cycle state */
196 /* stop ring operation after completion of the currently executing command */
197 #define CMD_RING_PAUSE (1 << 1)
198 /* stop ring immediately - abort the currently executing command */
199 #define CMD_RING_ABORT (1 << 2)
200 /* true: command ring is running */
201 #define CMD_RING_RUNNING (1 << 3)
202 /* bits 4:5 reserved and should be preserved */
203 /* Command Ring pointer - bit mask for the lower 32 bits. */
204 #define CMD_RING_RSVD_BITS (0x3f)
205
206 /* CONFIG - Configure Register - config_reg bitmasks */
207 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
208 #define MAX_DEVS(p) ((p) & 0xff)
209 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */
210 #define CONFIG_U3E (1 << 8)
211 /* bit 9: Configuration Information Enable, xhci 1.1 */
212 #define CONFIG_CIE (1 << 9)
213 /* bits 10:31 - reserved and should be preserved */
214
215 /**
216 * struct xhci_intr_reg - Interrupt Register Set
217 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
218 * interrupts and check for pending interrupts.
219 * @irq_control: IMOD - Interrupt Moderation Register.
220 * Used to throttle interrupts.
221 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
222 * @erst_base: ERST base address.
223 * @erst_dequeue: Event ring dequeue pointer.
224 *
225 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
226 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
227 * multiple segments of the same size. The HC places events on the ring and
228 * "updates the Cycle bit in the TRBs to indicate to software the current
229 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
230 * updates the dequeue pointer.
231 */
232 struct xhci_intr_reg {
233 __le32 irq_pending;
234 __le32 irq_control;
235 __le32 erst_size;
236 __le32 rsvd;
237 __le64 erst_base;
238 __le64 erst_dequeue;
239 };
240
241 /* irq_pending bitmasks */
242 #define ER_IRQ_PENDING(p) ((p) & 0x1)
243 /* bits 2:31 need to be preserved */
244 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
245 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
246 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
247 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
248
249 /* irq_control bitmasks */
250 /* Minimum interval between interrupts (in 250ns intervals). The interval
251 * between interrupts will be longer if there are no events on the event ring.
252 * Default is 4000 (1 ms).
253 */
254 #define ER_IRQ_INTERVAL_MASK (0xffff)
255 /* Counter used to count down the time to the next interrupt - HW use only */
256 #define ER_IRQ_COUNTER_MASK (0xffff << 16)
257
258 /* erst_size bitmasks */
259 /* Preserve bits 16:31 of erst_size */
260 #define ERST_SIZE_MASK (0xffff << 16)
261
262 /* erst_base bitmasks */
263 #define ERST_BASE_RSVDP (GENMASK_ULL(5, 0))
264
265 /* erst_dequeue bitmasks */
266 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
267 * where the current dequeue pointer lies. This is an optional HW hint.
268 */
269 #define ERST_DESI_MASK (0x7)
270 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
271 * a work queue (or delayed service routine)?
272 */
273 #define ERST_EHB (1 << 3)
274 #define ERST_PTR_MASK (GENMASK_ULL(63, 4))
275
276 /**
277 * struct xhci_run_regs
278 * @microframe_index:
279 * MFINDEX - current microframe number
280 *
281 * Section 5.5 Host Controller Runtime Registers:
282 * "Software should read and write these registers using only Dword (32 bit)
283 * or larger accesses"
284 */
285 struct xhci_run_regs {
286 __le32 microframe_index;
287 __le32 rsvd[7];
288 struct xhci_intr_reg ir_set[128];
289 };
290
291 /**
292 * struct doorbell_array
293 *
294 * Bits 0 - 7: Endpoint target
295 * Bits 8 - 15: RsvdZ
296 * Bits 16 - 31: Stream ID
297 *
298 * Section 5.6
299 */
300 struct xhci_doorbell_array {
301 __le32 doorbell[256];
302 };
303
304 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
305 #define DB_VALUE_HOST 0x00000000
306
307 #define PLT_MASK (0x03 << 6)
308 #define PLT_SYM (0x00 << 6)
309 #define PLT_ASYM_RX (0x02 << 6)
310 #define PLT_ASYM_TX (0x03 << 6)
311
312 /**
313 * struct xhci_container_ctx
314 * @type: Type of context. Used to calculated offsets to contained contexts.
315 * @size: Size of the context data
316 * @bytes: The raw context data given to HW
317 * @dma: dma address of the bytes
318 *
319 * Represents either a Device or Input context. Holds a pointer to the raw
320 * memory used for the context (bytes) and dma address of it (dma).
321 */
322 struct xhci_container_ctx {
323 unsigned type;
324 #define XHCI_CTX_TYPE_DEVICE 0x1
325 #define XHCI_CTX_TYPE_INPUT 0x2
326
327 int size;
328
329 u8 *bytes;
330 dma_addr_t dma;
331 };
332
333 /**
334 * struct xhci_slot_ctx
335 * @dev_info: Route string, device speed, hub info, and last valid endpoint
336 * @dev_info2: Max exit latency for device number, root hub port number
337 * @tt_info: tt_info is used to construct split transaction tokens
338 * @dev_state: slot state and device address
339 *
340 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
341 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
342 * reserved at the end of the slot context for HC internal use.
343 */
344 struct xhci_slot_ctx {
345 __le32 dev_info;
346 __le32 dev_info2;
347 __le32 tt_info;
348 __le32 dev_state;
349 /* offset 0x10 to 0x1f reserved for HC internal use */
350 __le32 reserved[4];
351 };
352
353 /* dev_info bitmasks */
354 /* Route String - 0:19 */
355 #define ROUTE_STRING_MASK (0xfffff)
356 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
357 #define DEV_SPEED (0xf << 20)
358 #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
359 /* bit 24 reserved */
360 /* Is this LS/FS device connected through a HS hub? - bit 25 */
361 #define DEV_MTT (0x1 << 25)
362 /* Set if the device is a hub - bit 26 */
363 #define DEV_HUB (0x1 << 26)
364 /* Index of the last valid endpoint context in this device context - 27:31 */
365 #define LAST_CTX_MASK (0x1f << 27)
366 #define LAST_CTX(p) ((p) << 27)
367 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
368 #define SLOT_FLAG (1 << 0)
369 #define EP0_FLAG (1 << 1)
370
371 /* dev_info2 bitmasks */
372 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
373 #define MAX_EXIT (0xffff)
374 /* Root hub port number that is needed to access the USB device */
375 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
376 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
377 /* Maximum number of ports under a hub device */
378 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
379 #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24)
380
381 /* tt_info bitmasks */
382 /*
383 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
384 * The Slot ID of the hub that isolates the high speed signaling from
385 * this low or full-speed device. '0' if attached to root hub port.
386 */
387 #define TT_SLOT (0xff)
388 /*
389 * The number of the downstream facing port of the high-speed hub
390 * '0' if the device is not low or full speed.
391 */
392 #define TT_PORT (0xff << 8)
393 #define TT_THINK_TIME(p) (((p) & 0x3) << 16)
394 #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16)
395
396 /* dev_state bitmasks */
397 /* USB device address - assigned by the HC */
398 #define DEV_ADDR_MASK (0xff)
399 /* bits 8:26 reserved */
400 /* Slot state */
401 #define SLOT_STATE (0x1f << 27)
402 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
403
404 #define SLOT_STATE_DISABLED 0
405 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
406 #define SLOT_STATE_DEFAULT 1
407 #define SLOT_STATE_ADDRESSED 2
408 #define SLOT_STATE_CONFIGURED 3
409
410 /**
411 * struct xhci_ep_ctx
412 * @ep_info: endpoint state, streams, mult, and interval information.
413 * @ep_info2: information on endpoint type, max packet size, max burst size,
414 * error count, and whether the HC will force an event for all
415 * transactions.
416 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
417 * defines one stream, this points to the endpoint transfer ring.
418 * Otherwise, it points to a stream context array, which has a
419 * ring pointer for each flow.
420 * @tx_info:
421 * Average TRB lengths for the endpoint ring and
422 * max payload within an Endpoint Service Interval Time (ESIT).
423 *
424 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
425 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
426 * reserved at the end of the endpoint context for HC internal use.
427 */
428 struct xhci_ep_ctx {
429 __le32 ep_info;
430 __le32 ep_info2;
431 __le64 deq;
432 __le32 tx_info;
433 /* offset 0x14 - 0x1f reserved for HC internal use */
434 __le32 reserved[3];
435 };
436
437 /* ep_info bitmasks */
438 /*
439 * Endpoint State - bits 0:2
440 * 0 - disabled
441 * 1 - running
442 * 2 - halted due to halt condition - ok to manipulate endpoint ring
443 * 3 - stopped
444 * 4 - TRB error
445 * 5-7 - reserved
446 */
447 #define EP_STATE_MASK (0x7)
448 #define EP_STATE_DISABLED 0
449 #define EP_STATE_RUNNING 1
450 #define EP_STATE_HALTED 2
451 #define EP_STATE_STOPPED 3
452 #define EP_STATE_ERROR 4
453 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
454
455 /* Mult - Max number of burtst within an interval, in EP companion desc. */
456 #define EP_MULT(p) (((p) & 0x3) << 8)
457 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
458 /* bits 10:14 are Max Primary Streams */
459 /* bit 15 is Linear Stream Array */
460 /* Interval - period between requests to an endpoint - 125u increments. */
461 #define EP_INTERVAL(p) (((p) & 0xff) << 16)
462 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
463 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
464 #define EP_MAXPSTREAMS_MASK (0x1f << 10)
465 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
466 #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
467 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
468 #define EP_HAS_LSA (1 << 15)
469 /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */
470 #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
471
472 /* ep_info2 bitmasks */
473 /*
474 * Force Event - generate transfer events for all TRBs for this endpoint
475 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
476 */
477 #define FORCE_EVENT (0x1)
478 #define ERROR_COUNT(p) (((p) & 0x3) << 1)
479 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
480 #define EP_TYPE(p) ((p) << 3)
481 #define ISOC_OUT_EP 1
482 #define BULK_OUT_EP 2
483 #define INT_OUT_EP 3
484 #define CTRL_EP 4
485 #define ISOC_IN_EP 5
486 #define BULK_IN_EP 6
487 #define INT_IN_EP 7
488 /* bit 6 reserved */
489 /* bit 7 is Host Initiate Disable - for disabling stream selection */
490 #define MAX_BURST(p) (((p)&0xff) << 8)
491 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
492 #define MAX_PACKET(p) (((p)&0xffff) << 16)
493 #define MAX_PACKET_MASK (0xffff << 16)
494 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
495
496 /* tx_info bitmasks */
497 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
498 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
499 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
500 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
501
502 /* deq bitmasks */
503 #define EP_CTX_CYCLE_MASK (1 << 0)
504 #define SCTX_DEQ_MASK (~0xfL)
505
506
507 /**
508 * struct xhci_input_control_context
509 * Input control context; see section 6.2.5.
510 *
511 * @drop_context: set the bit of the endpoint context you want to disable
512 * @add_context: set the bit of the endpoint context you want to enable
513 */
514 struct xhci_input_control_ctx {
515 __le32 drop_flags;
516 __le32 add_flags;
517 __le32 rsvd2[6];
518 };
519
520 #define EP_IS_ADDED(ctrl_ctx, i) \
521 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
522 #define EP_IS_DROPPED(ctrl_ctx, i) \
523 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
524
525 /* Represents everything that is needed to issue a command on the command ring.
526 * It's useful to pre-allocate these for commands that cannot fail due to
527 * out-of-memory errors, like freeing streams.
528 */
529 struct xhci_command {
530 /* Input context for changing device state */
531 struct xhci_container_ctx *in_ctx;
532 u32 status;
533 int slot_id;
534 /* If completion is null, no one is waiting on this command
535 * and the structure can be freed after the command completes.
536 */
537 struct completion *completion;
538 union xhci_trb *command_trb;
539 struct list_head cmd_list;
540 /* xHCI command response timeout in milliseconds */
541 unsigned int timeout_ms;
542
543 ANDROID_KABI_RESERVE(1);
544 ANDROID_KABI_RESERVE(2);
545 };
546
547 /* drop context bitmasks */
548 #define DROP_EP(x) (0x1 << x)
549 /* add context bitmasks */
550 #define ADD_EP(x) (0x1 << x)
551
552 struct xhci_stream_ctx {
553 /* 64-bit stream ring address, cycle state, and stream type */
554 __le64 stream_ring;
555 /* offset 0x14 - 0x1f reserved for HC internal use */
556 __le32 reserved[2];
557 };
558
559 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
560 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
561 /* Secondary stream array type, dequeue pointer is to a transfer ring */
562 #define SCT_SEC_TR 0
563 /* Primary stream array type, dequeue pointer is to a transfer ring */
564 #define SCT_PRI_TR 1
565 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
566 #define SCT_SSA_8 2
567 #define SCT_SSA_16 3
568 #define SCT_SSA_32 4
569 #define SCT_SSA_64 5
570 #define SCT_SSA_128 6
571 #define SCT_SSA_256 7
572
573 /* Assume no secondary streams for now */
574 struct xhci_stream_info {
575 struct xhci_ring **stream_rings;
576 /* Number of streams, including stream 0 (which drivers can't use) */
577 unsigned int num_streams;
578 /* The stream context array may be bigger than
579 * the number of streams the driver asked for
580 */
581 struct xhci_stream_ctx *stream_ctx_array;
582 unsigned int num_stream_ctxs;
583 dma_addr_t ctx_array_dma;
584 /* For mapping physical TRB addresses to segments in stream rings */
585 struct radix_tree_root trb_address_map;
586 struct xhci_command *free_streams_command;
587 };
588
589 #define SMALL_STREAM_ARRAY_SIZE 256
590 #define MEDIUM_STREAM_ARRAY_SIZE 1024
591
592 /* Some Intel xHCI host controllers need software to keep track of the bus
593 * bandwidth. Keep track of endpoint info here. Each root port is allocated
594 * the full bus bandwidth. We must also treat TTs (including each port under a
595 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
596 * (DMI) also limits the total bandwidth (across all domains) that can be used.
597 */
598 struct xhci_bw_info {
599 /* ep_interval is zero-based */
600 unsigned int ep_interval;
601 /* mult and num_packets are one-based */
602 unsigned int mult;
603 unsigned int num_packets;
604 unsigned int max_packet_size;
605 unsigned int max_esit_payload;
606 unsigned int type;
607 };
608
609 /* "Block" sizes in bytes the hardware uses for different device speeds.
610 * The logic in this part of the hardware limits the number of bits the hardware
611 * can use, so must represent bandwidth in a less precise manner to mimic what
612 * the scheduler hardware computes.
613 */
614 #define FS_BLOCK 1
615 #define HS_BLOCK 4
616 #define SS_BLOCK 16
617 #define DMI_BLOCK 32
618
619 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
620 * with each byte transferred. SuperSpeed devices have an initial overhead to
621 * set up bursts. These are in blocks, see above. LS overhead has already been
622 * translated into FS blocks.
623 */
624 #define DMI_OVERHEAD 8
625 #define DMI_OVERHEAD_BURST 4
626 #define SS_OVERHEAD 8
627 #define SS_OVERHEAD_BURST 32
628 #define HS_OVERHEAD 26
629 #define FS_OVERHEAD 20
630 #define LS_OVERHEAD 128
631 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per
632 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
633 * of overhead associated with split transfers crossing microframe boundaries.
634 * 31 blocks is pure protocol overhead.
635 */
636 #define TT_HS_OVERHEAD (31 + 94)
637 #define TT_DMI_OVERHEAD (25 + 12)
638
639 /* Bandwidth limits in blocks */
640 #define FS_BW_LIMIT 1285
641 #define TT_BW_LIMIT 1320
642 #define HS_BW_LIMIT 1607
643 #define SS_BW_LIMIT_IN 3906
644 #define DMI_BW_LIMIT_IN 3906
645 #define SS_BW_LIMIT_OUT 3906
646 #define DMI_BW_LIMIT_OUT 3906
647
648 /* Percentage of bus bandwidth reserved for non-periodic transfers */
649 #define FS_BW_RESERVED 10
650 #define HS_BW_RESERVED 20
651 #define SS_BW_RESERVED 10
652
653 struct xhci_virt_ep {
654 struct xhci_virt_device *vdev; /* parent */
655 unsigned int ep_index;
656 struct xhci_ring *ring;
657 /* Related to endpoints that are configured to use stream IDs only */
658 struct xhci_stream_info *stream_info;
659 /* Temporary storage in case the configure endpoint command fails and we
660 * have to restore the device state to the previous state
661 */
662 struct xhci_ring *new_ring;
663 unsigned int err_count;
664 unsigned int ep_state;
665 #define SET_DEQ_PENDING (1 << 0)
666 #define EP_HALTED (1 << 1) /* For stall handling */
667 #define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */
668 /* Transitioning the endpoint to using streams, don't enqueue URBs */
669 #define EP_GETTING_STREAMS (1 << 3)
670 #define EP_HAS_STREAMS (1 << 4)
671 /* Transitioning the endpoint to not using streams, don't enqueue URBs */
672 #define EP_GETTING_NO_STREAMS (1 << 5)
673 #define EP_HARD_CLEAR_TOGGLE (1 << 6)
674 #define EP_SOFT_CLEAR_TOGGLE (1 << 7)
675 /* usb_hub_clear_tt_buffer is in progress */
676 #define EP_CLEARING_TT (1 << 8)
677 /* ---- Related to URB cancellation ---- */
678 struct list_head cancelled_td_list;
679 struct xhci_hcd *xhci;
680 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
681 * command. We'll need to update the ring's dequeue segment and dequeue
682 * pointer after the command completes.
683 */
684 struct xhci_segment *queued_deq_seg;
685 union xhci_trb *queued_deq_ptr;
686 /*
687 * Sometimes the xHC can not process isochronous endpoint ring quickly
688 * enough, and it will miss some isoc tds on the ring and generate
689 * a Missed Service Error Event.
690 * Set skip flag when receive a Missed Service Error Event and
691 * process the missed tds on the endpoint ring.
692 */
693 bool skip;
694 /* Bandwidth checking storage */
695 struct xhci_bw_info bw_info;
696 struct list_head bw_endpoint_list;
697 unsigned long stop_time;
698 /* Isoch Frame ID checking storage */
699 int next_frame_id;
700 /* Use new Isoch TRB layout needed for extended TBC support */
701 bool use_extended_tbc;
702 /* set if this endpoint is controlled via sideband access*/
703 struct xhci_sideband *sideband;
704 };
705
706 enum xhci_overhead_type {
707 LS_OVERHEAD_TYPE = 0,
708 FS_OVERHEAD_TYPE,
709 HS_OVERHEAD_TYPE,
710 };
711
712 struct xhci_interval_bw {
713 unsigned int num_packets;
714 /* Sorted by max packet size.
715 * Head of the list is the greatest max packet size.
716 */
717 struct list_head endpoints;
718 /* How many endpoints of each speed are present. */
719 unsigned int overhead[3];
720 };
721
722 #define XHCI_MAX_INTERVAL 16
723
724 struct xhci_interval_bw_table {
725 unsigned int interval0_esit_payload;
726 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
727 /* Includes reserved bandwidth for async endpoints */
728 unsigned int bw_used;
729 unsigned int ss_bw_in;
730 unsigned int ss_bw_out;
731 };
732
733 #define EP_CTX_PER_DEV 31
734
735 struct xhci_virt_device {
736 int slot_id;
737 struct usb_device *udev;
738 /*
739 * Commands to the hardware are passed an "input context" that
740 * tells the hardware what to change in its data structures.
741 * The hardware will return changes in an "output context" that
742 * software must allocate for the hardware. We need to keep
743 * track of input and output contexts separately because
744 * these commands might fail and we don't trust the hardware.
745 */
746 struct xhci_container_ctx *out_ctx;
747 /* Used for addressing devices and configuration changes */
748 struct xhci_container_ctx *in_ctx;
749 struct xhci_virt_ep eps[EP_CTX_PER_DEV];
750 struct xhci_port *rhub_port;
751 struct xhci_interval_bw_table *bw_table;
752 struct xhci_tt_bw_info *tt_info;
753 /*
754 * flags for state tracking based on events and issued commands.
755 * Software can not rely on states from output contexts because of
756 * latency between events and xHC updating output context values.
757 * See xhci 1.1 section 4.8.3 for more details
758 */
759 unsigned long flags;
760 #define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */
761
762 /* The current max exit latency for the enabled USB3 link states. */
763 u16 current_mel;
764 /* Used for the debugfs interfaces. */
765 void *debugfs_private;
766 /* set if this endpoint is controlled via sideband access*/
767 struct xhci_sideband *sideband;
768 };
769
770 /*
771 * For each roothub, keep track of the bandwidth information for each periodic
772 * interval.
773 *
774 * If a high speed hub is attached to the roothub, each TT associated with that
775 * hub is a separate bandwidth domain. The interval information for the
776 * endpoints on the devices under that TT will appear in the TT structure.
777 */
778 struct xhci_root_port_bw_info {
779 struct list_head tts;
780 unsigned int num_active_tts;
781 struct xhci_interval_bw_table bw_table;
782 };
783
784 struct xhci_tt_bw_info {
785 struct list_head tt_list;
786 int slot_id;
787 int ttport;
788 struct xhci_interval_bw_table bw_table;
789 int active_eps;
790 };
791
792
793 /**
794 * struct xhci_device_context_array
795 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
796 */
797 struct xhci_device_context_array {
798 /* 64-bit device addresses; we only write 32-bit addresses */
799 __le64 dev_context_ptrs[MAX_HC_SLOTS];
800 /* private xHCD pointers */
801 dma_addr_t dma;
802 };
803 /* TODO: write function to set the 64-bit device DMA address */
804 /*
805 * TODO: change this to be dynamically sized at HC mem init time since the HC
806 * might not be able to handle the maximum number of devices possible.
807 */
808
809
810 struct xhci_transfer_event {
811 /* 64-bit buffer address, or immediate data */
812 __le64 buffer;
813 __le32 transfer_len;
814 /* This field is interpreted differently based on the type of TRB */
815 __le32 flags;
816 };
817
818 /* Transfer event flags bitfield, also for select command completion events */
819 #define TRB_TO_SLOT_ID(p) (((p) >> 24) & 0xff)
820 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
821
822 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) /* Endpoint ID 1 - 31 */
823 #define EP_ID_FOR_TRB(p) (((p) & 0x1f) << 16)
824
825 #define TRB_TO_EP_INDEX(p) (TRB_TO_EP_ID(p) - 1) /* Endpoint index 0 - 30 */
826 #define EP_INDEX_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
827
828 /* Transfer event TRB length bit mask */
829 #define EVENT_TRB_LEN(p) ((p) & 0xffffff)
830
831 /* Completion Code - only applicable for some types of TRBs */
832 #define COMP_CODE_MASK (0xff << 24)
833 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
834 #define COMP_INVALID 0
835 #define COMP_SUCCESS 1
836 #define COMP_DATA_BUFFER_ERROR 2
837 #define COMP_BABBLE_DETECTED_ERROR 3
838 #define COMP_USB_TRANSACTION_ERROR 4
839 #define COMP_TRB_ERROR 5
840 #define COMP_STALL_ERROR 6
841 #define COMP_RESOURCE_ERROR 7
842 #define COMP_BANDWIDTH_ERROR 8
843 #define COMP_NO_SLOTS_AVAILABLE_ERROR 9
844 #define COMP_INVALID_STREAM_TYPE_ERROR 10
845 #define COMP_SLOT_NOT_ENABLED_ERROR 11
846 #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
847 #define COMP_SHORT_PACKET 13
848 #define COMP_RING_UNDERRUN 14
849 #define COMP_RING_OVERRUN 15
850 #define COMP_VF_EVENT_RING_FULL_ERROR 16
851 #define COMP_PARAMETER_ERROR 17
852 #define COMP_BANDWIDTH_OVERRUN_ERROR 18
853 #define COMP_CONTEXT_STATE_ERROR 19
854 #define COMP_NO_PING_RESPONSE_ERROR 20
855 #define COMP_EVENT_RING_FULL_ERROR 21
856 #define COMP_INCOMPATIBLE_DEVICE_ERROR 22
857 #define COMP_MISSED_SERVICE_ERROR 23
858 #define COMP_COMMAND_RING_STOPPED 24
859 #define COMP_COMMAND_ABORTED 25
860 #define COMP_STOPPED 26
861 #define COMP_STOPPED_LENGTH_INVALID 27
862 #define COMP_STOPPED_SHORT_PACKET 28
863 #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
864 #define COMP_ISOCH_BUFFER_OVERRUN 31
865 #define COMP_EVENT_LOST_ERROR 32
866 #define COMP_UNDEFINED_ERROR 33
867 #define COMP_INVALID_STREAM_ID_ERROR 34
868 #define COMP_SECONDARY_BANDWIDTH_ERROR 35
869 #define COMP_SPLIT_TRANSACTION_ERROR 36
870
xhci_trb_comp_code_string(u8 status)871 static inline const char *xhci_trb_comp_code_string(u8 status)
872 {
873 switch (status) {
874 case COMP_INVALID:
875 return "Invalid";
876 case COMP_SUCCESS:
877 return "Success";
878 case COMP_DATA_BUFFER_ERROR:
879 return "Data Buffer Error";
880 case COMP_BABBLE_DETECTED_ERROR:
881 return "Babble Detected";
882 case COMP_USB_TRANSACTION_ERROR:
883 return "USB Transaction Error";
884 case COMP_TRB_ERROR:
885 return "TRB Error";
886 case COMP_STALL_ERROR:
887 return "Stall Error";
888 case COMP_RESOURCE_ERROR:
889 return "Resource Error";
890 case COMP_BANDWIDTH_ERROR:
891 return "Bandwidth Error";
892 case COMP_NO_SLOTS_AVAILABLE_ERROR:
893 return "No Slots Available Error";
894 case COMP_INVALID_STREAM_TYPE_ERROR:
895 return "Invalid Stream Type Error";
896 case COMP_SLOT_NOT_ENABLED_ERROR:
897 return "Slot Not Enabled Error";
898 case COMP_ENDPOINT_NOT_ENABLED_ERROR:
899 return "Endpoint Not Enabled Error";
900 case COMP_SHORT_PACKET:
901 return "Short Packet";
902 case COMP_RING_UNDERRUN:
903 return "Ring Underrun";
904 case COMP_RING_OVERRUN:
905 return "Ring Overrun";
906 case COMP_VF_EVENT_RING_FULL_ERROR:
907 return "VF Event Ring Full Error";
908 case COMP_PARAMETER_ERROR:
909 return "Parameter Error";
910 case COMP_BANDWIDTH_OVERRUN_ERROR:
911 return "Bandwidth Overrun Error";
912 case COMP_CONTEXT_STATE_ERROR:
913 return "Context State Error";
914 case COMP_NO_PING_RESPONSE_ERROR:
915 return "No Ping Response Error";
916 case COMP_EVENT_RING_FULL_ERROR:
917 return "Event Ring Full Error";
918 case COMP_INCOMPATIBLE_DEVICE_ERROR:
919 return "Incompatible Device Error";
920 case COMP_MISSED_SERVICE_ERROR:
921 return "Missed Service Error";
922 case COMP_COMMAND_RING_STOPPED:
923 return "Command Ring Stopped";
924 case COMP_COMMAND_ABORTED:
925 return "Command Aborted";
926 case COMP_STOPPED:
927 return "Stopped";
928 case COMP_STOPPED_LENGTH_INVALID:
929 return "Stopped - Length Invalid";
930 case COMP_STOPPED_SHORT_PACKET:
931 return "Stopped - Short Packet";
932 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
933 return "Max Exit Latency Too Large Error";
934 case COMP_ISOCH_BUFFER_OVERRUN:
935 return "Isoch Buffer Overrun";
936 case COMP_EVENT_LOST_ERROR:
937 return "Event Lost Error";
938 case COMP_UNDEFINED_ERROR:
939 return "Undefined Error";
940 case COMP_INVALID_STREAM_ID_ERROR:
941 return "Invalid Stream ID Error";
942 case COMP_SECONDARY_BANDWIDTH_ERROR:
943 return "Secondary Bandwidth Error";
944 case COMP_SPLIT_TRANSACTION_ERROR:
945 return "Split Transaction Error";
946 default:
947 return "Unknown!!";
948 }
949 }
950
951 struct xhci_link_trb {
952 /* 64-bit segment pointer*/
953 __le64 segment_ptr;
954 __le32 intr_target;
955 __le32 control;
956 };
957
958 /* control bitfields */
959 #define LINK_TOGGLE (0x1<<1)
960
961 /* Command completion event TRB */
962 struct xhci_event_cmd {
963 /* Pointer to command TRB, or the value passed by the event data trb */
964 __le64 cmd_trb;
965 __le32 status;
966 __le32 flags;
967 };
968
969 /* Address device - disable SetAddress */
970 #define TRB_BSR (1<<9)
971
972 /* Configure Endpoint - Deconfigure */
973 #define TRB_DC (1<<9)
974
975 /* Stop Ring - Transfer State Preserve */
976 #define TRB_TSP (1<<9)
977
978 enum xhci_ep_reset_type {
979 EP_HARD_RESET,
980 EP_SOFT_RESET,
981 };
982
983 /* Force Event */
984 #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22)
985 #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16)
986
987 /* Set Latency Tolerance Value */
988 #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16)
989
990 /* Get Port Bandwidth */
991 #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16)
992
993 /* Force Header */
994 #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f)
995 #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24)
996
997 enum xhci_setup_dev {
998 SETUP_CONTEXT_ONLY,
999 SETUP_CONTEXT_ADDRESS,
1000 };
1001
1002 /* bits 16:23 are the virtual function ID */
1003 /* bits 24:31 are the slot ID */
1004
1005 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1006 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1007 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1008 #define LAST_EP_INDEX 30
1009
1010 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */
1011 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1012 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1013 #define SCT_FOR_TRB(p) (((p) & 0x7) << 1)
1014
1015 /* Link TRB specific fields */
1016 #define TRB_TC (1<<1)
1017
1018 /* Port Status Change Event TRB fields */
1019 /* Port ID - bits 31:24 */
1020 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1021
1022 #define EVENT_DATA (1 << 2)
1023
1024 /* Normal TRB fields */
1025 /* transfer_len bitmasks - bits 0:16 */
1026 #define TRB_LEN(p) ((p) & 0x1ffff)
1027 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
1028 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
1029 #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17)
1030 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */
1031 #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1032 /* Interrupter Target - which MSI-X vector to target the completion event at */
1033 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1034 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1035 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */
1036 #define TRB_TBC(p) (((p) & 0x3) << 7)
1037 #define TRB_TLBPC(p) (((p) & 0xf) << 16)
1038
1039 /* Cycle bit - indicates TRB ownership by HC or HCD */
1040 #define TRB_CYCLE (1<<0)
1041 /*
1042 * Force next event data TRB to be evaluated before task switch.
1043 * Used to pass OS data back after a TD completes.
1044 */
1045 #define TRB_ENT (1<<1)
1046 /* Interrupt on short packet */
1047 #define TRB_ISP (1<<2)
1048 /* Set PCIe no snoop attribute */
1049 #define TRB_NO_SNOOP (1<<3)
1050 /* Chain multiple TRBs into a TD */
1051 #define TRB_CHAIN (1<<4)
1052 /* Interrupt on completion */
1053 #define TRB_IOC (1<<5)
1054 /* The buffer pointer contains immediate data */
1055 #define TRB_IDT (1<<6)
1056 /* TDs smaller than this might use IDT */
1057 #define TRB_IDT_MAX_SIZE 8
1058
1059 /* Block Event Interrupt */
1060 #define TRB_BEI (1<<9)
1061
1062 /* Control transfer TRB specific fields */
1063 #define TRB_DIR_IN (1<<16)
1064 #define TRB_TX_TYPE(p) ((p) << 16)
1065 #define TRB_DATA_OUT 2
1066 #define TRB_DATA_IN 3
1067
1068 /* Isochronous TRB specific fields */
1069 #define TRB_SIA (1<<31)
1070 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1071
1072 /* TRB cache size for xHC with TRB cache */
1073 #define TRB_CACHE_SIZE_HS 8
1074 #define TRB_CACHE_SIZE_SS 16
1075
1076 struct xhci_generic_trb {
1077 __le32 field[4];
1078 };
1079
1080 union xhci_trb {
1081 struct xhci_link_trb link;
1082 struct xhci_transfer_event trans_event;
1083 struct xhci_event_cmd event_cmd;
1084 struct xhci_generic_trb generic;
1085 };
1086
1087 /* TRB bit mask */
1088 #define TRB_TYPE_BITMASK (0xfc00)
1089 #define TRB_TYPE(p) ((p) << 10)
1090 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1091 /* TRB type IDs */
1092 /* bulk, interrupt, isoc scatter/gather, and control data stage */
1093 #define TRB_NORMAL 1
1094 /* setup stage for control transfers */
1095 #define TRB_SETUP 2
1096 /* data stage for control transfers */
1097 #define TRB_DATA 3
1098 /* status stage for control transfers */
1099 #define TRB_STATUS 4
1100 /* isoc transfers */
1101 #define TRB_ISOC 5
1102 /* TRB for linking ring segments */
1103 #define TRB_LINK 6
1104 #define TRB_EVENT_DATA 7
1105 /* Transfer Ring No-op (not for the command ring) */
1106 #define TRB_TR_NOOP 8
1107 /* Command TRBs */
1108 /* Enable Slot Command */
1109 #define TRB_ENABLE_SLOT 9
1110 /* Disable Slot Command */
1111 #define TRB_DISABLE_SLOT 10
1112 /* Address Device Command */
1113 #define TRB_ADDR_DEV 11
1114 /* Configure Endpoint Command */
1115 #define TRB_CONFIG_EP 12
1116 /* Evaluate Context Command */
1117 #define TRB_EVAL_CONTEXT 13
1118 /* Reset Endpoint Command */
1119 #define TRB_RESET_EP 14
1120 /* Stop Transfer Ring Command */
1121 #define TRB_STOP_RING 15
1122 /* Set Transfer Ring Dequeue Pointer Command */
1123 #define TRB_SET_DEQ 16
1124 /* Reset Device Command */
1125 #define TRB_RESET_DEV 17
1126 /* Force Event Command (opt) */
1127 #define TRB_FORCE_EVENT 18
1128 /* Negotiate Bandwidth Command (opt) */
1129 #define TRB_NEG_BANDWIDTH 19
1130 /* Set Latency Tolerance Value Command (opt) */
1131 #define TRB_SET_LT 20
1132 /* Get port bandwidth Command */
1133 #define TRB_GET_BW 21
1134 /* Force Header Command - generate a transaction or link management packet */
1135 #define TRB_FORCE_HEADER 22
1136 /* No-op Command - not for transfer rings */
1137 #define TRB_CMD_NOOP 23
1138 /* TRB IDs 24-31 reserved */
1139 /* Event TRBS */
1140 /* Transfer Event */
1141 #define TRB_TRANSFER 32
1142 /* Command Completion Event */
1143 #define TRB_COMPLETION 33
1144 /* Port Status Change Event */
1145 #define TRB_PORT_STATUS 34
1146 /* Bandwidth Request Event (opt) */
1147 #define TRB_BANDWIDTH_EVENT 35
1148 /* Doorbell Event (opt) */
1149 #define TRB_DOORBELL 36
1150 /* Host Controller Event */
1151 #define TRB_HC_EVENT 37
1152 /* Device Notification Event - device sent function wake notification */
1153 #define TRB_DEV_NOTE 38
1154 /* MFINDEX Wrap Event - microframe counter wrapped */
1155 #define TRB_MFINDEX_WRAP 39
1156 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1157 #define TRB_VENDOR_DEFINED_LOW 48
1158 /* Nec vendor-specific command completion event. */
1159 #define TRB_NEC_CMD_COMP 48
1160 /* Get NEC firmware revision. */
1161 #define TRB_NEC_GET_FW 49
1162
xhci_trb_type_string(u8 type)1163 static inline const char *xhci_trb_type_string(u8 type)
1164 {
1165 switch (type) {
1166 case TRB_NORMAL:
1167 return "Normal";
1168 case TRB_SETUP:
1169 return "Setup Stage";
1170 case TRB_DATA:
1171 return "Data Stage";
1172 case TRB_STATUS:
1173 return "Status Stage";
1174 case TRB_ISOC:
1175 return "Isoch";
1176 case TRB_LINK:
1177 return "Link";
1178 case TRB_EVENT_DATA:
1179 return "Event Data";
1180 case TRB_TR_NOOP:
1181 return "No-Op";
1182 case TRB_ENABLE_SLOT:
1183 return "Enable Slot Command";
1184 case TRB_DISABLE_SLOT:
1185 return "Disable Slot Command";
1186 case TRB_ADDR_DEV:
1187 return "Address Device Command";
1188 case TRB_CONFIG_EP:
1189 return "Configure Endpoint Command";
1190 case TRB_EVAL_CONTEXT:
1191 return "Evaluate Context Command";
1192 case TRB_RESET_EP:
1193 return "Reset Endpoint Command";
1194 case TRB_STOP_RING:
1195 return "Stop Ring Command";
1196 case TRB_SET_DEQ:
1197 return "Set TR Dequeue Pointer Command";
1198 case TRB_RESET_DEV:
1199 return "Reset Device Command";
1200 case TRB_FORCE_EVENT:
1201 return "Force Event Command";
1202 case TRB_NEG_BANDWIDTH:
1203 return "Negotiate Bandwidth Command";
1204 case TRB_SET_LT:
1205 return "Set Latency Tolerance Value Command";
1206 case TRB_GET_BW:
1207 return "Get Port Bandwidth Command";
1208 case TRB_FORCE_HEADER:
1209 return "Force Header Command";
1210 case TRB_CMD_NOOP:
1211 return "No-Op Command";
1212 case TRB_TRANSFER:
1213 return "Transfer Event";
1214 case TRB_COMPLETION:
1215 return "Command Completion Event";
1216 case TRB_PORT_STATUS:
1217 return "Port Status Change Event";
1218 case TRB_BANDWIDTH_EVENT:
1219 return "Bandwidth Request Event";
1220 case TRB_DOORBELL:
1221 return "Doorbell Event";
1222 case TRB_HC_EVENT:
1223 return "Host Controller Event";
1224 case TRB_DEV_NOTE:
1225 return "Device Notification Event";
1226 case TRB_MFINDEX_WRAP:
1227 return "MFINDEX Wrap Event";
1228 case TRB_NEC_CMD_COMP:
1229 return "NEC Command Completion Event";
1230 case TRB_NEC_GET_FW:
1231 return "NET Get Firmware Revision Command";
1232 default:
1233 return "UNKNOWN";
1234 }
1235 }
1236
1237 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1238 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1239 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1240 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1241 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1242 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1243
1244 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1245 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1246
1247 /*
1248 * TRBS_PER_SEGMENT must be a multiple of 4,
1249 * since the command ring is 64-byte aligned.
1250 * It must also be greater than 16.
1251 */
1252 #define TRBS_PER_SEGMENT 256
1253 /* Allow two commands + a link TRB, along with any reserved command TRBs */
1254 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1255 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1256 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1257 /* TRB buffer pointers can't cross 64KB boundaries */
1258 #define TRB_MAX_BUFF_SHIFT 16
1259 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1260 /* How much data is left before the 64KB boundary? */
1261 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1262 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1263 #define MAX_SOFT_RETRY 3
1264 /*
1265 * Limits of consecutive isoc trbs that can Block Event Interrupt (BEI) if
1266 * XHCI_AVOID_BEI quirk is in use.
1267 */
1268 #define AVOID_BEI_INTERVAL_MIN 8
1269 #define AVOID_BEI_INTERVAL_MAX 32
1270
1271 #define xhci_for_each_ring_seg(head, seg) \
1272 for (seg = head; seg != NULL; seg = (seg->next != head ? seg->next : NULL))
1273
1274 struct xhci_segment {
1275 union xhci_trb *trbs;
1276 /* private to HCD */
1277 struct xhci_segment *next;
1278 unsigned int num;
1279 dma_addr_t dma;
1280 /* Max packet sized bounce buffer for td-fragmant alignment */
1281 dma_addr_t bounce_dma;
1282 void *bounce_buf;
1283 unsigned int bounce_offs;
1284 unsigned int bounce_len;
1285
1286 ANDROID_KABI_RESERVE(1);
1287 };
1288
1289 enum xhci_cancelled_td_status {
1290 TD_DIRTY = 0,
1291 TD_HALTED,
1292 TD_CLEARING_CACHE,
1293 TD_CLEARING_CACHE_DEFERRED,
1294 TD_CLEARED,
1295 };
1296
1297 struct xhci_td {
1298 struct list_head td_list;
1299 struct list_head cancelled_td_list;
1300 int status;
1301 enum xhci_cancelled_td_status cancel_status;
1302 struct urb *urb;
1303 struct xhci_segment *start_seg;
1304 union xhci_trb *first_trb;
1305 union xhci_trb *last_trb;
1306 struct xhci_segment *last_trb_seg;
1307 struct xhci_segment *bounce_seg;
1308 /* actual_length of the URB has already been set */
1309 bool urb_length_set;
1310 bool error_mid_td;
1311 };
1312
1313 /*
1314 * xHCI command default timeout value in milliseconds.
1315 * USB 3.2 spec, section 9.2.6.1
1316 */
1317 #define XHCI_CMD_DEFAULT_TIMEOUT 5000
1318
1319 /* command descriptor */
1320 struct xhci_cd {
1321 struct xhci_command *command;
1322 union xhci_trb *cmd_trb;
1323 };
1324
1325 enum xhci_ring_type {
1326 TYPE_CTRL = 0,
1327 TYPE_ISOC,
1328 TYPE_BULK,
1329 TYPE_INTR,
1330 TYPE_STREAM,
1331 TYPE_COMMAND,
1332 TYPE_EVENT,
1333 };
1334
xhci_ring_type_string(enum xhci_ring_type type)1335 static inline const char *xhci_ring_type_string(enum xhci_ring_type type)
1336 {
1337 switch (type) {
1338 case TYPE_CTRL:
1339 return "CTRL";
1340 case TYPE_ISOC:
1341 return "ISOC";
1342 case TYPE_BULK:
1343 return "BULK";
1344 case TYPE_INTR:
1345 return "INTR";
1346 case TYPE_STREAM:
1347 return "STREAM";
1348 case TYPE_COMMAND:
1349 return "CMD";
1350 case TYPE_EVENT:
1351 return "EVENT";
1352 }
1353
1354 return "UNKNOWN";
1355 }
1356
1357 struct xhci_ring {
1358 struct xhci_segment *first_seg;
1359 struct xhci_segment *last_seg;
1360 union xhci_trb *enqueue;
1361 struct xhci_segment *enq_seg;
1362 union xhci_trb *dequeue;
1363 struct xhci_segment *deq_seg;
1364 struct list_head td_list;
1365 /*
1366 * Write the cycle state into the TRB cycle field to give ownership of
1367 * the TRB to the host controller (if we are the producer), or to check
1368 * if we own the TRB (if we are the consumer). See section 4.9.1.
1369 */
1370 u32 cycle_state;
1371 unsigned int stream_id;
1372 unsigned int num_segs;
1373 unsigned int num_trbs_free; /* used only by xhci DbC */
1374 unsigned int bounce_buf_len;
1375 enum xhci_ring_type type;
1376 bool last_td_was_short;
1377 struct radix_tree_root *trb_address_map;
1378
1379 ANDROID_KABI_RESERVE(1);
1380 ANDROID_KABI_RESERVE(2);
1381 };
1382
1383 struct xhci_erst_entry {
1384 /* 64-bit event ring segment address */
1385 __le64 seg_addr;
1386 __le32 seg_size;
1387 /* Set to zero */
1388 __le32 rsvd;
1389 };
1390
1391 struct xhci_erst {
1392 struct xhci_erst_entry *entries;
1393 unsigned int num_entries;
1394 /* xhci->event_ring keeps track of segment dma addresses */
1395 dma_addr_t erst_dma_addr;
1396 ANDROID_KABI_RESERVE(1);
1397 };
1398
1399 struct xhci_scratchpad {
1400 u64 *sp_array;
1401 dma_addr_t sp_dma;
1402 void **sp_buffers;
1403 };
1404
1405 struct urb_priv {
1406 int num_tds;
1407 int num_tds_done;
1408 struct xhci_td td[] __counted_by(num_tds);
1409 };
1410
1411 /* Number of Event Ring segments to allocate, when amount is not specified. (spec allows 32k) */
1412 #define ERST_DEFAULT_SEGS 2
1413 /* Poll every 60 seconds */
1414 #define POLL_TIMEOUT 60
1415 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1416 #define XHCI_STOP_EP_CMD_TIMEOUT 5
1417 /* XXX: Make these module parameters */
1418
1419 struct s3_save {
1420 u32 command;
1421 u32 dev_nt;
1422 u64 dcbaa_ptr;
1423 u32 config_reg;
1424 };
1425
1426 /* Use for lpm */
1427 struct dev_info {
1428 u32 dev_id;
1429 struct list_head list;
1430 };
1431
1432 struct xhci_bus_state {
1433 unsigned long bus_suspended;
1434 unsigned long next_statechange;
1435
1436 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1437 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1438 u32 port_c_suspend;
1439 u32 suspended_ports;
1440 u32 port_remote_wakeup;
1441 /* which ports have started to resume */
1442 unsigned long resuming_ports;
1443 };
1444
1445 struct xhci_interrupter {
1446 struct xhci_ring *event_ring;
1447 struct xhci_erst erst;
1448 struct xhci_intr_reg __iomem *ir_set;
1449 unsigned int intr_num;
1450 bool ip_autoclear;
1451 u32 isoc_bei_interval;
1452 /* For interrupter registers save and restore over suspend/resume */
1453 u32 s3_irq_pending;
1454 u32 s3_irq_control;
1455 u32 s3_erst_size;
1456 u64 s3_erst_base;
1457 u64 s3_erst_dequeue;
1458 };
1459 /*
1460 * It can take up to 20 ms to transition from RExit to U0 on the
1461 * Intel Lynx Point LP xHCI host.
1462 */
1463 #define XHCI_MAX_REXIT_TIMEOUT_MS 20
1464 struct xhci_port_cap {
1465 u32 *psi; /* array of protocol speed ID entries */
1466 u8 psi_count;
1467 u8 psi_uid_count;
1468 u8 maj_rev;
1469 u8 min_rev;
1470 u32 protocol_caps;
1471 };
1472
1473 struct xhci_port {
1474 __le32 __iomem *addr;
1475 int hw_portnum;
1476 int hcd_portnum;
1477 struct xhci_hub *rhub;
1478 struct xhci_port_cap *port_cap;
1479 unsigned int lpm_incapable:1;
1480 unsigned long resume_timestamp;
1481 bool rexit_active;
1482 /* Slot ID is the index of the device directly connected to the port */
1483 int slot_id;
1484 struct completion rexit_done;
1485 struct completion u3exit_done;
1486 };
1487
1488 struct xhci_hub {
1489 struct xhci_port **ports;
1490 unsigned int num_ports;
1491 struct usb_hcd *hcd;
1492 /* keep track of bus suspend info */
1493 struct xhci_bus_state bus_state;
1494 /* supported prococol extended capabiliy values */
1495 u8 maj_rev;
1496 u8 min_rev;
1497 };
1498
1499 /* There is one xhci_hcd structure per controller */
1500 struct xhci_hcd {
1501 struct usb_hcd *main_hcd;
1502 struct usb_hcd *shared_hcd;
1503 /* glue to PCI and HCD framework */
1504 struct xhci_cap_regs __iomem *cap_regs;
1505 struct xhci_op_regs __iomem *op_regs;
1506 struct xhci_run_regs __iomem *run_regs;
1507 struct xhci_doorbell_array __iomem *dba;
1508
1509 /* Cached register copies of read-only HC data */
1510 __u32 hcs_params1;
1511 __u32 hcs_params2;
1512 __u32 hcs_params3;
1513 __u32 hcc_params;
1514 __u32 hcc_params2;
1515
1516 spinlock_t lock;
1517
1518 /* packed release number */
1519 u16 hci_version;
1520 u16 max_interrupters;
1521 /* imod_interval in ns (I * 250ns) */
1522 u32 imod_interval;
1523 /* 4KB min, 128MB max */
1524 int page_size;
1525 /* Valid values are 12 to 20, inclusive */
1526 int page_shift;
1527 /* MSI-X/MSI vectors */
1528 int nvecs;
1529 /* optional clocks */
1530 struct clk *clk;
1531 struct clk *reg_clk;
1532 /* optional reset controller */
1533 struct reset_control *reset;
1534 /* data structures */
1535 struct xhci_device_context_array *dcbaa;
1536 struct xhci_interrupter **interrupters;
1537 struct xhci_ring *cmd_ring;
1538 unsigned int cmd_ring_state;
1539 #define CMD_RING_STATE_RUNNING (1 << 0)
1540 #define CMD_RING_STATE_ABORTED (1 << 1)
1541 #define CMD_RING_STATE_STOPPED (1 << 2)
1542 struct list_head cmd_list;
1543 unsigned int cmd_ring_reserved_trbs;
1544 struct delayed_work cmd_timer;
1545 struct completion cmd_ring_stop_completion;
1546 struct xhci_command *current_cmd;
1547
1548 /* Scratchpad */
1549 struct xhci_scratchpad *scratchpad;
1550
1551 /* slot enabling and address device helpers */
1552 /* these are not thread safe so use mutex */
1553 struct mutex mutex;
1554 /* Internal mirror of the HW's dcbaa */
1555 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1556 /* For keeping track of bandwidth domains per roothub. */
1557 struct xhci_root_port_bw_info *rh_bw;
1558
1559 /* DMA pools */
1560 struct dma_pool *device_pool;
1561 struct dma_pool *segment_pool;
1562 struct dma_pool *small_streams_pool;
1563 struct dma_pool *medium_streams_pool;
1564
1565 /* Host controller watchdog timer structures */
1566 unsigned int xhc_state;
1567 unsigned long run_graceperiod;
1568 struct s3_save s3;
1569 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1570 *
1571 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1572 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1573 * that sees this status (other than the timer that set it) should stop touching
1574 * hardware immediately. Interrupt handlers should return immediately when
1575 * they see this status (any time they drop and re-acquire xhci->lock).
1576 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1577 * putting the TD on the canceled list, etc.
1578 *
1579 * There are no reports of xHCI host controllers that display this issue.
1580 */
1581 #define XHCI_STATE_DYING (1 << 0)
1582 #define XHCI_STATE_HALTED (1 << 1)
1583 #define XHCI_STATE_REMOVING (1 << 2)
1584 unsigned long long quirks;
1585 #define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1586 #define XHCI_RESET_EP_QUIRK BIT_ULL(1) /* Deprecated */
1587 #define XHCI_NEC_HOST BIT_ULL(2)
1588 #define XHCI_AMD_PLL_FIX BIT_ULL(3)
1589 #define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
1590 /*
1591 * Certain Intel host controllers have a limit to the number of endpoint
1592 * contexts they can handle. Ideally, they would signal that they can't handle
1593 * anymore endpoint contexts by returning a Resource Error for the Configure
1594 * Endpoint command, but they don't. Instead they expect software to keep track
1595 * of the number of active endpoints for them, across configure endpoint
1596 * commands, reset device commands, disable slot commands, and address device
1597 * commands.
1598 */
1599 #define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
1600 #define XHCI_BROKEN_MSI BIT_ULL(6)
1601 #define XHCI_RESET_ON_RESUME BIT_ULL(7)
1602 #define XHCI_SW_BW_CHECKING BIT_ULL(8)
1603 #define XHCI_AMD_0x96_HOST BIT_ULL(9)
1604 #define XHCI_TRUST_TX_LENGTH BIT_ULL(10) /* Deprecated */
1605 #define XHCI_LPM_SUPPORT BIT_ULL(11)
1606 #define XHCI_INTEL_HOST BIT_ULL(12)
1607 #define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
1608 #define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
1609 #define XHCI_AVOID_BEI BIT_ULL(15)
1610 #define XHCI_PLAT BIT_ULL(16) /* Deprecated */
1611 #define XHCI_SLOW_SUSPEND BIT_ULL(17)
1612 #define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
1613 /* For controllers with a broken beyond repair streams implementation */
1614 #define XHCI_BROKEN_STREAMS BIT_ULL(19)
1615 #define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
1616 #define XHCI_MTK_HOST BIT_ULL(21)
1617 #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
1618 #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
1619 #define XHCI_MISSING_CAS BIT_ULL(24)
1620 /* For controller with a broken Port Disable implementation */
1621 #define XHCI_BROKEN_PORT_PED BIT_ULL(25)
1622 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
1623 #define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
1624 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
1625 #define XHCI_HW_LPM_DISABLE BIT_ULL(29)
1626 #define XHCI_SUSPEND_DELAY BIT_ULL(30)
1627 #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
1628 #define XHCI_ZERO_64B_REGS BIT_ULL(32)
1629 #define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33)
1630 #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
1631 #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
1632 /* Reserved. It was XHCI_RENESAS_FW_QUIRK */
1633 #define XHCI_SKIP_PHY_INIT BIT_ULL(37)
1634 #define XHCI_DISABLE_SPARSE BIT_ULL(38)
1635 #define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39)
1636 #define XHCI_NO_SOFT_RETRY BIT_ULL(40)
1637 #define XHCI_BROKEN_D3COLD_S2I BIT_ULL(41)
1638 #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42)
1639 #define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43)
1640 #define XHCI_RESET_TO_DEFAULT BIT_ULL(44)
1641 #define XHCI_TRB_OVERFETCH BIT_ULL(45)
1642 #define XHCI_ZHAOXIN_HOST BIT_ULL(46)
1643 #define XHCI_WRITE_64_HI_LO BIT_ULL(47)
1644 #define XHCI_CDNS_SCTX_QUIRK BIT_ULL(48)
1645 #define XHCI_ETRON_HOST BIT_ULL(49)
1646 #define XHCI_LIMIT_ENDPOINT_INTERVAL_9 BIT_ULL(50)
1647
1648 unsigned int num_active_eps;
1649 unsigned int limit_active_eps;
1650 struct xhci_port *hw_ports;
1651 struct xhci_hub usb2_rhub;
1652 struct xhci_hub usb3_rhub;
1653 /* support xHCI 1.0 spec USB2 hardware LPM */
1654 unsigned hw_lpm_support:1;
1655 /* Broken Suspend flag for SNPS Suspend resume issue */
1656 unsigned broken_suspend:1;
1657 /* Indicates that omitting hcd is supported if root hub has no ports */
1658 unsigned allow_single_roothub:1;
1659 /* cached extended protocol port capabilities */
1660 struct xhci_port_cap *port_caps;
1661 unsigned int num_port_caps;
1662 /* Compliance Mode Recovery Data */
1663 struct timer_list comp_mode_recovery_timer;
1664 u32 port_status_u0;
1665 u16 test_mode;
1666 /* Compliance Mode Timer Triggered every 2 seconds */
1667 #define COMP_MODE_RCVRY_MSECS 2000
1668
1669 struct dentry *debugfs_root;
1670 struct dentry *debugfs_slots;
1671 struct list_head regset_list;
1672
1673 void *dbc;
1674
1675 ANDROID_KABI_RESERVE(1);
1676 ANDROID_KABI_RESERVE(2);
1677 ANDROID_KABI_RESERVE(3);
1678 ANDROID_KABI_RESERVE(4);
1679
1680 /* platform-specific data -- must come last */
1681 unsigned long priv[] __aligned(sizeof(s64));
1682 };
1683
1684 /* Platform specific overrides to generic XHCI hc_driver ops */
1685 struct xhci_driver_overrides {
1686 size_t extra_priv_size;
1687 int (*reset)(struct usb_hcd *hcd);
1688 int (*start)(struct usb_hcd *hcd);
1689 int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1690 struct usb_host_endpoint *ep);
1691 int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1692 struct usb_host_endpoint *ep);
1693 int (*check_bandwidth)(struct usb_hcd *, struct usb_device *);
1694 void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);
1695 int (*update_hub_device)(struct usb_hcd *hcd, struct usb_device *hdev,
1696 struct usb_tt *tt, gfp_t mem_flags);
1697 int (*hub_control)(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1698 u16 wIndex, char *buf, u16 wLength);
1699
1700 ANDROID_KABI_RESERVE(1);
1701 ANDROID_KABI_RESERVE(2);
1702 ANDROID_KABI_RESERVE(3);
1703 ANDROID_KABI_RESERVE(4);
1704 };
1705
1706 #define XHCI_CFC_DELAY 10
1707
1708 /* convert between an HCD pointer and the corresponding EHCI_HCD */
hcd_to_xhci(struct usb_hcd * hcd)1709 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1710 {
1711 struct usb_hcd *primary_hcd;
1712
1713 if (usb_hcd_is_primary_hcd(hcd))
1714 primary_hcd = hcd;
1715 else
1716 primary_hcd = hcd->primary_hcd;
1717
1718 return (struct xhci_hcd *) (primary_hcd->hcd_priv);
1719 }
1720
xhci_to_hcd(struct xhci_hcd * xhci)1721 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1722 {
1723 return xhci->main_hcd;
1724 }
1725
xhci_get_usb3_hcd(struct xhci_hcd * xhci)1726 static inline struct usb_hcd *xhci_get_usb3_hcd(struct xhci_hcd *xhci)
1727 {
1728 if (xhci->shared_hcd)
1729 return xhci->shared_hcd;
1730
1731 if (!xhci->usb2_rhub.num_ports)
1732 return xhci->main_hcd;
1733
1734 return NULL;
1735 }
1736
xhci_hcd_is_usb3(struct usb_hcd * hcd)1737 static inline bool xhci_hcd_is_usb3(struct usb_hcd *hcd)
1738 {
1739 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1740
1741 return hcd == xhci_get_usb3_hcd(xhci);
1742 }
1743
xhci_has_one_roothub(struct xhci_hcd * xhci)1744 static inline bool xhci_has_one_roothub(struct xhci_hcd *xhci)
1745 {
1746 return xhci->allow_single_roothub &&
1747 (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports);
1748 }
1749
1750 #define xhci_dbg(xhci, fmt, args...) \
1751 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1752 #define xhci_err(xhci, fmt, args...) \
1753 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1754 #define xhci_warn(xhci, fmt, args...) \
1755 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1756 #define xhci_info(xhci, fmt, args...) \
1757 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1758
1759 /*
1760 * Registers should always be accessed with double word or quad word accesses.
1761 *
1762 * Some xHCI implementations may support 64-bit address pointers. Registers
1763 * with 64-bit address pointers should be written to with dword accesses by
1764 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1765 * xHCI implementations that do not support 64-bit address pointers will ignore
1766 * the high dword, and write order is irrelevant.
1767 */
xhci_read_64(const struct xhci_hcd * xhci,__le64 __iomem * regs)1768 static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1769 __le64 __iomem *regs)
1770 {
1771 return lo_hi_readq(regs);
1772 }
xhci_write_64(struct xhci_hcd * xhci,const u64 val,__le64 __iomem * regs)1773 static inline void xhci_write_64(struct xhci_hcd *xhci,
1774 const u64 val, __le64 __iomem *regs)
1775 {
1776 lo_hi_writeq(val, regs);
1777 }
1778
1779
1780 /*
1781 * Reportedly, some chapters of v0.95 spec said that Link TRB always has its chain bit set.
1782 * Other chapters and later specs say that it should only be set if the link is inside a TD
1783 * which continues from the end of one segment to the next segment.
1784 *
1785 * Some 0.95 hardware was found to misbehave if any link TRB doesn't have the chain bit set.
1786 *
1787 * 0.96 hardware from AMD and NEC was found to ignore unchained isochronous link TRBs when
1788 * "resynchronizing the pipe" after a Missed Service Error.
1789 */
xhci_link_chain_quirk(struct xhci_hcd * xhci,enum xhci_ring_type type)1790 static inline bool xhci_link_chain_quirk(struct xhci_hcd *xhci, enum xhci_ring_type type)
1791 {
1792 return (xhci->quirks & XHCI_LINK_TRB_QUIRK) ||
1793 (type == TYPE_ISOC && (xhci->quirks & (XHCI_AMD_0x96_HOST | XHCI_NEC_HOST)));
1794 }
1795
1796 /* xHCI debugging */
1797 char *xhci_get_slot_state(struct xhci_hcd *xhci,
1798 struct xhci_container_ctx *ctx);
1799 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
1800 const char *fmt, ...);
1801
1802 /* xHCI memory management */
1803 void xhci_mem_cleanup(struct xhci_hcd *xhci);
1804 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1805 void xhci_free_virt_device(struct xhci_hcd *xhci, struct xhci_virt_device *dev, int slot_id);
1806 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1807 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1808 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1809 struct usb_device *udev);
1810 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1811 unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1812 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1813 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1814 struct xhci_virt_device *virt_dev,
1815 int old_active_eps);
1816 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1817 void xhci_update_bw_info(struct xhci_hcd *xhci,
1818 struct xhci_container_ctx *in_ctx,
1819 struct xhci_input_control_ctx *ctrl_ctx,
1820 struct xhci_virt_device *virt_dev);
1821 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1822 struct xhci_container_ctx *in_ctx,
1823 struct xhci_container_ctx *out_ctx,
1824 unsigned int ep_index);
1825 void xhci_slot_copy(struct xhci_hcd *xhci,
1826 struct xhci_container_ctx *in_ctx,
1827 struct xhci_container_ctx *out_ctx);
1828 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1829 struct usb_device *udev, struct usb_host_endpoint *ep,
1830 gfp_t mem_flags);
1831 struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, unsigned int num_segs,
1832 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags);
1833 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1834 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
1835 unsigned int num_trbs, gfp_t flags);
1836 void xhci_initialize_ring_info(struct xhci_ring *ring);
1837 void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
1838 struct xhci_virt_device *virt_dev,
1839 unsigned int ep_index);
1840 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1841 unsigned int num_stream_ctxs,
1842 unsigned int num_streams,
1843 unsigned int max_packet, gfp_t flags);
1844 void xhci_free_stream_info(struct xhci_hcd *xhci,
1845 struct xhci_stream_info *stream_info);
1846 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1847 struct xhci_ep_ctx *ep_ctx,
1848 struct xhci_stream_info *stream_info);
1849 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
1850 struct xhci_virt_ep *ep);
1851 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
1852 struct xhci_virt_device *virt_dev, bool drop_control_ep);
1853 struct xhci_ring *xhci_dma_to_transfer_ring(
1854 struct xhci_virt_ep *ep,
1855 u64 address);
1856 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1857 bool allocate_completion, gfp_t mem_flags);
1858 struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
1859 bool allocate_completion, gfp_t mem_flags);
1860 void xhci_urb_free_priv(struct urb_priv *urb_priv);
1861 void xhci_free_command(struct xhci_hcd *xhci,
1862 struct xhci_command *command);
1863 struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
1864 int type, gfp_t flags);
1865 void xhci_free_container_ctx(struct xhci_hcd *xhci,
1866 struct xhci_container_ctx *ctx);
1867 struct xhci_interrupter *
1868 xhci_create_secondary_interrupter(struct usb_hcd *hcd, unsigned int segs,
1869 u32 imod_interval, unsigned int intr_num);
1870 void xhci_remove_secondary_interrupter(struct usb_hcd
1871 *hcd, struct xhci_interrupter *ir);
1872 void xhci_skip_sec_intr_events(struct xhci_hcd *xhci,
1873 struct xhci_ring *ring,
1874 struct xhci_interrupter *ir);
1875
1876 /* xHCI host controller glue */
1877 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
1878 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us);
1879 void xhci_quiesce(struct xhci_hcd *xhci);
1880 int xhci_halt(struct xhci_hcd *xhci);
1881 int xhci_start(struct xhci_hcd *xhci);
1882 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us);
1883 int xhci_run(struct usb_hcd *hcd);
1884 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
1885 void xhci_shutdown(struct usb_hcd *hcd);
1886 void xhci_stop(struct usb_hcd *hcd);
1887 void xhci_init_driver(struct hc_driver *drv,
1888 const struct xhci_driver_overrides *over);
1889 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1890 struct usb_host_endpoint *ep);
1891 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1892 struct usb_host_endpoint *ep);
1893 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1894 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1895 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1896 struct usb_tt *tt, gfp_t mem_flags);
1897 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
1898 int xhci_disable_and_free_slot(struct xhci_hcd *xhci, u32 slot_id);
1899 int xhci_ext_cap_init(struct xhci_hcd *xhci);
1900
1901 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
1902 int xhci_resume(struct xhci_hcd *xhci, pm_message_t msg);
1903
1904 irqreturn_t xhci_irq(struct usb_hcd *hcd);
1905 irqreturn_t xhci_msi_irq(int irq, void *hcd);
1906 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1907 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
1908 struct xhci_virt_device *virt_dev,
1909 struct usb_device *hdev,
1910 struct usb_tt *tt, gfp_t mem_flags);
1911 int xhci_set_interrupter_moderation(struct xhci_interrupter *ir,
1912 u32 imod_interval);
1913 int xhci_enable_interrupter(struct xhci_interrupter *ir);
1914 int xhci_disable_interrupter(struct xhci_interrupter *ir);
1915
1916 /* xHCI ring, segment, TRB, and TD functions */
1917 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1918 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, struct xhci_td *td,
1919 dma_addr_t suspect_dma, bool debug);
1920 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1921 void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1922 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
1923 u32 trb_type, u32 slot_id);
1924 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
1925 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
1926 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
1927 u32 field1, u32 field2, u32 field3, u32 field4);
1928 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
1929 int slot_id, unsigned int ep_index, int suspend);
1930 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1931 int slot_id, unsigned int ep_index);
1932 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1933 int slot_id, unsigned int ep_index);
1934 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1935 int slot_id, unsigned int ep_index);
1936 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1937 struct urb *urb, int slot_id, unsigned int ep_index);
1938 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
1939 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
1940 bool command_must_succeed);
1941 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
1942 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
1943 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
1944 int slot_id, unsigned int ep_index,
1945 enum xhci_ep_reset_type reset_type);
1946 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
1947 u32 slot_id);
1948 void xhci_handle_command_timeout(struct work_struct *work);
1949
1950 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
1951 unsigned int ep_index, unsigned int stream_id);
1952 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
1953 unsigned int slot_id,
1954 unsigned int ep_index);
1955 void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
1956 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring);
1957 unsigned int count_trbs(u64 addr, u64 len);
1958 int xhci_stop_endpoint_sync(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
1959 int suspend, gfp_t gfp_flags);
1960 void xhci_process_cancelled_tds(struct xhci_virt_ep *ep);
1961 void xhci_update_erst_dequeue(struct xhci_hcd *xhci,
1962 struct xhci_interrupter *ir,
1963 bool clear_ehb);
1964
1965 /* xHCI roothub code */
1966 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
1967 u32 link_state);
1968 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
1969 u32 port_bit);
1970 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1971 char *buf, u16 wLength);
1972 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1973 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
1974 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd);
1975 enum usb_link_tunnel_mode xhci_port_is_tunneled(struct xhci_hcd *xhci,
1976 struct xhci_port *port);
1977 void xhci_hc_died(struct xhci_hcd *xhci);
1978
1979 #ifdef CONFIG_PM
1980 int xhci_bus_suspend(struct usb_hcd *hcd);
1981 int xhci_bus_resume(struct usb_hcd *hcd);
1982 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd);
1983 #else
1984 #define xhci_bus_suspend NULL
1985 #define xhci_bus_resume NULL
1986 #define xhci_get_resuming_ports NULL
1987 #endif /* CONFIG_PM */
1988
1989 u32 xhci_port_state_to_neutral(u32 state);
1990 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
1991
1992 /* xHCI contexts */
1993 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
1994 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1995 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1996
1997 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
1998 unsigned int slot_id, unsigned int ep_index,
1999 unsigned int stream_id);
2000
xhci_urb_to_transfer_ring(struct xhci_hcd * xhci,struct urb * urb)2001 static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
2002 struct urb *urb)
2003 {
2004 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
2005 xhci_get_endpoint_index(&urb->ep->desc),
2006 urb->stream_id);
2007 }
2008
2009 /*
2010 * TODO: As per spec Isochronous IDT transmissions are supported. We bypass
2011 * them anyways as we where unable to find a device that matches the
2012 * constraints.
2013 */
xhci_urb_suitable_for_idt(struct urb * urb)2014 static inline bool xhci_urb_suitable_for_idt(struct urb *urb)
2015 {
2016 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) &&
2017 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE &&
2018 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE &&
2019 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) &&
2020 !urb->num_sgs)
2021 return true;
2022
2023 return false;
2024 }
2025
xhci_slot_state_string(u32 state)2026 static inline char *xhci_slot_state_string(u32 state)
2027 {
2028 switch (state) {
2029 case SLOT_STATE_ENABLED:
2030 return "enabled/disabled";
2031 case SLOT_STATE_DEFAULT:
2032 return "default";
2033 case SLOT_STATE_ADDRESSED:
2034 return "addressed";
2035 case SLOT_STATE_CONFIGURED:
2036 return "configured";
2037 default:
2038 return "reserved";
2039 }
2040 }
2041
xhci_decode_trb(char * str,size_t size,u32 field0,u32 field1,u32 field2,u32 field3)2042 static inline const char *xhci_decode_trb(char *str, size_t size,
2043 u32 field0, u32 field1, u32 field2, u32 field3)
2044 {
2045 int type = TRB_FIELD_TO_TYPE(field3);
2046
2047 switch (type) {
2048 case TRB_LINK:
2049 snprintf(str, size,
2050 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c",
2051 field1, field0, GET_INTR_TARGET(field2),
2052 xhci_trb_type_string(type),
2053 field3 & TRB_IOC ? 'I' : 'i',
2054 field3 & TRB_CHAIN ? 'C' : 'c',
2055 field3 & TRB_TC ? 'T' : 't',
2056 field3 & TRB_CYCLE ? 'C' : 'c');
2057 break;
2058 case TRB_TRANSFER:
2059 case TRB_COMPLETION:
2060 case TRB_PORT_STATUS:
2061 case TRB_BANDWIDTH_EVENT:
2062 case TRB_DOORBELL:
2063 case TRB_HC_EVENT:
2064 case TRB_DEV_NOTE:
2065 case TRB_MFINDEX_WRAP:
2066 snprintf(str, size,
2067 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c",
2068 field1, field0,
2069 xhci_trb_comp_code_string(GET_COMP_CODE(field2)),
2070 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3),
2071 TRB_TO_EP_ID(field3),
2072 xhci_trb_type_string(type),
2073 field3 & EVENT_DATA ? 'E' : 'e',
2074 field3 & TRB_CYCLE ? 'C' : 'c');
2075
2076 break;
2077 case TRB_SETUP:
2078 snprintf(str, size,
2079 "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c",
2080 field0 & 0xff,
2081 (field0 & 0xff00) >> 8,
2082 (field0 & 0xff000000) >> 24,
2083 (field0 & 0xff0000) >> 16,
2084 (field1 & 0xff00) >> 8,
2085 field1 & 0xff,
2086 (field1 & 0xff000000) >> 16 |
2087 (field1 & 0xff0000) >> 16,
2088 TRB_LEN(field2), GET_TD_SIZE(field2),
2089 GET_INTR_TARGET(field2),
2090 xhci_trb_type_string(type),
2091 field3 & TRB_IDT ? 'I' : 'i',
2092 field3 & TRB_IOC ? 'I' : 'i',
2093 field3 & TRB_CYCLE ? 'C' : 'c');
2094 break;
2095 case TRB_DATA:
2096 snprintf(str, size,
2097 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c",
2098 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2099 GET_INTR_TARGET(field2),
2100 xhci_trb_type_string(type),
2101 field3 & TRB_IDT ? 'I' : 'i',
2102 field3 & TRB_IOC ? 'I' : 'i',
2103 field3 & TRB_CHAIN ? 'C' : 'c',
2104 field3 & TRB_NO_SNOOP ? 'S' : 's',
2105 field3 & TRB_ISP ? 'I' : 'i',
2106 field3 & TRB_ENT ? 'E' : 'e',
2107 field3 & TRB_CYCLE ? 'C' : 'c');
2108 break;
2109 case TRB_STATUS:
2110 snprintf(str, size,
2111 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c",
2112 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2113 GET_INTR_TARGET(field2),
2114 xhci_trb_type_string(type),
2115 field3 & TRB_IOC ? 'I' : 'i',
2116 field3 & TRB_CHAIN ? 'C' : 'c',
2117 field3 & TRB_ENT ? 'E' : 'e',
2118 field3 & TRB_CYCLE ? 'C' : 'c');
2119 break;
2120 case TRB_NORMAL:
2121 case TRB_ISOC:
2122 case TRB_EVENT_DATA:
2123 case TRB_TR_NOOP:
2124 snprintf(str, size,
2125 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c",
2126 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2127 GET_INTR_TARGET(field2),
2128 xhci_trb_type_string(type),
2129 field3 & TRB_BEI ? 'B' : 'b',
2130 field3 & TRB_IDT ? 'I' : 'i',
2131 field3 & TRB_IOC ? 'I' : 'i',
2132 field3 & TRB_CHAIN ? 'C' : 'c',
2133 field3 & TRB_NO_SNOOP ? 'S' : 's',
2134 field3 & TRB_ISP ? 'I' : 'i',
2135 field3 & TRB_ENT ? 'E' : 'e',
2136 field3 & TRB_CYCLE ? 'C' : 'c');
2137 break;
2138
2139 case TRB_CMD_NOOP:
2140 case TRB_ENABLE_SLOT:
2141 snprintf(str, size,
2142 "%s: flags %c",
2143 xhci_trb_type_string(type),
2144 field3 & TRB_CYCLE ? 'C' : 'c');
2145 break;
2146 case TRB_DISABLE_SLOT:
2147 case TRB_NEG_BANDWIDTH:
2148 snprintf(str, size,
2149 "%s: slot %d flags %c",
2150 xhci_trb_type_string(type),
2151 TRB_TO_SLOT_ID(field3),
2152 field3 & TRB_CYCLE ? 'C' : 'c');
2153 break;
2154 case TRB_ADDR_DEV:
2155 snprintf(str, size,
2156 "%s: ctx %08x%08x slot %d flags %c:%c",
2157 xhci_trb_type_string(type),
2158 field1, field0,
2159 TRB_TO_SLOT_ID(field3),
2160 field3 & TRB_BSR ? 'B' : 'b',
2161 field3 & TRB_CYCLE ? 'C' : 'c');
2162 break;
2163 case TRB_CONFIG_EP:
2164 snprintf(str, size,
2165 "%s: ctx %08x%08x slot %d flags %c:%c",
2166 xhci_trb_type_string(type),
2167 field1, field0,
2168 TRB_TO_SLOT_ID(field3),
2169 field3 & TRB_DC ? 'D' : 'd',
2170 field3 & TRB_CYCLE ? 'C' : 'c');
2171 break;
2172 case TRB_EVAL_CONTEXT:
2173 snprintf(str, size,
2174 "%s: ctx %08x%08x slot %d flags %c",
2175 xhci_trb_type_string(type),
2176 field1, field0,
2177 TRB_TO_SLOT_ID(field3),
2178 field3 & TRB_CYCLE ? 'C' : 'c');
2179 break;
2180 case TRB_RESET_EP:
2181 snprintf(str, size,
2182 "%s: ctx %08x%08x slot %d ep %d flags %c:%c",
2183 xhci_trb_type_string(type),
2184 field1, field0,
2185 TRB_TO_SLOT_ID(field3),
2186 TRB_TO_EP_ID(field3),
2187 field3 & TRB_TSP ? 'T' : 't',
2188 field3 & TRB_CYCLE ? 'C' : 'c');
2189 break;
2190 case TRB_STOP_RING:
2191 snprintf(str, size,
2192 "%s: slot %d sp %d ep %d flags %c",
2193 xhci_trb_type_string(type),
2194 TRB_TO_SLOT_ID(field3),
2195 TRB_TO_SUSPEND_PORT(field3),
2196 TRB_TO_EP_ID(field3),
2197 field3 & TRB_CYCLE ? 'C' : 'c');
2198 break;
2199 case TRB_SET_DEQ:
2200 snprintf(str, size,
2201 "%s: deq %08x%08x stream %d slot %d ep %d flags %c",
2202 xhci_trb_type_string(type),
2203 field1, field0,
2204 TRB_TO_STREAM_ID(field2),
2205 TRB_TO_SLOT_ID(field3),
2206 TRB_TO_EP_ID(field3),
2207 field3 & TRB_CYCLE ? 'C' : 'c');
2208 break;
2209 case TRB_RESET_DEV:
2210 snprintf(str, size,
2211 "%s: slot %d flags %c",
2212 xhci_trb_type_string(type),
2213 TRB_TO_SLOT_ID(field3),
2214 field3 & TRB_CYCLE ? 'C' : 'c');
2215 break;
2216 case TRB_FORCE_EVENT:
2217 snprintf(str, size,
2218 "%s: event %08x%08x vf intr %d vf id %d flags %c",
2219 xhci_trb_type_string(type),
2220 field1, field0,
2221 TRB_TO_VF_INTR_TARGET(field2),
2222 TRB_TO_VF_ID(field3),
2223 field3 & TRB_CYCLE ? 'C' : 'c');
2224 break;
2225 case TRB_SET_LT:
2226 snprintf(str, size,
2227 "%s: belt %d flags %c",
2228 xhci_trb_type_string(type),
2229 TRB_TO_BELT(field3),
2230 field3 & TRB_CYCLE ? 'C' : 'c');
2231 break;
2232 case TRB_GET_BW:
2233 snprintf(str, size,
2234 "%s: ctx %08x%08x slot %d speed %d flags %c",
2235 xhci_trb_type_string(type),
2236 field1, field0,
2237 TRB_TO_SLOT_ID(field3),
2238 TRB_TO_DEV_SPEED(field3),
2239 field3 & TRB_CYCLE ? 'C' : 'c');
2240 break;
2241 case TRB_FORCE_HEADER:
2242 snprintf(str, size,
2243 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c",
2244 xhci_trb_type_string(type),
2245 field2, field1, field0 & 0xffffffe0,
2246 TRB_TO_PACKET_TYPE(field0),
2247 TRB_TO_ROOTHUB_PORT(field3),
2248 field3 & TRB_CYCLE ? 'C' : 'c');
2249 break;
2250 default:
2251 snprintf(str, size,
2252 "type '%s' -> raw %08x %08x %08x %08x",
2253 xhci_trb_type_string(type),
2254 field0, field1, field2, field3);
2255 }
2256
2257 return str;
2258 }
2259
xhci_decode_ctrl_ctx(char * str,unsigned long drop,unsigned long add)2260 static inline const char *xhci_decode_ctrl_ctx(char *str,
2261 unsigned long drop, unsigned long add)
2262 {
2263 unsigned int bit;
2264 int ret = 0;
2265
2266 str[0] = '\0';
2267
2268 if (drop) {
2269 ret = sprintf(str, "Drop:");
2270 for_each_set_bit(bit, &drop, 32)
2271 ret += sprintf(str + ret, " %d%s",
2272 bit / 2,
2273 bit % 2 ? "in":"out");
2274 ret += sprintf(str + ret, ", ");
2275 }
2276
2277 if (add) {
2278 ret += sprintf(str + ret, "Add:%s%s",
2279 (add & SLOT_FLAG) ? " slot":"",
2280 (add & EP0_FLAG) ? " ep0":"");
2281 add &= ~(SLOT_FLAG | EP0_FLAG);
2282 for_each_set_bit(bit, &add, 32)
2283 ret += sprintf(str + ret, " %d%s",
2284 bit / 2,
2285 bit % 2 ? "in":"out");
2286 }
2287 return str;
2288 }
2289
xhci_decode_slot_context(char * str,u32 info,u32 info2,u32 tt_info,u32 state)2290 static inline const char *xhci_decode_slot_context(char *str,
2291 u32 info, u32 info2, u32 tt_info, u32 state)
2292 {
2293 u32 speed;
2294 u32 hub;
2295 u32 mtt;
2296 int ret = 0;
2297
2298 speed = info & DEV_SPEED;
2299 hub = info & DEV_HUB;
2300 mtt = info & DEV_MTT;
2301
2302 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d",
2303 info & ROUTE_STRING_MASK,
2304 ({ char *s;
2305 switch (speed) {
2306 case SLOT_SPEED_FS:
2307 s = "full-speed";
2308 break;
2309 case SLOT_SPEED_LS:
2310 s = "low-speed";
2311 break;
2312 case SLOT_SPEED_HS:
2313 s = "high-speed";
2314 break;
2315 case SLOT_SPEED_SS:
2316 s = "super-speed";
2317 break;
2318 case SLOT_SPEED_SSP:
2319 s = "super-speed plus";
2320 break;
2321 default:
2322 s = "UNKNOWN speed";
2323 } s; }),
2324 mtt ? " multi-TT" : "",
2325 hub ? " Hub" : "",
2326 (info & LAST_CTX_MASK) >> 27,
2327 info2 & MAX_EXIT,
2328 DEVINFO_TO_ROOT_HUB_PORT(info2),
2329 DEVINFO_TO_MAX_PORTS(info2));
2330
2331 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s",
2332 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8,
2333 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info),
2334 state & DEV_ADDR_MASK,
2335 xhci_slot_state_string(GET_SLOT_STATE(state)));
2336
2337 return str;
2338 }
2339
2340
xhci_portsc_link_state_string(u32 portsc)2341 static inline const char *xhci_portsc_link_state_string(u32 portsc)
2342 {
2343 switch (portsc & PORT_PLS_MASK) {
2344 case XDEV_U0:
2345 return "U0";
2346 case XDEV_U1:
2347 return "U1";
2348 case XDEV_U2:
2349 return "U2";
2350 case XDEV_U3:
2351 return "U3";
2352 case XDEV_DISABLED:
2353 return "Disabled";
2354 case XDEV_RXDETECT:
2355 return "RxDetect";
2356 case XDEV_INACTIVE:
2357 return "Inactive";
2358 case XDEV_POLLING:
2359 return "Polling";
2360 case XDEV_RECOVERY:
2361 return "Recovery";
2362 case XDEV_HOT_RESET:
2363 return "Hot Reset";
2364 case XDEV_COMP_MODE:
2365 return "Compliance mode";
2366 case XDEV_TEST_MODE:
2367 return "Test mode";
2368 case XDEV_RESUME:
2369 return "Resume";
2370 default:
2371 break;
2372 }
2373 return "Unknown";
2374 }
2375
xhci_decode_portsc(char * str,u32 portsc)2376 static inline const char *xhci_decode_portsc(char *str, u32 portsc)
2377 {
2378 int ret;
2379
2380 ret = sprintf(str, "0x%08x ", portsc);
2381
2382 if (portsc == ~(u32)0)
2383 return str;
2384
2385 ret += sprintf(str + ret, "%s %s %s Link:%s PortSpeed:%d ",
2386 portsc & PORT_POWER ? "Powered" : "Powered-off",
2387 portsc & PORT_CONNECT ? "Connected" : "Not-connected",
2388 portsc & PORT_PE ? "Enabled" : "Disabled",
2389 xhci_portsc_link_state_string(portsc),
2390 DEV_PORT_SPEED(portsc));
2391
2392 if (portsc & PORT_OC)
2393 ret += sprintf(str + ret, "OverCurrent ");
2394 if (portsc & PORT_RESET)
2395 ret += sprintf(str + ret, "In-Reset ");
2396
2397 ret += sprintf(str + ret, "Change: ");
2398 if (portsc & PORT_CSC)
2399 ret += sprintf(str + ret, "CSC ");
2400 if (portsc & PORT_PEC)
2401 ret += sprintf(str + ret, "PEC ");
2402 if (portsc & PORT_WRC)
2403 ret += sprintf(str + ret, "WRC ");
2404 if (portsc & PORT_OCC)
2405 ret += sprintf(str + ret, "OCC ");
2406 if (portsc & PORT_RC)
2407 ret += sprintf(str + ret, "PRC ");
2408 if (portsc & PORT_PLC)
2409 ret += sprintf(str + ret, "PLC ");
2410 if (portsc & PORT_CEC)
2411 ret += sprintf(str + ret, "CEC ");
2412 if (portsc & PORT_CAS)
2413 ret += sprintf(str + ret, "CAS ");
2414
2415 ret += sprintf(str + ret, "Wake: ");
2416 if (portsc & PORT_WKCONN_E)
2417 ret += sprintf(str + ret, "WCE ");
2418 if (portsc & PORT_WKDISC_E)
2419 ret += sprintf(str + ret, "WDE ");
2420 if (portsc & PORT_WKOC_E)
2421 ret += sprintf(str + ret, "WOE ");
2422
2423 return str;
2424 }
2425
xhci_decode_usbsts(char * str,u32 usbsts)2426 static inline const char *xhci_decode_usbsts(char *str, u32 usbsts)
2427 {
2428 int ret = 0;
2429
2430 ret = sprintf(str, " 0x%08x", usbsts);
2431
2432 if (usbsts == ~(u32)0)
2433 return str;
2434
2435 if (usbsts & STS_HALT)
2436 ret += sprintf(str + ret, " HCHalted");
2437 if (usbsts & STS_FATAL)
2438 ret += sprintf(str + ret, " HSE");
2439 if (usbsts & STS_EINT)
2440 ret += sprintf(str + ret, " EINT");
2441 if (usbsts & STS_PORT)
2442 ret += sprintf(str + ret, " PCD");
2443 if (usbsts & STS_SAVE)
2444 ret += sprintf(str + ret, " SSS");
2445 if (usbsts & STS_RESTORE)
2446 ret += sprintf(str + ret, " RSS");
2447 if (usbsts & STS_SRE)
2448 ret += sprintf(str + ret, " SRE");
2449 if (usbsts & STS_CNR)
2450 ret += sprintf(str + ret, " CNR");
2451 if (usbsts & STS_HCE)
2452 ret += sprintf(str + ret, " HCE");
2453
2454 return str;
2455 }
2456
xhci_decode_doorbell(char * str,u32 slot,u32 doorbell)2457 static inline const char *xhci_decode_doorbell(char *str, u32 slot, u32 doorbell)
2458 {
2459 u8 ep;
2460 u16 stream;
2461 int ret;
2462
2463 ep = (doorbell & 0xff);
2464 stream = doorbell >> 16;
2465
2466 if (slot == 0) {
2467 sprintf(str, "Command Ring %d", doorbell);
2468 return str;
2469 }
2470 ret = sprintf(str, "Slot %d ", slot);
2471 if (ep > 0 && ep < 32)
2472 ret = sprintf(str + ret, "ep%d%s",
2473 ep / 2,
2474 ep % 2 ? "in" : "out");
2475 else if (ep == 0 || ep < 248)
2476 ret = sprintf(str + ret, "Reserved %d", ep);
2477 else
2478 ret = sprintf(str + ret, "Vendor Defined %d", ep);
2479 if (stream)
2480 ret = sprintf(str + ret, " Stream %d", stream);
2481
2482 return str;
2483 }
2484
xhci_ep_state_string(u8 state)2485 static inline const char *xhci_ep_state_string(u8 state)
2486 {
2487 switch (state) {
2488 case EP_STATE_DISABLED:
2489 return "disabled";
2490 case EP_STATE_RUNNING:
2491 return "running";
2492 case EP_STATE_HALTED:
2493 return "halted";
2494 case EP_STATE_STOPPED:
2495 return "stopped";
2496 case EP_STATE_ERROR:
2497 return "error";
2498 default:
2499 return "INVALID";
2500 }
2501 }
2502
xhci_ep_type_string(u8 type)2503 static inline const char *xhci_ep_type_string(u8 type)
2504 {
2505 switch (type) {
2506 case ISOC_OUT_EP:
2507 return "Isoc OUT";
2508 case BULK_OUT_EP:
2509 return "Bulk OUT";
2510 case INT_OUT_EP:
2511 return "Int OUT";
2512 case CTRL_EP:
2513 return "Ctrl";
2514 case ISOC_IN_EP:
2515 return "Isoc IN";
2516 case BULK_IN_EP:
2517 return "Bulk IN";
2518 case INT_IN_EP:
2519 return "Int IN";
2520 default:
2521 return "INVALID";
2522 }
2523 }
2524
xhci_decode_ep_context(char * str,u32 info,u32 info2,u64 deq,u32 tx_info)2525 static inline const char *xhci_decode_ep_context(char *str, u32 info,
2526 u32 info2, u64 deq, u32 tx_info)
2527 {
2528 int ret;
2529
2530 u32 esit;
2531 u16 maxp;
2532 u16 avg;
2533
2534 u8 max_pstr;
2535 u8 ep_state;
2536 u8 interval;
2537 u8 ep_type;
2538 u8 burst;
2539 u8 cerr;
2540 u8 mult;
2541
2542 bool lsa;
2543 bool hid;
2544
2545 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 |
2546 CTX_TO_MAX_ESIT_PAYLOAD(tx_info);
2547
2548 ep_state = info & EP_STATE_MASK;
2549 max_pstr = CTX_TO_EP_MAXPSTREAMS(info);
2550 interval = CTX_TO_EP_INTERVAL(info);
2551 mult = CTX_TO_EP_MULT(info) + 1;
2552 lsa = !!(info & EP_HAS_LSA);
2553
2554 cerr = (info2 & (3 << 1)) >> 1;
2555 ep_type = CTX_TO_EP_TYPE(info2);
2556 hid = !!(info2 & (1 << 7));
2557 burst = CTX_TO_MAX_BURST(info2);
2558 maxp = MAX_PACKET_DECODED(info2);
2559
2560 avg = EP_AVG_TRB_LENGTH(tx_info);
2561
2562 ret = sprintf(str, "State %s mult %d max P. Streams %d %s",
2563 xhci_ep_state_string(ep_state), mult,
2564 max_pstr, lsa ? "LSA " : "");
2565
2566 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ",
2567 (1 << interval) * 125, esit, cerr);
2568
2569 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ",
2570 xhci_ep_type_string(ep_type), hid ? "HID" : "",
2571 burst, maxp, deq);
2572
2573 ret += sprintf(str + ret, "avg trb len %d", avg);
2574
2575 return str;
2576 }
2577
2578 #endif /* __LINUX_XHCI_HCD_H */
2579