1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _CORE_TYPES_H_ 27 #define _CORE_TYPES_H_ 28 29 #include "dc.h" 30 #include "dce_calcs.h" 31 #include "dcn_calcs.h" 32 #include "ddc_service_types.h" 33 #include "dc_bios_types.h" 34 #include "mem_input.h" 35 #include "hubp.h" 36 #include "mpc.h" 37 #include "dwb.h" 38 #include "mcif_wb.h" 39 #include "panel_cntl.h" 40 #include "dmub/inc/dmub_cmd.h" 41 #include "pg_cntl.h" 42 #include "spl/dc_spl.h" 43 44 #define MAX_CLOCK_SOURCES 7 45 #define MAX_SVP_PHANTOM_STREAMS 2 46 #define MAX_SVP_PHANTOM_PLANES 2 47 48 void enable_surface_flip_reporting(struct dc_plane_state *plane_state, 49 uint32_t controller_id); 50 51 #include "grph_object_id.h" 52 #include "link_encoder.h" 53 #include "stream_encoder.h" 54 #include "clock_source.h" 55 #include "audio.h" 56 #include "dm_pp_smu.h" 57 #include "dm_cp_psp.h" 58 #include "link_hwss.h" 59 60 /********** DAL Core*********************/ 61 #include "transform.h" 62 #include "dpp.h" 63 64 #include "dml2/dml21/inc/dml_top_dchub_registers.h" 65 #include "dml2/dml21/inc/dml_top_types.h" 66 67 struct resource_pool; 68 struct dc_state; 69 struct resource_context; 70 struct clk_bw_params; 71 72 struct resource_funcs { 73 enum engine_id (*get_preferred_eng_id_dpia)(unsigned int dpia_index); 74 void (*destroy)(struct resource_pool **pool); 75 void (*link_init)(struct dc_link *link); 76 struct panel_cntl*(*panel_cntl_create)( 77 const struct panel_cntl_init_data *panel_cntl_init_data); 78 struct link_encoder *(*link_enc_create)( 79 struct dc_context *ctx, 80 const struct encoder_init_data *init); 81 /* Create a minimal link encoder object with no dc_link object 82 * associated with it. */ 83 struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx, enum engine_id eng_id); 84 85 bool (*validate_bandwidth)( 86 struct dc *dc, 87 struct dc_state *context, 88 bool fast_validate); 89 void (*calculate_wm_and_dlg)( 90 struct dc *dc, struct dc_state *context, 91 display_e2e_pipe_params_st *pipes, 92 int pipe_cnt, 93 int vlevel); 94 void (*update_soc_for_wm_a)( 95 struct dc *dc, struct dc_state *context); 96 97 unsigned int (*calculate_mall_ways_from_bytes)( 98 const struct dc *dc, 99 unsigned int total_size_in_mall_bytes); 100 void (*prepare_mcache_programming)( 101 struct dc *dc, 102 struct dc_state *context); 103 /** 104 * @populate_dml_pipes - Populate pipe data struct 105 * 106 * Returns: 107 * Total of pipes available in the specific ASIC. 108 */ 109 int (*populate_dml_pipes)( 110 struct dc *dc, 111 struct dc_state *context, 112 display_e2e_pipe_params_st *pipes, 113 bool fast_validate); 114 115 /* 116 * Algorithm for assigning available link encoders to links. 117 * 118 * Update link_enc_assignments table and link_enc_avail list accordingly in 119 * struct resource_context. 120 */ 121 void (*link_encs_assign)( 122 struct dc *dc, 123 struct dc_state *state, 124 struct dc_stream_state *streams[], 125 uint8_t stream_count); 126 /* 127 * Unassign a link encoder from a stream. 128 * 129 * Update link_enc_assignments table and link_enc_avail list accordingly in 130 * struct resource_context. 131 */ 132 void (*link_enc_unassign)( 133 struct dc_state *state, 134 struct dc_stream_state *stream); 135 136 enum dc_status (*validate_global)( 137 struct dc *dc, 138 struct dc_state *context); 139 140 struct pipe_ctx *(*acquire_free_pipe_as_secondary_dpp_pipe)( 141 const struct dc_state *cur_ctx, 142 struct dc_state *new_ctx, 143 const struct resource_pool *pool, 144 const struct pipe_ctx *opp_head_pipe); 145 146 struct pipe_ctx *(*acquire_free_pipe_as_secondary_opp_head)( 147 const struct dc_state *cur_ctx, 148 struct dc_state *new_ctx, 149 const struct resource_pool *pool, 150 const struct pipe_ctx *otg_master); 151 152 void (*release_pipe)(struct dc_state *context, 153 struct pipe_ctx *pipe, 154 const struct resource_pool *pool); 155 156 enum dc_status (*validate_plane)( 157 const struct dc_plane_state *plane_state, 158 struct dc_caps *caps); 159 160 enum dc_status (*add_stream_to_ctx)( 161 struct dc *dc, 162 struct dc_state *new_ctx, 163 struct dc_stream_state *dc_stream); 164 165 enum dc_status (*remove_stream_from_ctx)( 166 struct dc *dc, 167 struct dc_state *new_ctx, 168 struct dc_stream_state *stream); 169 170 enum dc_status (*patch_unknown_plane_state)( 171 struct dc_plane_state *plane_state); 172 173 struct stream_encoder *(*find_first_free_match_stream_enc_for_link)( 174 struct resource_context *res_ctx, 175 const struct resource_pool *pool, 176 struct dc_stream_state *stream); 177 178 void (*populate_dml_writeback_from_context)( 179 struct dc *dc, 180 struct resource_context *res_ctx, 181 display_e2e_pipe_params_st *pipes); 182 183 void (*set_mcif_arb_params)( 184 struct dc *dc, 185 struct dc_state *context, 186 display_e2e_pipe_params_st *pipes, 187 int pipe_cnt); 188 189 void (*update_bw_bounding_box)( 190 struct dc *dc, 191 struct clk_bw_params *bw_params); 192 bool (*acquire_post_bldn_3dlut)( 193 struct resource_context *res_ctx, 194 const struct resource_pool *pool, 195 int mpcc_id, 196 struct dc_3dlut **lut, 197 struct dc_transfer_func **shaper); 198 199 bool (*release_post_bldn_3dlut)( 200 struct resource_context *res_ctx, 201 const struct resource_pool *pool, 202 struct dc_3dlut **lut, 203 struct dc_transfer_func **shaper); 204 205 enum dc_status (*add_dsc_to_stream_resource)( 206 struct dc *dc, struct dc_state *state, 207 struct dc_stream_state *stream); 208 209 void (*add_phantom_pipes)( 210 struct dc *dc, 211 struct dc_state *context, 212 display_e2e_pipe_params_st *pipes, 213 unsigned int pipe_cnt, 214 unsigned int index); 215 216 void (*get_panel_config_defaults)(struct dc_panel_config *panel_config); 217 void (*build_pipe_pix_clk_params)(struct pipe_ctx *pipe_ctx); 218 unsigned int (*get_det_buffer_size)(const struct dc_state *context); 219 }; 220 221 struct audio_support{ 222 bool dp_audio; 223 bool hdmi_audio_on_dongle; 224 bool hdmi_audio_native; 225 }; 226 227 #define NO_UNDERLAY_PIPE -1 228 229 struct resource_pool { 230 struct mem_input *mis[MAX_PIPES]; 231 struct hubp *hubps[MAX_PIPES]; 232 struct input_pixel_processor *ipps[MAX_PIPES]; 233 struct transform *transforms[MAX_PIPES]; 234 struct dpp *dpps[MAX_PIPES]; 235 struct output_pixel_processor *opps[MAX_PIPES]; 236 struct timing_generator *timing_generators[MAX_PIPES]; 237 struct stream_encoder *stream_enc[MAX_PIPES * 2]; 238 struct hubbub *hubbub; 239 struct mpc *mpc; 240 struct pp_smu_funcs *pp_smu; 241 struct dce_aux *engines[MAX_PIPES]; 242 struct dce_i2c_hw *hw_i2cs[MAX_PIPES]; 243 struct dce_i2c_sw *sw_i2cs[MAX_PIPES]; 244 bool i2c_hw_buffer_in_use; 245 246 struct dwbc *dwbc[MAX_DWB_PIPES]; 247 struct mcif_wb *mcif_wb[MAX_DWB_PIPES]; 248 struct { 249 unsigned int gsl_0:1; 250 unsigned int gsl_1:1; 251 unsigned int gsl_2:1; 252 } gsl_groups; 253 254 struct display_stream_compressor *dscs[MAX_PIPES]; 255 256 unsigned int pipe_count; 257 unsigned int underlay_pipe_index; 258 unsigned int stream_enc_count; 259 260 /* An array for accessing the link encoder objects that have been created. 261 * Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA 262 */ 263 struct link_encoder *link_encoders[MAX_DIG_LINK_ENCODERS]; 264 /* Number of DIG link encoder objects created - i.e. number of valid 265 * entries in link_encoders array. 266 */ 267 unsigned int dig_link_enc_count; 268 /* Number of USB4 DPIA (DisplayPort Input Adapter) link objects created.*/ 269 unsigned int usb4_dpia_count; 270 271 unsigned int hpo_dp_stream_enc_count; 272 struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS]; 273 unsigned int hpo_dp_link_enc_count; 274 struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS]; 275 struct dc_3dlut *mpc_lut[MAX_PIPES]; 276 struct dc_transfer_func *mpc_shaper[MAX_PIPES]; 277 278 struct { 279 unsigned int xtalin_clock_inKhz; 280 unsigned int dccg_ref_clock_inKhz; 281 unsigned int dchub_ref_clock_inKhz; 282 } ref_clocks; 283 unsigned int timing_generator_count; 284 unsigned int mpcc_count; 285 286 unsigned int writeback_pipe_count; 287 /* 288 * reserved clock source for DP 289 */ 290 struct clock_source *dp_clock_source; 291 292 struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 293 unsigned int clk_src_count; 294 295 struct audio *audios[MAX_AUDIOS]; 296 unsigned int audio_count; 297 struct audio_support audio_support; 298 299 struct dccg *dccg; 300 struct pg_cntl *pg_cntl; 301 struct irq_service *irqs; 302 303 struct abm *abm; 304 struct dmcu *dmcu; 305 struct dmub_psr *psr; 306 struct dmub_replay *replay; 307 308 struct abm *multiple_abms[MAX_PIPES]; 309 310 const struct resource_funcs *funcs; 311 const struct resource_caps *res_cap; 312 313 struct ddc_service *oem_device; 314 }; 315 316 struct dcn_fe_bandwidth { 317 int dppclk_khz; 318 319 }; 320 321 /* Parameters needed to call set_disp_pattern_generator */ 322 struct test_pattern_params { 323 enum controller_dp_test_pattern test_pattern; 324 enum controller_dp_color_space color_space; 325 enum dc_color_depth color_depth; 326 int width; 327 int height; 328 int offset; 329 }; 330 331 struct stream_resource { 332 struct output_pixel_processor *opp; 333 struct display_stream_compressor *dsc; 334 struct timing_generator *tg; 335 struct stream_encoder *stream_enc; 336 struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 337 struct audio *audio; 338 339 struct pixel_clk_params pix_clk_params; 340 struct encoder_info_frame encoder_info_frame; 341 342 struct abm *abm; 343 /* There are only (num_pipes+1)/2 groups. 0 means unassigned, 344 * otherwise it's using group number 'gsl_group-1' 345 */ 346 uint8_t gsl_group; 347 348 struct test_pattern_params test_pattern_params; 349 }; 350 351 struct plane_resource { 352 /* scl_data is scratch space required to program a plane */ 353 struct scaler_data scl_data; 354 /* Below pointers to hw objects are required to enable the plane */ 355 /* spl_in and spl_out are the input and output structures for SPL 356 * which are required when using Scaler Programming Library 357 * these are scratch spaces needed when programming a plane 358 */ 359 struct spl_in spl_in; 360 struct spl_out spl_out; 361 /* Below pointers to hw objects are required to enable the plane */ 362 struct hubp *hubp; 363 struct mem_input *mi; 364 struct input_pixel_processor *ipp; 365 struct transform *xfm; 366 struct dpp *dpp; 367 uint8_t mpcc_inst; 368 369 struct dcn_fe_bandwidth bw; 370 }; 371 372 #define LINK_RES_HPO_DP_REC_MAP__MASK 0xFFFF 373 #define LINK_RES_HPO_DP_REC_MAP__SHIFT 0 374 375 /* all mappable hardware resources used to enable a link */ 376 struct link_resource { 377 struct hpo_dp_link_encoder *hpo_dp_link_enc; 378 }; 379 380 struct link_config { 381 struct dc_link_settings dp_link_settings; 382 }; 383 union pipe_update_flags { 384 struct { 385 uint32_t enable : 1; 386 uint32_t disable : 1; 387 uint32_t odm : 1; 388 uint32_t global_sync : 1; 389 uint32_t opp_changed : 1; 390 uint32_t tg_changed : 1; 391 uint32_t mpcc : 1; 392 uint32_t dppclk : 1; 393 uint32_t hubp_interdependent : 1; 394 uint32_t hubp_rq_dlg_ttu : 1; 395 uint32_t gamut_remap : 1; 396 uint32_t scaler : 1; 397 uint32_t viewport : 1; 398 uint32_t plane_changed : 1; 399 uint32_t det_size : 1; 400 uint32_t unbounded_req : 1; 401 uint32_t test_pattern_changed : 1; 402 } bits; 403 uint32_t raw; 404 }; 405 406 struct pixel_rate_divider { 407 uint32_t div_factor1; 408 uint32_t div_factor2; 409 }; 410 411 enum p_state_switch_method { 412 P_STATE_UNKNOWN = 0, 413 P_STATE_V_BLANK = 1, 414 P_STATE_FPO, 415 P_STATE_V_ACTIVE, 416 P_STATE_SUB_VP, 417 P_STATE_DRR_SUB_VP, 418 P_STATE_V_BLANK_SUB_VP 419 }; 420 421 struct pipe_ctx { 422 struct dc_plane_state *plane_state; 423 struct dc_stream_state *stream; 424 425 struct plane_resource plane_res; 426 427 /** 428 * @stream_res: Reference to DCN resource components such OPP and DSC. 429 */ 430 struct stream_resource stream_res; 431 struct link_resource link_res; 432 433 struct clock_source *clock_source; 434 435 struct pll_settings pll_settings; 436 437 /** 438 * @link_config: 439 * 440 * link config records software decision for what link config should be 441 * enabled given current link capability and stream during hw resource 442 * mapping. This is to decouple the dependency on link capability during 443 * dc commit or update. 444 */ 445 struct link_config link_config; 446 447 uint8_t pipe_idx; 448 uint8_t pipe_idx_syncd; 449 450 struct pipe_ctx *top_pipe; 451 struct pipe_ctx *bottom_pipe; 452 struct pipe_ctx *next_odm_pipe; 453 struct pipe_ctx *prev_odm_pipe; 454 455 struct _vcs_dpi_display_dlg_regs_st dlg_regs; 456 struct _vcs_dpi_display_ttu_regs_st ttu_regs; 457 struct _vcs_dpi_display_rq_regs_st rq_regs; 458 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 459 struct _vcs_dpi_display_rq_params_st dml_rq_param; 460 struct _vcs_dpi_display_dlg_sys_params_st dml_dlg_sys_param; 461 struct _vcs_dpi_display_e2e_pipe_params_st dml_input; 462 int det_buffer_size_kb; 463 bool unbounded_req; 464 unsigned int surface_size_in_mall_bytes; 465 struct dml2_dchub_per_pipe_register_set hubp_regs; 466 struct dml2_hubp_pipe_mcache_regs mcache_regs; 467 468 struct dwbc *dwbc; 469 struct mcif_wb *mcif_wb; 470 union pipe_update_flags update_flags; 471 enum p_state_switch_method p_state_type; 472 struct tg_color visual_confirm_color; 473 bool has_vactive_margin; 474 /* subvp_index: only valid if the pipe is a SUBVP_MAIN*/ 475 uint8_t subvp_index; 476 struct pixel_rate_divider pixel_rate_divider; 477 }; 478 479 /* Data used for dynamic link encoder assignment. 480 * Tracks current and future assignments; available link encoders; 481 * and mode of operation (whether to use current or future assignments). 482 */ 483 struct link_enc_cfg_context { 484 enum link_enc_cfg_mode mode; 485 struct link_enc_assignment link_enc_assignments[MAX_PIPES]; 486 enum engine_id link_enc_avail[MAX_DIG_LINK_ENCODERS]; 487 struct link_enc_assignment transient_assignments[MAX_PIPES]; 488 }; 489 490 struct resource_context { 491 struct pipe_ctx pipe_ctx[MAX_PIPES]; 492 bool is_stream_enc_acquired[MAX_PIPES * 2]; 493 bool is_audio_acquired[MAX_PIPES]; 494 uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 495 uint8_t dp_clock_source_ref_count; 496 bool is_dsc_acquired[MAX_PIPES]; 497 struct link_enc_cfg_context link_enc_cfg_ctx; 498 bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS]; 499 unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS]; 500 int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS]; 501 bool is_mpc_3dlut_acquired[MAX_PIPES]; 502 /* solely used for build scalar data in dml2 */ 503 struct pipe_ctx temp_pipe; 504 }; 505 506 struct dce_bw_output { 507 bool cpuc_state_change_enable; 508 bool cpup_state_change_enable; 509 bool stutter_mode_enable; 510 bool nbp_state_change_enable; 511 bool all_displays_in_sync; 512 struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 513 struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 514 struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES]; 515 struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 516 int sclk_khz; 517 int sclk_deep_sleep_khz; 518 int yclk_khz; 519 int dispclk_khz; 520 int blackout_recovery_time_us; 521 }; 522 523 struct dcn_bw_writeback { 524 struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES]; 525 }; 526 527 struct dcn_bw_output { 528 struct dc_clocks clk; 529 union dcn_watermark_set watermarks; 530 struct dcn_bw_writeback bw_writeback; 531 int compbuf_size_kb; 532 unsigned int mall_ss_size_bytes; 533 unsigned int mall_ss_psr_active_size_bytes; 534 unsigned int mall_subvp_size_bytes; 535 unsigned int legacy_svp_drr_stream_index; 536 bool legacy_svp_drr_stream_index_valid; 537 struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES]; 538 struct dmub_cmd_fams2_global_config fams2_global_config; 539 struct dmub_fams2_stream_static_state fams2_stream_params[DML2_MAX_PLANES]; 540 struct dml2_display_arb_regs arb_regs; 541 }; 542 543 union bw_output { 544 struct dcn_bw_output dcn; 545 struct dce_bw_output dce; 546 }; 547 548 struct bw_context { 549 union bw_output bw; 550 struct display_mode_lib dml; 551 struct dml2_context *dml2; 552 struct dml2_context *dml2_dc_power_source; 553 }; 554 555 struct dc_dmub_cmd { 556 union dmub_rb_cmd dmub_cmd; 557 enum dm_dmub_wait_type wait_type; 558 }; 559 560 /** 561 * struct dc_state - The full description of a state requested by users 562 */ 563 struct dc_state { 564 /** 565 * @streams: Stream state properties 566 */ 567 struct dc_stream_state *streams[MAX_PIPES]; 568 569 /** 570 * @stream_status: Planes status on a given stream 571 */ 572 struct dc_stream_status stream_status[MAX_PIPES]; 573 /** 574 * @phantom_streams: Stream state properties for phantoms 575 */ 576 struct dc_stream_state *phantom_streams[MAX_PHANTOM_PIPES]; 577 /** 578 * @phantom_planes: Planes state properties for phantoms 579 */ 580 struct dc_plane_state *phantom_planes[MAX_PHANTOM_PIPES]; 581 582 /** 583 * @stream_count: Total of streams in use 584 */ 585 uint8_t stream_count; 586 uint8_t stream_mask; 587 588 /** 589 * @stream_count: Total phantom streams in use 590 */ 591 uint8_t phantom_stream_count; 592 /** 593 * @stream_count: Total phantom planes in use 594 */ 595 uint8_t phantom_plane_count; 596 /** 597 * @res_ctx: Persistent state of resources 598 */ 599 struct resource_context res_ctx; 600 601 /** 602 * @pp_display_cfg: PowerPlay clocks and settings 603 * Note: this is a big struct, do *not* put on stack! 604 */ 605 struct dm_pp_display_configuration pp_display_cfg; 606 607 /** 608 * @dcn_bw_vars: non-stack memory to support bandwidth calculations 609 * Note: this is a big struct, do *not* put on stack! 610 */ 611 struct dcn_bw_internal_vars dcn_bw_vars; 612 613 struct clk_mgr *clk_mgr; 614 615 /** 616 * @bw_ctx: The output from bandwidth and watermark calculations and the DML 617 * 618 * Each context must have its own instance of VBA, and in order to 619 * initialize and obtain IP and SOC, the base DML instance from DC is 620 * initially copied into every context. 621 */ 622 struct bw_context bw_ctx; 623 624 struct block_sequence block_sequence[100]; 625 unsigned int block_sequence_steps; 626 struct dc_dmub_cmd dc_dmub_cmd[10]; 627 unsigned int dmub_cmd_count; 628 629 /** 630 * @refcount: refcount reference 631 * 632 * Notice that dc_state is used around the code to capture the current 633 * context, so we need to pass it everywhere. That's why we want to use 634 * kref in this struct. 635 */ 636 struct kref refcount; 637 638 struct { 639 unsigned int stutter_period_us; 640 } perf_params; 641 642 enum dc_power_source_type power_source; 643 }; 644 645 struct replay_context { 646 /* ddc line */ 647 enum channel_id aux_inst; 648 /* Transmitter id */ 649 enum transmitter digbe_inst; 650 /* Engine Id is used for Dig Be source select */ 651 enum engine_id digfe_inst; 652 /* Controller Id used for Dig Fe source select */ 653 enum controller_id controllerId; 654 unsigned int line_time_in_ns; 655 }; 656 657 enum dc_replay_enable { 658 DC_REPLAY_DISABLE = 0, 659 DC_REPLAY_ENABLE = 1, 660 }; 661 662 struct dc_bounding_box_max_clk { 663 int max_dcfclk_mhz; 664 int max_dispclk_mhz; 665 int max_dppclk_mhz; 666 int max_phyclk_mhz; 667 }; 668 669 #endif /* _CORE_TYPES_H_ */ 670