1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright IBM Corp. 2012
4 *
5 * Author(s):
6 * Jan Glauber <jang@linux.vnet.ibm.com>
7 */
8
9 #define KMSG_COMPONENT "zpci"
10 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
11
12 #include <linux/compat.h>
13 #include <linux/kernel.h>
14 #include <linux/miscdevice.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/delay.h>
18 #include <linux/pci.h>
19 #include <linux/uaccess.h>
20 #include <asm/asm-extable.h>
21 #include <asm/pci_debug.h>
22 #include <asm/pci_clp.h>
23 #include <asm/clp.h>
24 #include <uapi/asm/clp.h>
25
26 #include "pci_bus.h"
27
28 bool zpci_unique_uid;
29
update_uid_checking(bool new)30 void update_uid_checking(bool new)
31 {
32 if (zpci_unique_uid != new)
33 zpci_dbg(3, "uid checking:%d\n", new);
34
35 zpci_unique_uid = new;
36 }
37
zpci_err_clp(unsigned int rsp,int rc)38 static inline void zpci_err_clp(unsigned int rsp, int rc)
39 {
40 struct {
41 unsigned int rsp;
42 int rc;
43 } __packed data = {rsp, rc};
44
45 zpci_err_hex(&data, sizeof(data));
46 }
47
48 /*
49 * Call Logical Processor with c=1, lps=0 and command 1
50 * to get the bit mask of installed logical processors
51 */
clp_get_ilp(unsigned long * ilp)52 static inline int clp_get_ilp(unsigned long *ilp)
53 {
54 unsigned long mask;
55 int cc = 3;
56
57 asm volatile (
58 " .insn rrf,0xb9a00000,%[mask],%[cmd],8,0\n"
59 "0: ipm %[cc]\n"
60 " srl %[cc],28\n"
61 "1:\n"
62 EX_TABLE(0b, 1b)
63 : [cc] "+d" (cc), [mask] "=d" (mask) : [cmd] "a" (1)
64 : "cc");
65 *ilp = mask;
66 return cc;
67 }
68
69 /*
70 * Call Logical Processor with c=0, the give constant lps and an lpcb request.
71 */
clp_req(void * data,unsigned int lps)72 static __always_inline int clp_req(void *data, unsigned int lps)
73 {
74 struct { u8 _[CLP_BLK_SIZE]; } *req = data;
75 u64 ignored;
76 int cc = 3;
77
78 asm volatile (
79 " .insn rrf,0xb9a00000,%[ign],%[req],0,%[lps]\n"
80 "0: ipm %[cc]\n"
81 " srl %[cc],28\n"
82 "1:\n"
83 EX_TABLE(0b, 1b)
84 : [cc] "+d" (cc), [ign] "=d" (ignored), "+m" (*req)
85 : [req] "a" (req), [lps] "i" (lps)
86 : "cc");
87 return cc;
88 }
89
clp_alloc_block(gfp_t gfp_mask)90 static void *clp_alloc_block(gfp_t gfp_mask)
91 {
92 return (void *) __get_free_pages(gfp_mask, get_order(CLP_BLK_SIZE));
93 }
94
clp_free_block(void * ptr)95 static void clp_free_block(void *ptr)
96 {
97 free_pages((unsigned long) ptr, get_order(CLP_BLK_SIZE));
98 }
99
clp_store_query_pci_fngrp(struct zpci_dev * zdev,struct clp_rsp_query_pci_grp * response)100 static void clp_store_query_pci_fngrp(struct zpci_dev *zdev,
101 struct clp_rsp_query_pci_grp *response)
102 {
103 zdev->tlb_refresh = response->refresh;
104 zdev->dma_mask = response->dasm;
105 zdev->msi_addr = response->msia;
106 zdev->max_msi = response->noi;
107 zdev->fmb_update = response->mui;
108 zdev->version = response->version;
109 zdev->maxstbl = response->maxstbl;
110 zdev->dtsm = response->dtsm;
111
112 switch (response->version) {
113 case 1:
114 zdev->max_bus_speed = PCIE_SPEED_5_0GT;
115 break;
116 default:
117 zdev->max_bus_speed = PCI_SPEED_UNKNOWN;
118 break;
119 }
120 }
121
clp_query_pci_fngrp(struct zpci_dev * zdev,u8 pfgid)122 static int clp_query_pci_fngrp(struct zpci_dev *zdev, u8 pfgid)
123 {
124 struct clp_req_rsp_query_pci_grp *rrb;
125 int rc;
126
127 rrb = clp_alloc_block(GFP_KERNEL);
128 if (!rrb)
129 return -ENOMEM;
130
131 memset(rrb, 0, sizeof(*rrb));
132 rrb->request.hdr.len = sizeof(rrb->request);
133 rrb->request.hdr.cmd = CLP_QUERY_PCI_FNGRP;
134 rrb->response.hdr.len = sizeof(rrb->response);
135 rrb->request.pfgid = pfgid;
136
137 rc = clp_req(rrb, CLP_LPS_PCI);
138 if (!rc && rrb->response.hdr.rsp == CLP_RC_OK)
139 clp_store_query_pci_fngrp(zdev, &rrb->response);
140 else {
141 zpci_err("Q PCI FGRP:\n");
142 zpci_err_clp(rrb->response.hdr.rsp, rc);
143 rc = -EIO;
144 }
145 clp_free_block(rrb);
146 return rc;
147 }
148
clp_store_query_pci_fn(struct zpci_dev * zdev,struct clp_rsp_query_pci * response)149 static int clp_store_query_pci_fn(struct zpci_dev *zdev,
150 struct clp_rsp_query_pci *response)
151 {
152 int i;
153
154 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
155 zdev->bars[i].val = le32_to_cpu(response->bar[i]);
156 zdev->bars[i].size = response->bar_size[i];
157 }
158 zdev->start_dma = response->sdma;
159 zdev->end_dma = response->edma;
160 zdev->pchid = response->pchid;
161 zdev->pfgid = response->pfgid;
162 zdev->pft = response->pft;
163 zdev->vfn = response->vfn;
164 zdev->port = response->port;
165 zdev->uid = response->uid;
166 zdev->fmb_length = sizeof(u32) * response->fmb_len;
167 zdev->is_physfn = response->is_physfn;
168 zdev->rid_available = response->rid_avail;
169 if (zdev->rid_available)
170 zdev->rid = response->rid;
171 zdev->tid_avail = response->tid_avail;
172 if (zdev->tid_avail)
173 zdev->tid = response->tid;
174
175 memcpy(zdev->pfip, response->pfip, sizeof(zdev->pfip));
176 if (response->util_str_avail) {
177 memcpy(zdev->util_str, response->util_str,
178 sizeof(zdev->util_str));
179 zdev->util_str_avail = 1;
180 }
181 zdev->mio_capable = response->mio_addr_avail;
182 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
183 if (!(response->mio.valid & (1 << (PCI_STD_NUM_BARS - i - 1))))
184 continue;
185
186 zdev->bars[i].mio_wb = (void __iomem *) response->mio.addr[i].wb;
187 zdev->bars[i].mio_wt = (void __iomem *) response->mio.addr[i].wt;
188 }
189 return 0;
190 }
191
clp_query_pci_fn(struct zpci_dev * zdev)192 int clp_query_pci_fn(struct zpci_dev *zdev)
193 {
194 struct clp_req_rsp_query_pci *rrb;
195 int rc;
196
197 rrb = clp_alloc_block(GFP_KERNEL);
198 if (!rrb)
199 return -ENOMEM;
200
201 memset(rrb, 0, sizeof(*rrb));
202 rrb->request.hdr.len = sizeof(rrb->request);
203 rrb->request.hdr.cmd = CLP_QUERY_PCI_FN;
204 rrb->response.hdr.len = sizeof(rrb->response);
205 rrb->request.fh = zdev->fh;
206
207 rc = clp_req(rrb, CLP_LPS_PCI);
208 if (!rc && rrb->response.hdr.rsp == CLP_RC_OK) {
209 rc = clp_store_query_pci_fn(zdev, &rrb->response);
210 if (rc)
211 goto out;
212 rc = clp_query_pci_fngrp(zdev, rrb->response.pfgid);
213 } else {
214 zpci_err("Q PCI FN:\n");
215 zpci_err_clp(rrb->response.hdr.rsp, rc);
216 rc = -EIO;
217 }
218 out:
219 clp_free_block(rrb);
220 return rc;
221 }
222
223 /**
224 * clp_set_pci_fn() - Execute a command on a PCI function
225 * @zdev: Function that will be affected
226 * @fh: Out parameter for updated function handle
227 * @nr_dma_as: DMA address space number
228 * @command: The command code to execute
229 *
230 * Returns: 0 on success, < 0 for Linux errors (e.g. -ENOMEM), and
231 * > 0 for non-success platform responses
232 */
clp_set_pci_fn(struct zpci_dev * zdev,u32 * fh,u8 nr_dma_as,u8 command)233 static int clp_set_pci_fn(struct zpci_dev *zdev, u32 *fh, u8 nr_dma_as, u8 command)
234 {
235 struct clp_req_rsp_set_pci *rrb;
236 int rc, retries = 100;
237 u32 gisa = 0;
238
239 *fh = 0;
240 rrb = clp_alloc_block(GFP_KERNEL);
241 if (!rrb)
242 return -ENOMEM;
243
244 if (command != CLP_SET_DISABLE_PCI_FN)
245 gisa = zdev->gisa;
246
247 do {
248 memset(rrb, 0, sizeof(*rrb));
249 rrb->request.hdr.len = sizeof(rrb->request);
250 rrb->request.hdr.cmd = CLP_SET_PCI_FN;
251 rrb->response.hdr.len = sizeof(rrb->response);
252 rrb->request.fh = zdev->fh;
253 rrb->request.oc = command;
254 rrb->request.ndas = nr_dma_as;
255 rrb->request.gisa = gisa;
256
257 rc = clp_req(rrb, CLP_LPS_PCI);
258 if (rrb->response.hdr.rsp == CLP_RC_SETPCIFN_BUSY) {
259 retries--;
260 if (retries < 0)
261 break;
262 msleep(20);
263 }
264 } while (rrb->response.hdr.rsp == CLP_RC_SETPCIFN_BUSY);
265
266 if (!rc && rrb->response.hdr.rsp == CLP_RC_OK) {
267 *fh = rrb->response.fh;
268 } else {
269 zpci_err("Set PCI FN:\n");
270 zpci_err_clp(rrb->response.hdr.rsp, rc);
271 if (!rc)
272 rc = rrb->response.hdr.rsp;
273 }
274 clp_free_block(rrb);
275 return rc;
276 }
277
clp_setup_writeback_mio(void)278 int clp_setup_writeback_mio(void)
279 {
280 struct clp_req_rsp_slpc_pci *rrb;
281 u8 wb_bit_pos;
282 int rc;
283
284 rrb = clp_alloc_block(GFP_KERNEL);
285 if (!rrb)
286 return -ENOMEM;
287
288 memset(rrb, 0, sizeof(*rrb));
289 rrb->request.hdr.len = sizeof(rrb->request);
290 rrb->request.hdr.cmd = CLP_SLPC;
291 rrb->response.hdr.len = sizeof(rrb->response);
292
293 rc = clp_req(rrb, CLP_LPS_PCI);
294 if (!rc && rrb->response.hdr.rsp == CLP_RC_OK) {
295 if (rrb->response.vwb) {
296 wb_bit_pos = rrb->response.mio_wb;
297 set_bit_inv(wb_bit_pos, &mio_wb_bit_mask);
298 zpci_dbg(3, "wb bit: %d\n", wb_bit_pos);
299 } else {
300 zpci_dbg(3, "wb bit: n.a.\n");
301 }
302
303 } else {
304 zpci_err("SLPC PCI:\n");
305 zpci_err_clp(rrb->response.hdr.rsp, rc);
306 rc = -EIO;
307 }
308 clp_free_block(rrb);
309 return rc;
310 }
311
clp_enable_fh(struct zpci_dev * zdev,u32 * fh,u8 nr_dma_as)312 int clp_enable_fh(struct zpci_dev *zdev, u32 *fh, u8 nr_dma_as)
313 {
314 int rc;
315
316 rc = clp_set_pci_fn(zdev, fh, nr_dma_as, CLP_SET_ENABLE_PCI_FN);
317 zpci_dbg(3, "ena fid:%x, fh:%x, rc:%d\n", zdev->fid, *fh, rc);
318 if (!rc && zpci_use_mio(zdev)) {
319 rc = clp_set_pci_fn(zdev, fh, nr_dma_as, CLP_SET_ENABLE_MIO);
320 zpci_dbg(3, "ena mio fid:%x, fh:%x, rc:%d\n",
321 zdev->fid, *fh, rc);
322 if (rc)
323 clp_disable_fh(zdev, fh);
324 }
325 return rc;
326 }
327
clp_disable_fh(struct zpci_dev * zdev,u32 * fh)328 int clp_disable_fh(struct zpci_dev *zdev, u32 *fh)
329 {
330 int rc;
331
332 if (!zdev_enabled(zdev))
333 return 0;
334
335 rc = clp_set_pci_fn(zdev, fh, 0, CLP_SET_DISABLE_PCI_FN);
336 zpci_dbg(3, "dis fid:%x, fh:%x, rc:%d\n", zdev->fid, *fh, rc);
337 return rc;
338 }
339
clp_list_pci_req(struct clp_req_rsp_list_pci * rrb,u64 * resume_token,int * nentries)340 static int clp_list_pci_req(struct clp_req_rsp_list_pci *rrb,
341 u64 *resume_token, int *nentries)
342 {
343 int rc;
344
345 memset(rrb, 0, sizeof(*rrb));
346 rrb->request.hdr.len = sizeof(rrb->request);
347 rrb->request.hdr.cmd = CLP_LIST_PCI;
348 /* store as many entries as possible */
349 rrb->response.hdr.len = CLP_BLK_SIZE - LIST_PCI_HDR_LEN;
350 rrb->request.resume_token = *resume_token;
351
352 /* Get PCI function handle list */
353 rc = clp_req(rrb, CLP_LPS_PCI);
354 if (rc || rrb->response.hdr.rsp != CLP_RC_OK) {
355 zpci_err("List PCI FN:\n");
356 zpci_err_clp(rrb->response.hdr.rsp, rc);
357 return -EIO;
358 }
359
360 update_uid_checking(rrb->response.uid_checking);
361 WARN_ON_ONCE(rrb->response.entry_size !=
362 sizeof(struct clp_fh_list_entry));
363
364 *nentries = (rrb->response.hdr.len - LIST_PCI_HDR_LEN) /
365 rrb->response.entry_size;
366 *resume_token = rrb->response.resume_token;
367
368 return rc;
369 }
370
clp_list_pci(struct clp_req_rsp_list_pci * rrb,void * data,void (* cb)(struct clp_fh_list_entry *,void *))371 static int clp_list_pci(struct clp_req_rsp_list_pci *rrb, void *data,
372 void (*cb)(struct clp_fh_list_entry *, void *))
373 {
374 u64 resume_token = 0;
375 int nentries, i, rc;
376
377 do {
378 rc = clp_list_pci_req(rrb, &resume_token, &nentries);
379 if (rc)
380 return rc;
381 for (i = 0; i < nentries; i++)
382 cb(&rrb->response.fh_list[i], data);
383 } while (resume_token);
384
385 return rc;
386 }
387
clp_find_pci(struct clp_req_rsp_list_pci * rrb,u32 fid,struct clp_fh_list_entry * entry)388 static int clp_find_pci(struct clp_req_rsp_list_pci *rrb, u32 fid,
389 struct clp_fh_list_entry *entry)
390 {
391 struct clp_fh_list_entry *fh_list;
392 u64 resume_token = 0;
393 int nentries, i, rc;
394
395 do {
396 rc = clp_list_pci_req(rrb, &resume_token, &nentries);
397 if (rc)
398 return rc;
399 fh_list = rrb->response.fh_list;
400 for (i = 0; i < nentries; i++) {
401 if (fh_list[i].fid == fid) {
402 *entry = fh_list[i];
403 return 0;
404 }
405 }
406 } while (resume_token);
407
408 return -ENODEV;
409 }
410
__clp_add(struct clp_fh_list_entry * entry,void * data)411 static void __clp_add(struct clp_fh_list_entry *entry, void *data)
412 {
413 struct list_head *scan_list = data;
414 struct zpci_dev *zdev;
415
416 if (!entry->vendor_id)
417 return;
418
419 zdev = get_zdev_by_fid(entry->fid);
420 if (zdev) {
421 zpci_zdev_put(zdev);
422 return;
423 }
424 zdev = zpci_create_device(entry->fid, entry->fh, entry->config_state);
425 if (IS_ERR(zdev))
426 return;
427 list_add_tail(&zdev->entry, scan_list);
428 }
429
clp_scan_pci_devices(struct list_head * scan_list)430 int clp_scan_pci_devices(struct list_head *scan_list)
431 {
432 struct clp_req_rsp_list_pci *rrb;
433 int rc;
434
435 rrb = clp_alloc_block(GFP_KERNEL);
436 if (!rrb)
437 return -ENOMEM;
438
439 rc = clp_list_pci(rrb, scan_list, __clp_add);
440
441 clp_free_block(rrb);
442 return rc;
443 }
444
445 /*
446 * Get the current function handle of the function matching @fid
447 */
clp_refresh_fh(u32 fid,u32 * fh)448 int clp_refresh_fh(u32 fid, u32 *fh)
449 {
450 struct clp_req_rsp_list_pci *rrb;
451 struct clp_fh_list_entry entry;
452 int rc;
453
454 rrb = clp_alloc_block(GFP_NOWAIT);
455 if (!rrb)
456 return -ENOMEM;
457
458 rc = clp_find_pci(rrb, fid, &entry);
459 if (!rc)
460 *fh = entry.fh;
461
462 clp_free_block(rrb);
463 return rc;
464 }
465
clp_get_state(u32 fid,enum zpci_state * state)466 int clp_get_state(u32 fid, enum zpci_state *state)
467 {
468 struct clp_req_rsp_list_pci *rrb;
469 struct clp_fh_list_entry entry;
470 int rc;
471
472 rrb = clp_alloc_block(GFP_ATOMIC);
473 if (!rrb)
474 return -ENOMEM;
475
476 rc = clp_find_pci(rrb, fid, &entry);
477 if (!rc) {
478 *state = entry.config_state;
479 } else if (rc == -ENODEV) {
480 *state = ZPCI_FN_STATE_RESERVED;
481 rc = 0;
482 }
483
484 clp_free_block(rrb);
485 return rc;
486 }
487
clp_base_slpc(struct clp_req * req,struct clp_req_rsp_slpc * lpcb)488 static int clp_base_slpc(struct clp_req *req, struct clp_req_rsp_slpc *lpcb)
489 {
490 unsigned long limit = PAGE_SIZE - sizeof(lpcb->request);
491
492 if (lpcb->request.hdr.len != sizeof(lpcb->request) ||
493 lpcb->response.hdr.len > limit)
494 return -EINVAL;
495 return clp_req(lpcb, CLP_LPS_BASE) ? -EOPNOTSUPP : 0;
496 }
497
clp_base_command(struct clp_req * req,struct clp_req_hdr * lpcb)498 static int clp_base_command(struct clp_req *req, struct clp_req_hdr *lpcb)
499 {
500 switch (lpcb->cmd) {
501 case 0x0001: /* store logical-processor characteristics */
502 return clp_base_slpc(req, (void *) lpcb);
503 default:
504 return -EINVAL;
505 }
506 }
507
clp_pci_slpc(struct clp_req * req,struct clp_req_rsp_slpc_pci * lpcb)508 static int clp_pci_slpc(struct clp_req *req, struct clp_req_rsp_slpc_pci *lpcb)
509 {
510 unsigned long limit = PAGE_SIZE - sizeof(lpcb->request);
511
512 if (lpcb->request.hdr.len != sizeof(lpcb->request) ||
513 lpcb->response.hdr.len > limit)
514 return -EINVAL;
515 return clp_req(lpcb, CLP_LPS_PCI) ? -EOPNOTSUPP : 0;
516 }
517
clp_pci_list(struct clp_req * req,struct clp_req_rsp_list_pci * lpcb)518 static int clp_pci_list(struct clp_req *req, struct clp_req_rsp_list_pci *lpcb)
519 {
520 unsigned long limit = PAGE_SIZE - sizeof(lpcb->request);
521
522 if (lpcb->request.hdr.len != sizeof(lpcb->request) ||
523 lpcb->response.hdr.len > limit)
524 return -EINVAL;
525 if (lpcb->request.reserved2 != 0)
526 return -EINVAL;
527 return clp_req(lpcb, CLP_LPS_PCI) ? -EOPNOTSUPP : 0;
528 }
529
clp_pci_query(struct clp_req * req,struct clp_req_rsp_query_pci * lpcb)530 static int clp_pci_query(struct clp_req *req,
531 struct clp_req_rsp_query_pci *lpcb)
532 {
533 unsigned long limit = PAGE_SIZE - sizeof(lpcb->request);
534
535 if (lpcb->request.hdr.len != sizeof(lpcb->request) ||
536 lpcb->response.hdr.len > limit)
537 return -EINVAL;
538 if (lpcb->request.reserved2 != 0 || lpcb->request.reserved3 != 0)
539 return -EINVAL;
540 return clp_req(lpcb, CLP_LPS_PCI) ? -EOPNOTSUPP : 0;
541 }
542
clp_pci_query_grp(struct clp_req * req,struct clp_req_rsp_query_pci_grp * lpcb)543 static int clp_pci_query_grp(struct clp_req *req,
544 struct clp_req_rsp_query_pci_grp *lpcb)
545 {
546 unsigned long limit = PAGE_SIZE - sizeof(lpcb->request);
547
548 if (lpcb->request.hdr.len != sizeof(lpcb->request) ||
549 lpcb->response.hdr.len > limit)
550 return -EINVAL;
551 if (lpcb->request.reserved2 != 0 || lpcb->request.reserved3 != 0 ||
552 lpcb->request.reserved4 != 0)
553 return -EINVAL;
554 return clp_req(lpcb, CLP_LPS_PCI) ? -EOPNOTSUPP : 0;
555 }
556
clp_pci_command(struct clp_req * req,struct clp_req_hdr * lpcb)557 static int clp_pci_command(struct clp_req *req, struct clp_req_hdr *lpcb)
558 {
559 switch (lpcb->cmd) {
560 case 0x0001: /* store logical-processor characteristics */
561 return clp_pci_slpc(req, (void *) lpcb);
562 case 0x0002: /* list PCI functions */
563 return clp_pci_list(req, (void *) lpcb);
564 case 0x0003: /* query PCI function */
565 return clp_pci_query(req, (void *) lpcb);
566 case 0x0004: /* query PCI function group */
567 return clp_pci_query_grp(req, (void *) lpcb);
568 default:
569 return -EINVAL;
570 }
571 }
572
clp_normal_command(struct clp_req * req)573 static int clp_normal_command(struct clp_req *req)
574 {
575 struct clp_req_hdr *lpcb;
576 void __user *uptr;
577 int rc;
578
579 rc = -EINVAL;
580 if (req->lps != 0 && req->lps != 2)
581 goto out;
582
583 rc = -ENOMEM;
584 lpcb = clp_alloc_block(GFP_KERNEL);
585 if (!lpcb)
586 goto out;
587
588 rc = -EFAULT;
589 uptr = (void __force __user *)(unsigned long) req->data_p;
590 if (copy_from_user(lpcb, uptr, PAGE_SIZE) != 0)
591 goto out_free;
592
593 rc = -EINVAL;
594 if (lpcb->fmt != 0 || lpcb->reserved1 != 0 || lpcb->reserved2 != 0)
595 goto out_free;
596
597 switch (req->lps) {
598 case 0:
599 rc = clp_base_command(req, lpcb);
600 break;
601 case 2:
602 rc = clp_pci_command(req, lpcb);
603 break;
604 }
605 if (rc)
606 goto out_free;
607
608 rc = -EFAULT;
609 if (copy_to_user(uptr, lpcb, PAGE_SIZE) != 0)
610 goto out_free;
611
612 rc = 0;
613
614 out_free:
615 clp_free_block(lpcb);
616 out:
617 return rc;
618 }
619
clp_immediate_command(struct clp_req * req)620 static int clp_immediate_command(struct clp_req *req)
621 {
622 void __user *uptr;
623 unsigned long ilp;
624 int exists;
625
626 if (req->cmd > 1 || clp_get_ilp(&ilp) != 0)
627 return -EINVAL;
628
629 uptr = (void __force __user *)(unsigned long) req->data_p;
630 if (req->cmd == 0) {
631 /* Command code 0: test for a specific processor */
632 exists = test_bit_inv(req->lps, &ilp);
633 return put_user(exists, (int __user *) uptr);
634 }
635 /* Command code 1: return bit mask of installed processors */
636 return put_user(ilp, (unsigned long __user *) uptr);
637 }
638
clp_misc_ioctl(struct file * filp,unsigned int cmd,unsigned long arg)639 static long clp_misc_ioctl(struct file *filp, unsigned int cmd,
640 unsigned long arg)
641 {
642 struct clp_req req;
643 void __user *argp;
644
645 if (cmd != CLP_SYNC)
646 return -EINVAL;
647
648 argp = is_compat_task() ? compat_ptr(arg) : (void __user *) arg;
649 if (copy_from_user(&req, argp, sizeof(req)))
650 return -EFAULT;
651 if (req.r != 0)
652 return -EINVAL;
653 return req.c ? clp_immediate_command(&req) : clp_normal_command(&req);
654 }
655
clp_misc_release(struct inode * inode,struct file * filp)656 static int clp_misc_release(struct inode *inode, struct file *filp)
657 {
658 return 0;
659 }
660
661 static const struct file_operations clp_misc_fops = {
662 .owner = THIS_MODULE,
663 .open = nonseekable_open,
664 .release = clp_misc_release,
665 .unlocked_ioctl = clp_misc_ioctl,
666 .compat_ioctl = clp_misc_ioctl,
667 };
668
669 static struct miscdevice clp_misc_device = {
670 .minor = MISC_DYNAMIC_MINOR,
671 .name = "clp",
672 .fops = &clp_misc_fops,
673 };
674
675 builtin_misc_device(clp_misc_device);
676