1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_CORE_H__
6 #define __RTW89_CORE_H__
7
8 #include <linux/average.h>
9 #include <linux/bitfield.h>
10 #include <linux/dmi.h>
11 #include <linux/firmware.h>
12 #include <linux/iopoll.h>
13 #include <linux/workqueue.h>
14 #include <net/mac80211.h>
15
16 struct rtw89_dev;
17 struct rtw89_pci_info;
18 struct rtw89_mac_gen_def;
19 struct rtw89_phy_gen_def;
20 struct rtw89_fw_blacklist;
21 struct rtw89_efuse_block_cfg;
22 struct rtw89_h2c_rf_tssi;
23 struct rtw89_fw_txpwr_track_cfg;
24 struct rtw89_phy_rfk_log_fmt;
25 struct rtw89_debugfs;
26
27 extern const struct ieee80211_ops rtw89_ops;
28
29 #define MASKBYTE0 0xff
30 #define MASKBYTE1 0xff00
31 #define MASKBYTE2 0xff0000
32 #define MASKBYTE3 0xff000000
33 #define MASKBYTE4 0xff00000000ULL
34 #define MASKHWORD 0xffff0000
35 #define MASKLWORD 0x0000ffff
36 #define MASKDWORD 0xffffffff
37 #define RFREG_MASK 0xfffff
38 #define INV_RF_DATA 0xffffffff
39 #define BYPASS_CR_DATA 0xbabecafe
40
41 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2)
42 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4)
43 #define CFO_TRACK_MAX_USER 64
44 #define MAX_RSSI 110
45 #define RSSI_FACTOR 1
46 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
47 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR)
48 #define DELTA_SWINGIDX_SIZE 30
49
50 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he)
51 #define RTW89_RADIOTAP_ROOM_EHT \
52 (sizeof(struct ieee80211_radiotap_tlv) + \
53 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \
54 sizeof(struct ieee80211_radiotap_tlv) + \
55 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4))
56 #define RTW89_RADIOTAP_ROOM \
57 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64)
58
59 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0)
60 #define RTW89_HTC_VARIANT_HE 3
61 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2)
62 #define RTW89_HTC_VARIANT_HE_CID_OM 1
63 #define RTW89_HTC_VARIANT_HE_CID_CAS 6
64 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6)
65
66 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6)
67 enum htc_om_channel_width {
68 HTC_OM_CHANNEL_WIDTH_20 = 0,
69 HTC_OM_CHANNEL_WIDTH_40 = 1,
70 HTC_OM_CHANNEL_WIDTH_80 = 2,
71 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3,
72 };
73 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9)
74 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11)
75 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12)
76 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15)
77 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16)
78 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17)
79
80 #define RTW89_TF_PAD GENMASK(11, 0)
81 #define RTW89_TF_BASIC_USER_INFO_SZ 6
82
83 #define RTW89_GET_TF_USER_INFO_AID12(data) \
84 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0))
85 #define RTW89_GET_TF_USER_INFO_RUA(data) \
86 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12))
87 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \
88 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21))
89
90 enum rtw89_subband {
91 RTW89_CH_2G = 0,
92 RTW89_CH_5G_BAND_1 = 1,
93 /* RTW89_CH_5G_BAND_2 = 2, unused */
94 RTW89_CH_5G_BAND_3 = 3,
95 RTW89_CH_5G_BAND_4 = 4,
96
97 RTW89_CH_6G_BAND_IDX0, /* Low */
98 RTW89_CH_6G_BAND_IDX1, /* Low */
99 RTW89_CH_6G_BAND_IDX2, /* Mid */
100 RTW89_CH_6G_BAND_IDX3, /* Mid */
101 RTW89_CH_6G_BAND_IDX4, /* High */
102 RTW89_CH_6G_BAND_IDX5, /* High */
103 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */
104 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */
105
106 RTW89_SUBBAND_NR,
107 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1,
108 };
109
110 enum rtw89_gain_offset {
111 RTW89_GAIN_OFFSET_2G_CCK,
112 RTW89_GAIN_OFFSET_2G_OFDM,
113 RTW89_GAIN_OFFSET_5G_LOW,
114 RTW89_GAIN_OFFSET_5G_MID,
115 RTW89_GAIN_OFFSET_5G_HIGH,
116 RTW89_GAIN_OFFSET_6G_L0,
117 RTW89_GAIN_OFFSET_6G_L1,
118 RTW89_GAIN_OFFSET_6G_M0,
119 RTW89_GAIN_OFFSET_6G_M1,
120 RTW89_GAIN_OFFSET_6G_H0,
121 RTW89_GAIN_OFFSET_6G_H1,
122 RTW89_GAIN_OFFSET_6G_UH0,
123 RTW89_GAIN_OFFSET_6G_UH1,
124
125 RTW89_GAIN_OFFSET_NR,
126 };
127
128 enum rtw89_hci_type {
129 RTW89_HCI_TYPE_PCIE,
130 RTW89_HCI_TYPE_USB,
131 RTW89_HCI_TYPE_SDIO,
132 };
133
134 enum rtw89_core_chip_id {
135 RTL8852A,
136 RTL8852B,
137 RTL8852BT,
138 RTL8852C,
139 RTL8851B,
140 RTL8922A,
141 };
142
143 enum rtw89_chip_gen {
144 RTW89_CHIP_AX,
145 RTW89_CHIP_BE,
146
147 RTW89_CHIP_GEN_NUM,
148 };
149
150 enum rtw89_cv {
151 CHIP_CAV,
152 CHIP_CBV,
153 CHIP_CCV,
154 CHIP_CDV,
155 CHIP_CEV,
156 CHIP_CFV,
157 CHIP_CV_MAX,
158 CHIP_CV_INVALID = CHIP_CV_MAX,
159 };
160
161 enum rtw89_bacam_ver {
162 RTW89_BACAM_V0,
163 RTW89_BACAM_V1,
164
165 RTW89_BACAM_V0_EXT = 99,
166 };
167
168 enum rtw89_core_tx_type {
169 RTW89_CORE_TX_TYPE_DATA,
170 RTW89_CORE_TX_TYPE_MGMT,
171 RTW89_CORE_TX_TYPE_FWCMD,
172 };
173
174 enum rtw89_core_rx_type {
175 RTW89_CORE_RX_TYPE_WIFI = 0,
176 RTW89_CORE_RX_TYPE_PPDU_STAT = 1,
177 RTW89_CORE_RX_TYPE_CHAN_INFO = 2,
178 RTW89_CORE_RX_TYPE_BB_SCOPE = 3,
179 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4,
180 RTW89_CORE_RX_TYPE_SS2FW = 5,
181 RTW89_CORE_RX_TYPE_TX_REPORT = 6,
182 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7,
183 RTW89_CORE_RX_TYPE_DFS_REPORT = 8,
184 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9,
185 RTW89_CORE_RX_TYPE_C2H = 10,
186 RTW89_CORE_RX_TYPE_CSI = 11,
187 RTW89_CORE_RX_TYPE_CQI = 12,
188 RTW89_CORE_RX_TYPE_H2C = 13,
189 RTW89_CORE_RX_TYPE_FWDL = 14,
190 };
191
192 enum rtw89_txq_flags {
193 RTW89_TXQ_F_AMPDU = 0,
194 RTW89_TXQ_F_BLOCK_BA = 1,
195 RTW89_TXQ_F_FORBID_BA = 2,
196 };
197
198 enum rtw89_net_type {
199 RTW89_NET_TYPE_NO_LINK = 0,
200 RTW89_NET_TYPE_AD_HOC = 1,
201 RTW89_NET_TYPE_INFRA = 2,
202 RTW89_NET_TYPE_AP_MODE = 3,
203 };
204
205 enum rtw89_wifi_role {
206 RTW89_WIFI_ROLE_NONE,
207 RTW89_WIFI_ROLE_STATION,
208 RTW89_WIFI_ROLE_AP,
209 RTW89_WIFI_ROLE_AP_VLAN,
210 RTW89_WIFI_ROLE_ADHOC,
211 RTW89_WIFI_ROLE_ADHOC_MASTER,
212 RTW89_WIFI_ROLE_MESH_POINT,
213 RTW89_WIFI_ROLE_MONITOR,
214 RTW89_WIFI_ROLE_P2P_DEVICE,
215 RTW89_WIFI_ROLE_P2P_CLIENT,
216 RTW89_WIFI_ROLE_P2P_GO,
217 RTW89_WIFI_ROLE_NAN,
218 RTW89_WIFI_ROLE_MLME_MAX
219 };
220
221 enum rtw89_upd_mode {
222 RTW89_ROLE_CREATE,
223 RTW89_ROLE_REMOVE,
224 RTW89_ROLE_TYPE_CHANGE,
225 RTW89_ROLE_INFO_CHANGE,
226 RTW89_ROLE_CON_DISCONN,
227 RTW89_ROLE_BAND_SW,
228 RTW89_ROLE_FW_RESTORE,
229 };
230
231 enum rtw89_self_role {
232 RTW89_SELF_ROLE_CLIENT,
233 RTW89_SELF_ROLE_AP,
234 RTW89_SELF_ROLE_AP_CLIENT
235 };
236
237 enum rtw89_msk_sO_el {
238 RTW89_NO_MSK,
239 RTW89_SMA,
240 RTW89_TMA,
241 RTW89_BSSID
242 };
243
244 enum rtw89_sch_tx_sel {
245 RTW89_SCH_TX_SEL_ALL,
246 RTW89_SCH_TX_SEL_HIQ,
247 RTW89_SCH_TX_SEL_MG0,
248 RTW89_SCH_TX_SEL_MACID,
249 };
250
251 /* RTW89_ADDR_CAM_SEC_NONE : not enabled
252 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast
253 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP
254 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP
255 */
256 enum rtw89_add_cam_sec_mode {
257 RTW89_ADDR_CAM_SEC_NONE = 0,
258 RTW89_ADDR_CAM_SEC_ALL_UNI = 1,
259 RTW89_ADDR_CAM_SEC_NORMAL = 2,
260 RTW89_ADDR_CAM_SEC_4GROUP = 3,
261 };
262
263 enum rtw89_sec_key_type {
264 RTW89_SEC_KEY_TYPE_NONE = 0,
265 RTW89_SEC_KEY_TYPE_WEP40 = 1,
266 RTW89_SEC_KEY_TYPE_WEP104 = 2,
267 RTW89_SEC_KEY_TYPE_TKIP = 3,
268 RTW89_SEC_KEY_TYPE_WAPI = 4,
269 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5,
270 RTW89_SEC_KEY_TYPE_CCMP128 = 6,
271 RTW89_SEC_KEY_TYPE_CCMP256 = 7,
272 RTW89_SEC_KEY_TYPE_GCMP128 = 8,
273 RTW89_SEC_KEY_TYPE_GCMP256 = 9,
274 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10,
275 };
276
277 enum rtw89_port {
278 RTW89_PORT_0 = 0,
279 RTW89_PORT_1 = 1,
280 RTW89_PORT_2 = 2,
281 RTW89_PORT_3 = 3,
282 RTW89_PORT_4 = 4,
283 RTW89_PORT_NUM
284 };
285
286 enum rtw89_band {
287 RTW89_BAND_2G = 0,
288 RTW89_BAND_5G = 1,
289 RTW89_BAND_6G = 2,
290 RTW89_BAND_NUM,
291 };
292
293 enum rtw89_hw_rate {
294 RTW89_HW_RATE_CCK1 = 0x0,
295 RTW89_HW_RATE_CCK2 = 0x1,
296 RTW89_HW_RATE_CCK5_5 = 0x2,
297 RTW89_HW_RATE_CCK11 = 0x3,
298 RTW89_HW_RATE_OFDM6 = 0x4,
299 RTW89_HW_RATE_OFDM9 = 0x5,
300 RTW89_HW_RATE_OFDM12 = 0x6,
301 RTW89_HW_RATE_OFDM18 = 0x7,
302 RTW89_HW_RATE_OFDM24 = 0x8,
303 RTW89_HW_RATE_OFDM36 = 0x9,
304 RTW89_HW_RATE_OFDM48 = 0xA,
305 RTW89_HW_RATE_OFDM54 = 0xB,
306 RTW89_HW_RATE_MCS0 = 0x80,
307 RTW89_HW_RATE_MCS1 = 0x81,
308 RTW89_HW_RATE_MCS2 = 0x82,
309 RTW89_HW_RATE_MCS3 = 0x83,
310 RTW89_HW_RATE_MCS4 = 0x84,
311 RTW89_HW_RATE_MCS5 = 0x85,
312 RTW89_HW_RATE_MCS6 = 0x86,
313 RTW89_HW_RATE_MCS7 = 0x87,
314 RTW89_HW_RATE_MCS8 = 0x88,
315 RTW89_HW_RATE_MCS9 = 0x89,
316 RTW89_HW_RATE_MCS10 = 0x8A,
317 RTW89_HW_RATE_MCS11 = 0x8B,
318 RTW89_HW_RATE_MCS12 = 0x8C,
319 RTW89_HW_RATE_MCS13 = 0x8D,
320 RTW89_HW_RATE_MCS14 = 0x8E,
321 RTW89_HW_RATE_MCS15 = 0x8F,
322 RTW89_HW_RATE_MCS16 = 0x90,
323 RTW89_HW_RATE_MCS17 = 0x91,
324 RTW89_HW_RATE_MCS18 = 0x92,
325 RTW89_HW_RATE_MCS19 = 0x93,
326 RTW89_HW_RATE_MCS20 = 0x94,
327 RTW89_HW_RATE_MCS21 = 0x95,
328 RTW89_HW_RATE_MCS22 = 0x96,
329 RTW89_HW_RATE_MCS23 = 0x97,
330 RTW89_HW_RATE_MCS24 = 0x98,
331 RTW89_HW_RATE_MCS25 = 0x99,
332 RTW89_HW_RATE_MCS26 = 0x9A,
333 RTW89_HW_RATE_MCS27 = 0x9B,
334 RTW89_HW_RATE_MCS28 = 0x9C,
335 RTW89_HW_RATE_MCS29 = 0x9D,
336 RTW89_HW_RATE_MCS30 = 0x9E,
337 RTW89_HW_RATE_MCS31 = 0x9F,
338 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100,
339 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101,
340 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102,
341 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103,
342 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104,
343 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105,
344 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106,
345 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107,
346 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108,
347 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109,
348 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110,
349 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111,
350 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112,
351 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113,
352 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114,
353 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115,
354 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116,
355 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117,
356 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118,
357 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119,
358 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120,
359 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121,
360 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122,
361 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123,
362 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124,
363 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125,
364 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126,
365 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127,
366 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128,
367 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129,
368 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130,
369 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131,
370 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132,
371 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133,
372 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134,
373 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135,
374 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136,
375 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137,
376 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138,
377 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139,
378 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180,
379 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181,
380 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182,
381 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183,
382 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184,
383 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185,
384 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186,
385 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187,
386 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188,
387 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189,
388 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A,
389 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B,
390 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190,
391 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191,
392 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192,
393 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193,
394 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194,
395 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195,
396 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196,
397 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197,
398 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198,
399 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199,
400 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A,
401 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B,
402 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0,
403 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1,
404 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2,
405 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3,
406 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4,
407 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5,
408 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6,
409 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7,
410 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8,
411 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9,
412 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA,
413 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB,
414 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0,
415 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1,
416 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2,
417 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3,
418 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4,
419 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5,
420 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6,
421 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7,
422 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8,
423 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9,
424 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA,
425 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB,
426
427 RTW89_HW_RATE_V1_MCS0 = 0x100,
428 RTW89_HW_RATE_V1_MCS1 = 0x101,
429 RTW89_HW_RATE_V1_MCS2 = 0x102,
430 RTW89_HW_RATE_V1_MCS3 = 0x103,
431 RTW89_HW_RATE_V1_MCS4 = 0x104,
432 RTW89_HW_RATE_V1_MCS5 = 0x105,
433 RTW89_HW_RATE_V1_MCS6 = 0x106,
434 RTW89_HW_RATE_V1_MCS7 = 0x107,
435 RTW89_HW_RATE_V1_MCS8 = 0x108,
436 RTW89_HW_RATE_V1_MCS9 = 0x109,
437 RTW89_HW_RATE_V1_MCS10 = 0x10A,
438 RTW89_HW_RATE_V1_MCS11 = 0x10B,
439 RTW89_HW_RATE_V1_MCS12 = 0x10C,
440 RTW89_HW_RATE_V1_MCS13 = 0x10D,
441 RTW89_HW_RATE_V1_MCS14 = 0x10E,
442 RTW89_HW_RATE_V1_MCS15 = 0x10F,
443 RTW89_HW_RATE_V1_MCS16 = 0x110,
444 RTW89_HW_RATE_V1_MCS17 = 0x111,
445 RTW89_HW_RATE_V1_MCS18 = 0x112,
446 RTW89_HW_RATE_V1_MCS19 = 0x113,
447 RTW89_HW_RATE_V1_MCS20 = 0x114,
448 RTW89_HW_RATE_V1_MCS21 = 0x115,
449 RTW89_HW_RATE_V1_MCS22 = 0x116,
450 RTW89_HW_RATE_V1_MCS23 = 0x117,
451 RTW89_HW_RATE_V1_MCS24 = 0x118,
452 RTW89_HW_RATE_V1_MCS25 = 0x119,
453 RTW89_HW_RATE_V1_MCS26 = 0x11A,
454 RTW89_HW_RATE_V1_MCS27 = 0x11B,
455 RTW89_HW_RATE_V1_MCS28 = 0x11C,
456 RTW89_HW_RATE_V1_MCS29 = 0x11D,
457 RTW89_HW_RATE_V1_MCS30 = 0x11E,
458 RTW89_HW_RATE_V1_MCS31 = 0x11F,
459 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200,
460 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201,
461 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202,
462 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203,
463 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204,
464 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205,
465 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206,
466 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207,
467 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208,
468 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209,
469 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A,
470 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B,
471 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220,
472 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221,
473 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222,
474 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223,
475 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224,
476 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225,
477 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226,
478 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227,
479 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228,
480 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229,
481 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A,
482 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B,
483 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240,
484 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241,
485 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242,
486 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243,
487 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244,
488 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245,
489 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246,
490 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247,
491 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248,
492 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249,
493 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A,
494 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B,
495 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260,
496 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261,
497 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262,
498 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263,
499 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264,
500 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265,
501 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266,
502 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267,
503 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268,
504 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269,
505 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A,
506 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B,
507 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300,
508 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301,
509 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302,
510 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303,
511 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304,
512 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305,
513 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306,
514 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307,
515 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308,
516 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309,
517 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A,
518 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B,
519 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320,
520 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321,
521 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322,
522 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323,
523 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324,
524 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325,
525 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326,
526 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327,
527 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328,
528 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329,
529 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A,
530 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B,
531 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340,
532 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341,
533 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342,
534 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343,
535 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344,
536 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345,
537 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346,
538 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347,
539 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348,
540 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349,
541 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A,
542 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B,
543 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360,
544 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361,
545 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362,
546 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363,
547 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364,
548 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365,
549 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366,
550 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367,
551 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368,
552 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369,
553 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A,
554 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B,
555 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400,
556 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401,
557 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402,
558 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403,
559 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404,
560 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405,
561 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406,
562 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407,
563 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408,
564 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409,
565 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A,
566 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B,
567 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C,
568 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D,
569 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E,
570 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F,
571 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420,
572 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421,
573 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422,
574 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423,
575 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424,
576 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425,
577 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426,
578 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427,
579 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428,
580 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429,
581 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A,
582 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B,
583 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C,
584 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D,
585 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440,
586 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441,
587 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442,
588 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443,
589 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444,
590 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445,
591 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446,
592 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447,
593 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448,
594 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449,
595 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A,
596 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B,
597 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C,
598 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D,
599 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460,
600 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461,
601 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462,
602 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463,
603 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464,
604 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465,
605 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466,
606 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467,
607 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468,
608 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469,
609 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A,
610 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B,
611 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C,
612 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D,
613
614 RTW89_HW_RATE_NR,
615 RTW89_HW_RATE_INVAL,
616
617 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7),
618 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0),
619 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8),
620 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0),
621 };
622
623 /* 2G channels,
624 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
625 */
626 #define RTW89_2G_CH_NUM 14
627
628 /* 5G channels,
629 * 36, 38, 40, 42, 44, 46, 48, 50,
630 * 52, 54, 56, 58, 60, 62, 64,
631 * 100, 102, 104, 106, 108, 110, 112, 114,
632 * 116, 118, 120, 122, 124, 126, 128, 130,
633 * 132, 134, 136, 138, 140, 142, 144,
634 * 149, 151, 153, 155, 157, 159, 161, 163,
635 * 165, 167, 169, 171, 173, 175, 177
636 */
637 #define RTW89_5G_CH_NUM 53
638
639 /* 6G channels,
640 * 1, 3, 5, 7, 9, 11, 13, 15,
641 * 17, 19, 21, 23, 25, 27, 29, 33,
642 * 35, 37, 39, 41, 43, 45, 47, 49,
643 * 51, 53, 55, 57, 59, 61, 65, 67,
644 * 69, 71, 73, 75, 77, 79, 81, 83,
645 * 85, 87, 89, 91, 93, 97, 99, 101,
646 * 103, 105, 107, 109, 111, 113, 115, 117,
647 * 119, 121, 123, 125, 129, 131, 133, 135,
648 * 137, 139, 141, 143, 145, 147, 149, 151,
649 * 153, 155, 157, 161, 163, 165, 167, 169,
650 * 171, 173, 175, 177, 179, 181, 183, 185,
651 * 187, 189, 193, 195, 197, 199, 201, 203,
652 * 205, 207, 209, 211, 213, 215, 217, 219,
653 * 221, 225, 227, 229, 231, 233, 235, 237,
654 * 239, 241, 243, 245, 247, 249, 251, 253,
655 */
656 #define RTW89_6G_CH_NUM 120
657
658 enum rtw89_rate_section {
659 RTW89_RS_CCK,
660 RTW89_RS_OFDM,
661 RTW89_RS_MCS, /* for HT/VHT/HE */
662 RTW89_RS_HEDCM,
663 RTW89_RS_OFFSET,
664 RTW89_RS_NUM,
665 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1,
666 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1,
667 };
668
669 enum rtw89_rate_offset_indexes {
670 RTW89_RATE_OFFSET_HE,
671 RTW89_RATE_OFFSET_VHT,
672 RTW89_RATE_OFFSET_HT,
673 RTW89_RATE_OFFSET_OFDM,
674 RTW89_RATE_OFFSET_CCK,
675 RTW89_RATE_OFFSET_DLRU_EHT,
676 RTW89_RATE_OFFSET_DLRU_HE,
677 RTW89_RATE_OFFSET_EHT,
678 __RTW89_RATE_OFFSET_NUM,
679
680 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1,
681 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1,
682 };
683
684 enum rtw89_rate_num {
685 RTW89_RATE_CCK_NUM = 4,
686 RTW89_RATE_OFDM_NUM = 8,
687 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */
688
689 RTW89_RATE_MCS_NUM_AX = 12,
690 RTW89_RATE_MCS_NUM_BE = 16,
691 __RTW89_RATE_MCS_NUM = 16,
692 };
693
694 enum rtw89_nss {
695 RTW89_NSS_1 = 0,
696 RTW89_NSS_2 = 1,
697 /* HE DCM only support 1ss and 2ss */
698 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1,
699 RTW89_NSS_3 = 2,
700 RTW89_NSS_4 = 3,
701 RTW89_NSS_NUM,
702 };
703
704 enum rtw89_ntx {
705 RTW89_1TX = 0,
706 RTW89_2TX = 1,
707 RTW89_NTX_NUM,
708 };
709
710 enum rtw89_beamforming_type {
711 RTW89_NONBF = 0,
712 RTW89_BF = 1,
713 RTW89_BF_NUM,
714 };
715
716 enum rtw89_ofdma_type {
717 RTW89_NON_OFDMA = 0,
718 RTW89_OFDMA = 1,
719 RTW89_OFDMA_NUM,
720 };
721
722 enum rtw89_regulation_type {
723 RTW89_WW = 0,
724 RTW89_ETSI = 1,
725 RTW89_FCC = 2,
726 RTW89_MKK = 3,
727 RTW89_NA = 4,
728 RTW89_IC = 5,
729 RTW89_KCC = 6,
730 RTW89_ACMA = 7,
731 RTW89_NCC = 8,
732 RTW89_MEXICO = 9,
733 RTW89_CHILE = 10,
734 RTW89_UKRAINE = 11,
735 RTW89_CN = 12,
736 RTW89_QATAR = 13,
737 RTW89_UK = 14,
738 RTW89_THAILAND = 15,
739 RTW89_REGD_NUM,
740 };
741
742 enum rtw89_reg_6ghz_power {
743 RTW89_REG_6GHZ_POWER_VLP = 0,
744 RTW89_REG_6GHZ_POWER_LPI = 1,
745 RTW89_REG_6GHZ_POWER_STD = 2,
746
747 NUM_OF_RTW89_REG_6GHZ_POWER,
748 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP,
749 };
750
751 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */
752
753 /* calculate based on ieee80211 Transmit Power Envelope */
754 struct rtw89_reg_6ghz_tpe {
755 bool valid;
756 s8 constraint; /* unit: dBm */
757 };
758
759 enum rtw89_fw_pkt_ofld_type {
760 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0,
761 RTW89_PKT_OFLD_TYPE_PS_POLL = 1,
762 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2,
763 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3,
764 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4,
765 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5,
766 RTW89_PKT_OFLD_TYPE_NDP = 6,
767 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7,
768 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8,
769 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12,
770 RTW89_PKT_OFLD_TYPE_NUM,
771 };
772
773 struct rtw89_txpwr_byrate {
774 s8 cck[RTW89_RATE_CCK_NUM];
775 s8 ofdm[RTW89_RATE_OFDM_NUM];
776 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM];
777 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM];
778 s8 offset[__RTW89_RATE_OFFSET_NUM];
779 s8 trap;
780 };
781
782 struct rtw89_rate_desc {
783 enum rtw89_nss nss;
784 enum rtw89_rate_section rs;
785 enum rtw89_ofdma_type ofdma;
786 u8 idx;
787 };
788
789 #define PHY_STS_HDR_LEN 8
790 #define RF_PATH_MAX 4
791 #define RTW89_MAX_PPDU_CNT 8
792 struct rtw89_rx_phy_ppdu {
793 void *buf;
794 u32 len;
795 u8 rssi_avg;
796 u8 rssi[RF_PATH_MAX];
797 u8 mac_id;
798 u8 chan_idx;
799 u8 ie;
800 u16 rate;
801 u8 rpl_avg;
802 u8 rpl_path[RF_PATH_MAX];
803 u8 rpl_fd[RF_PATH_MAX];
804 u8 bw_idx;
805 u8 rx_path_en;
806 struct {
807 bool has;
808 u8 avg_snr;
809 u8 evm_max;
810 u8 evm_min;
811 } ofdm;
812 bool has_data;
813 bool has_bcn;
814 bool ldpc;
815 bool stbc;
816 bool to_self;
817 bool valid;
818 bool hdr_2_en;
819 };
820
821 enum rtw89_mac_idx {
822 RTW89_MAC_0 = 0,
823 RTW89_MAC_1 = 1,
824 RTW89_MAC_NUM,
825 };
826
827 enum rtw89_phy_idx {
828 RTW89_PHY_0 = 0,
829 RTW89_PHY_1 = 1,
830 RTW89_PHY_MAX
831 };
832
833 #define __RTW89_MLD_MAX_LINK_NUM 2
834
835 enum rtw89_chanctx_idx {
836 RTW89_CHANCTX_0 = 0,
837 RTW89_CHANCTX_1 = 1,
838
839 NUM_OF_RTW89_CHANCTX,
840 RTW89_CHANCTX_IDLE = NUM_OF_RTW89_CHANCTX,
841 };
842
843 enum rtw89_rf_path {
844 RF_PATH_A = 0,
845 RF_PATH_B = 1,
846 RF_PATH_C = 2,
847 RF_PATH_D = 3,
848 RF_PATH_AB,
849 RF_PATH_AC,
850 RF_PATH_AD,
851 RF_PATH_BC,
852 RF_PATH_BD,
853 RF_PATH_CD,
854 RF_PATH_ABC,
855 RF_PATH_ABD,
856 RF_PATH_ACD,
857 RF_PATH_BCD,
858 RF_PATH_ABCD,
859 };
860
861 enum rtw89_rf_path_bit {
862 RF_A = BIT(0),
863 RF_B = BIT(1),
864 RF_C = BIT(2),
865 RF_D = BIT(3),
866
867 RF_AB = (RF_A | RF_B),
868 RF_AC = (RF_A | RF_C),
869 RF_AD = (RF_A | RF_D),
870 RF_BC = (RF_B | RF_C),
871 RF_BD = (RF_B | RF_D),
872 RF_CD = (RF_C | RF_D),
873
874 RF_ABC = (RF_A | RF_B | RF_C),
875 RF_ABD = (RF_A | RF_B | RF_D),
876 RF_ACD = (RF_A | RF_C | RF_D),
877 RF_BCD = (RF_B | RF_C | RF_D),
878
879 RF_ABCD = (RF_A | RF_B | RF_C | RF_D),
880 };
881
882 enum rtw89_bandwidth {
883 RTW89_CHANNEL_WIDTH_20 = 0,
884 RTW89_CHANNEL_WIDTH_40 = 1,
885 RTW89_CHANNEL_WIDTH_80 = 2,
886 RTW89_CHANNEL_WIDTH_160 = 3,
887 RTW89_CHANNEL_WIDTH_320 = 4,
888
889 /* keep index order above */
890 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5,
891
892 RTW89_CHANNEL_WIDTH_80_80 = 5,
893 RTW89_CHANNEL_WIDTH_5 = 6,
894 RTW89_CHANNEL_WIDTH_10 = 7,
895 };
896
897 enum rtw89_ps_mode {
898 RTW89_PS_MODE_NONE = 0,
899 RTW89_PS_MODE_RFOFF = 1,
900 RTW89_PS_MODE_CLK_GATED = 2,
901 RTW89_PS_MODE_PWR_GATED = 3,
902 };
903
904 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1)
905 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
906 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
907 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
908 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
909
910 enum rtw89_pe_duration {
911 RTW89_PE_DURATION_0 = 0,
912 RTW89_PE_DURATION_8 = 1,
913 RTW89_PE_DURATION_16 = 2,
914 RTW89_PE_DURATION_16_20 = 3,
915 };
916
917 enum rtw89_ru_bandwidth {
918 RTW89_RU26 = 0,
919 RTW89_RU52 = 1,
920 RTW89_RU106 = 2,
921 RTW89_RU52_26 = 3,
922 RTW89_RU106_26 = 4,
923 RTW89_RU_NUM,
924 };
925
926 enum rtw89_sc_offset {
927 RTW89_SC_DONT_CARE = 0,
928 RTW89_SC_20_UPPER = 1,
929 RTW89_SC_20_LOWER = 2,
930 RTW89_SC_20_UPMOST = 3,
931 RTW89_SC_20_LOWEST = 4,
932 RTW89_SC_20_UP2X = 5,
933 RTW89_SC_20_LOW2X = 6,
934 RTW89_SC_20_UP3X = 7,
935 RTW89_SC_20_LOW3X = 8,
936 RTW89_SC_40_UPPER = 9,
937 RTW89_SC_40_LOWER = 10,
938 };
939
940 /* only mgd features can be added to the enum */
941 enum rtw89_wow_flags {
942 RTW89_WOW_FLAG_EN_MAGIC_PKT,
943 RTW89_WOW_FLAG_EN_REKEY_PKT,
944 RTW89_WOW_FLAG_EN_DISCONNECT,
945 RTW89_WOW_FLAG_EN_PATTERN,
946 RTW89_WOW_FLAG_NUM,
947 };
948
949 struct rtw89_chan {
950 u8 channel;
951 u8 primary_channel;
952 enum rtw89_band band_type;
953 enum rtw89_bandwidth band_width;
954
955 /* The follow-up are derived from the above. We must ensure that it
956 * is assigned correctly in rtw89_chan_create() if new one is added.
957 */
958 u32 freq;
959 enum rtw89_subband subband_type;
960 enum rtw89_sc_offset pri_ch_idx;
961 u8 pri_sb_idx;
962 };
963
964 struct rtw89_chan_rcd {
965 u8 prev_primary_channel;
966 enum rtw89_band prev_band_type;
967 bool band_changed;
968 };
969
970 struct rtw89_channel_help_params {
971 u32 tx_en;
972 };
973
974 struct rtw89_port_reg {
975 u32 port_cfg;
976 u32 tbtt_prohib;
977 u32 bcn_area;
978 u32 bcn_early;
979 u32 tbtt_early;
980 u32 tbtt_agg;
981 u32 bcn_space;
982 u32 bcn_forcetx;
983 u32 bcn_err_cnt;
984 u32 bcn_err_flag;
985 u32 dtim_ctrl;
986 u32 tbtt_shift;
987 u32 bcn_cnt_tmr;
988 u32 tsftr_l;
989 u32 tsftr_h;
990 u32 md_tsft;
991 u32 bss_color;
992 u32 mbssid;
993 u32 mbssid_drop;
994 u32 tsf_sync;
995 u32 ptcl_dbg;
996 u32 ptcl_dbg_info;
997 u32 bcn_drop_all;
998 u32 hiq_win[RTW89_PORT_NUM];
999 };
1000
1001 struct rtw89_txwd_body {
1002 __le32 dword0;
1003 __le32 dword1;
1004 __le32 dword2;
1005 __le32 dword3;
1006 __le32 dword4;
1007 __le32 dword5;
1008 } __packed;
1009
1010 struct rtw89_txwd_body_v1 {
1011 __le32 dword0;
1012 __le32 dword1;
1013 __le32 dword2;
1014 __le32 dword3;
1015 __le32 dword4;
1016 __le32 dword5;
1017 __le32 dword6;
1018 __le32 dword7;
1019 } __packed;
1020
1021 struct rtw89_txwd_body_v2 {
1022 __le32 dword0;
1023 __le32 dword1;
1024 __le32 dword2;
1025 __le32 dword3;
1026 __le32 dword4;
1027 __le32 dword5;
1028 __le32 dword6;
1029 __le32 dword7;
1030 } __packed;
1031
1032 struct rtw89_txwd_info {
1033 __le32 dword0;
1034 __le32 dword1;
1035 __le32 dword2;
1036 __le32 dword3;
1037 __le32 dword4;
1038 __le32 dword5;
1039 } __packed;
1040
1041 struct rtw89_txwd_info_v2 {
1042 __le32 dword0;
1043 __le32 dword1;
1044 __le32 dword2;
1045 __le32 dword3;
1046 __le32 dword4;
1047 __le32 dword5;
1048 __le32 dword6;
1049 __le32 dword7;
1050 } __packed;
1051
1052 struct rtw89_rx_desc_info {
1053 u16 pkt_size;
1054 u8 pkt_type;
1055 u8 drv_info_size;
1056 u8 phy_rpt_size;
1057 u8 hdr_cnv_size;
1058 u8 shift;
1059 u8 wl_hd_iv_len;
1060 bool long_rxdesc;
1061 bool bb_sel;
1062 bool mac_info_valid;
1063 u16 data_rate;
1064 u8 gi_ltf;
1065 u8 bw;
1066 u32 free_run_cnt;
1067 u8 user_id;
1068 bool sr_en;
1069 u8 ppdu_cnt;
1070 u8 ppdu_type;
1071 bool icv_err;
1072 bool crc32_err;
1073 bool hw_dec;
1074 bool sw_dec;
1075 bool addr1_match;
1076 u8 frag;
1077 u16 seq;
1078 u8 frame_type;
1079 u8 rx_pl_id;
1080 bool addr_cam_valid;
1081 u8 addr_cam_id;
1082 u8 sec_cam_id;
1083 u8 mac_id;
1084 u16 offset;
1085 u16 rxd_len;
1086 bool ready;
1087 };
1088
1089 struct rtw89_rxdesc_short {
1090 __le32 dword0;
1091 __le32 dword1;
1092 __le32 dword2;
1093 __le32 dword3;
1094 } __packed;
1095
1096 struct rtw89_rxdesc_short_v2 {
1097 __le32 dword0;
1098 __le32 dword1;
1099 __le32 dword2;
1100 __le32 dword3;
1101 __le32 dword4;
1102 __le32 dword5;
1103 } __packed;
1104
1105 struct rtw89_rxdesc_long {
1106 __le32 dword0;
1107 __le32 dword1;
1108 __le32 dword2;
1109 __le32 dword3;
1110 __le32 dword4;
1111 __le32 dword5;
1112 __le32 dword6;
1113 __le32 dword7;
1114 } __packed;
1115
1116 struct rtw89_rxdesc_long_v2 {
1117 __le32 dword0;
1118 __le32 dword1;
1119 __le32 dword2;
1120 __le32 dword3;
1121 __le32 dword4;
1122 __le32 dword5;
1123 __le32 dword6;
1124 __le32 dword7;
1125 __le32 dword8;
1126 __le32 dword9;
1127 } __packed;
1128
1129 struct rtw89_tx_desc_info {
1130 u16 pkt_size;
1131 u8 wp_offset;
1132 u8 mac_id;
1133 u8 qsel;
1134 u8 ch_dma;
1135 u8 hdr_llc_len;
1136 bool is_bmc;
1137 bool en_wd_info;
1138 bool wd_page;
1139 bool use_rate;
1140 bool dis_data_fb;
1141 bool tid_indicate;
1142 bool agg_en;
1143 bool bk;
1144 u8 ampdu_density;
1145 u8 ampdu_num;
1146 bool sec_en;
1147 u8 addr_info_nr;
1148 u8 sec_keyid;
1149 u8 sec_type;
1150 u8 sec_cam_idx;
1151 u8 sec_seq[6];
1152 u16 data_rate;
1153 u16 data_retry_lowest_rate;
1154 bool fw_dl;
1155 u16 seq;
1156 bool a_ctrl_bsr;
1157 u8 hw_ssn_sel;
1158 #define RTW89_MGMT_HW_SSN_SEL 1
1159 u8 hw_seq_mode;
1160 #define RTW89_MGMT_HW_SEQ_MODE 1
1161 bool hiq;
1162 u8 port;
1163 bool er_cap;
1164 bool stbc;
1165 bool ldpc;
1166 };
1167
1168 struct rtw89_core_tx_request {
1169 enum rtw89_core_tx_type tx_type;
1170
1171 struct sk_buff *skb;
1172 struct rtw89_vif_link *rtwvif_link;
1173 struct rtw89_sta_link *rtwsta_link;
1174 struct rtw89_tx_desc_info desc_info;
1175 };
1176
1177 struct rtw89_txq {
1178 struct list_head list;
1179 unsigned long flags;
1180 int wait_cnt;
1181 };
1182
1183 struct rtw89_mac_ax_gnt {
1184 u8 gnt_bt_sw_en;
1185 u8 gnt_bt;
1186 u8 gnt_wl_sw_en;
1187 u8 gnt_wl;
1188 } __packed;
1189
1190 struct rtw89_mac_ax_wl_act {
1191 u8 wlan_act_en;
1192 u8 wlan_act;
1193 };
1194
1195 #define RTW89_MAC_AX_COEX_GNT_NR 2
1196 struct rtw89_mac_ax_coex_gnt {
1197 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR];
1198 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR];
1199 };
1200
1201 enum rtw89_btc_ncnt {
1202 BTC_NCNT_POWER_ON = 0x0,
1203 BTC_NCNT_POWER_OFF,
1204 BTC_NCNT_INIT_COEX,
1205 BTC_NCNT_SCAN_START,
1206 BTC_NCNT_SCAN_FINISH,
1207 BTC_NCNT_SPECIAL_PACKET,
1208 BTC_NCNT_SWITCH_BAND,
1209 BTC_NCNT_RFK_TIMEOUT,
1210 BTC_NCNT_SHOW_COEX_INFO,
1211 BTC_NCNT_ROLE_INFO,
1212 BTC_NCNT_CONTROL,
1213 BTC_NCNT_RADIO_STATE,
1214 BTC_NCNT_CUSTOMERIZE,
1215 BTC_NCNT_WL_RFK,
1216 BTC_NCNT_WL_STA,
1217 BTC_NCNT_WL_STA_LAST,
1218 BTC_NCNT_FWINFO,
1219 BTC_NCNT_TIMER,
1220 BTC_NCNT_SWITCH_CHBW,
1221 BTC_NCNT_RESUME_DL_FW,
1222 BTC_NCNT_COUNTRYCODE,
1223 BTC_NCNT_NUM,
1224 };
1225
1226 enum rtw89_btc_btinfo {
1227 BTC_BTINFO_L0 = 0,
1228 BTC_BTINFO_L1,
1229 BTC_BTINFO_L2,
1230 BTC_BTINFO_L3,
1231 BTC_BTINFO_H0,
1232 BTC_BTINFO_H1,
1233 BTC_BTINFO_H2,
1234 BTC_BTINFO_H3,
1235 BTC_BTINFO_MAX
1236 };
1237
1238 enum rtw89_btc_dcnt {
1239 BTC_DCNT_RUN = 0x0,
1240 BTC_DCNT_CX_RUNINFO,
1241 BTC_DCNT_RPT,
1242 BTC_DCNT_RPT_HANG,
1243 BTC_DCNT_CYCLE,
1244 BTC_DCNT_CYCLE_HANG,
1245 BTC_DCNT_W1,
1246 BTC_DCNT_W1_HANG,
1247 BTC_DCNT_B1,
1248 BTC_DCNT_B1_HANG,
1249 BTC_DCNT_TDMA_NONSYNC,
1250 BTC_DCNT_SLOT_NONSYNC,
1251 BTC_DCNT_BTCNT_HANG,
1252 BTC_DCNT_BTTX_HANG,
1253 BTC_DCNT_WL_SLOT_DRIFT,
1254 BTC_DCNT_WL_STA_LAST,
1255 BTC_DCNT_BT_SLOT_DRIFT,
1256 BTC_DCNT_BT_SLOT_FLOOD,
1257 BTC_DCNT_FDDT_TRIG,
1258 BTC_DCNT_E2G,
1259 BTC_DCNT_E2G_HANG,
1260 BTC_DCNT_WL_FW_VER_MATCH,
1261 BTC_DCNT_NULL_TX_FAIL,
1262 BTC_DCNT_WL_STA_NTFY,
1263 BTC_DCNT_NUM,
1264 };
1265
1266 enum rtw89_btc_wl_state_cnt {
1267 BTC_WCNT_SCANAP = 0x0,
1268 BTC_WCNT_DHCP,
1269 BTC_WCNT_EAPOL,
1270 BTC_WCNT_ARP,
1271 BTC_WCNT_SCBDUPDATE,
1272 BTC_WCNT_RFK_REQ,
1273 BTC_WCNT_RFK_GO,
1274 BTC_WCNT_RFK_REJECT,
1275 BTC_WCNT_RFK_TIMEOUT,
1276 BTC_WCNT_CH_UPDATE,
1277 BTC_WCNT_DBCC_ALL_2G,
1278 BTC_WCNT_DBCC_CHG,
1279 BTC_WCNT_RX_OK_LAST,
1280 BTC_WCNT_RX_OK_LAST2S,
1281 BTC_WCNT_RX_ERR_LAST,
1282 BTC_WCNT_RX_ERR_LAST2S,
1283 BTC_WCNT_RX_LAST,
1284 BTC_WCNT_NUM
1285 };
1286
1287 enum rtw89_btc_bt_state_cnt {
1288 BTC_BCNT_RETRY = 0x0,
1289 BTC_BCNT_REINIT,
1290 BTC_BCNT_REENABLE,
1291 BTC_BCNT_SCBDREAD,
1292 BTC_BCNT_RELINK,
1293 BTC_BCNT_IGNOWL,
1294 BTC_BCNT_INQPAG,
1295 BTC_BCNT_INQ,
1296 BTC_BCNT_PAGE,
1297 BTC_BCNT_ROLESW,
1298 BTC_BCNT_AFH,
1299 BTC_BCNT_INFOUPDATE,
1300 BTC_BCNT_INFOSAME,
1301 BTC_BCNT_SCBDUPDATE,
1302 BTC_BCNT_HIPRI_TX,
1303 BTC_BCNT_HIPRI_RX,
1304 BTC_BCNT_LOPRI_TX,
1305 BTC_BCNT_LOPRI_RX,
1306 BTC_BCNT_POLUT,
1307 BTC_BCNT_POLUT_NOW,
1308 BTC_BCNT_POLUT_DIFF,
1309 BTC_BCNT_RATECHG,
1310 BTC_BCNT_NUM,
1311 };
1312
1313 enum rtw89_btc_bt_profile {
1314 BTC_BT_NOPROFILE = 0,
1315 BTC_BT_HFP = BIT(0),
1316 BTC_BT_HID = BIT(1),
1317 BTC_BT_A2DP = BIT(2),
1318 BTC_BT_PAN = BIT(3),
1319 BTC_PROFILE_MAX = 4,
1320 };
1321
1322 struct rtw89_btc_ant_info {
1323 u8 type; /* shared, dedicated */
1324 u8 num;
1325 u8 isolation;
1326
1327 u8 single_pos: 1;/* Single antenna at S0 or S1 */
1328 u8 diversity: 1;
1329 u8 btg_pos: 2;
1330 u8 stream_cnt: 4;
1331 };
1332
1333 struct rtw89_btc_ant_info_v7 {
1334 u8 type; /* shared, dedicated(non-shared) */
1335 u8 num; /* antenna count */
1336 u8 isolation;
1337 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */
1338
1339 u8 diversity; /* only for wifi use 1-antenna */
1340 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */
1341 u8 stream_cnt; /* spatial_stream count */
1342 u8 rsvd;
1343 } __packed;
1344
1345 enum rtw89_tfc_dir {
1346 RTW89_TFC_UL,
1347 RTW89_TFC_DL,
1348 };
1349
1350 struct rtw89_btc_wl_smap {
1351 u32 busy: 1;
1352 u32 scan: 1;
1353 u32 connecting: 1;
1354 u32 roaming: 1;
1355 u32 dbccing: 1;
1356 u32 transacting: 1;
1357 u32 _4way: 1;
1358 u32 rf_off: 1;
1359 u32 lps: 2;
1360 u32 ips: 1;
1361 u32 init_ok: 1;
1362 u32 traffic_dir : 2;
1363 u32 rf_off_pre: 1;
1364 u32 lps_pre: 2;
1365 u32 lps_exiting: 1;
1366 u32 emlsr: 1;
1367 };
1368
1369 enum rtw89_tfc_lv {
1370 RTW89_TFC_IDLE,
1371 RTW89_TFC_ULTRA_LOW,
1372 RTW89_TFC_LOW,
1373 RTW89_TFC_MID,
1374 RTW89_TFC_HIGH,
1375 };
1376
1377 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */
1378 DECLARE_EWMA(tp, 10, 2);
1379
1380 struct rtw89_traffic_stats {
1381 /* units in bytes */
1382 u64 tx_unicast;
1383 u64 rx_unicast;
1384 u32 tx_avg_len;
1385 u32 rx_avg_len;
1386
1387 /* count for packets */
1388 u64 tx_cnt;
1389 u64 rx_cnt;
1390
1391 /* units in Mbps */
1392 u32 tx_throughput;
1393 u32 rx_throughput;
1394 u32 tx_throughput_raw;
1395 u32 rx_throughput_raw;
1396
1397 u32 rx_tf_acc;
1398 u32 rx_tf_periodic;
1399
1400 enum rtw89_tfc_lv tx_tfc_lv;
1401 enum rtw89_tfc_lv rx_tfc_lv;
1402 struct ewma_tp tx_ewma_tp;
1403 struct ewma_tp rx_ewma_tp;
1404
1405 u16 tx_rate;
1406 u16 rx_rate;
1407 };
1408
1409 struct rtw89_btc_chdef {
1410 u8 center_ch;
1411 u8 band;
1412 u8 chan;
1413 enum rtw89_sc_offset offset;
1414 enum rtw89_bandwidth bw;
1415 };
1416
1417 struct rtw89_btc_statistic {
1418 u8 rssi; /* 0%~110% (dBm = rssi -110) */
1419 struct rtw89_traffic_stats traffic;
1420 };
1421
1422 #define BTC_WL_RSSI_THMAX 4
1423
1424 struct rtw89_btc_wl_link_info {
1425 struct rtw89_btc_chdef chdef;
1426 struct rtw89_btc_statistic stat;
1427 enum rtw89_tfc_dir dir;
1428 u8 rssi_state[BTC_WL_RSSI_THMAX];
1429 u8 mac_addr[ETH_ALEN];
1430 u8 busy;
1431 u8 ch;
1432 u8 bw;
1433 u8 band;
1434 u8 role;
1435 u8 pid;
1436 u8 phy;
1437 u8 dtim_period;
1438 u8 mode;
1439 u8 tx_1ss_limit;
1440
1441 u8 mac_id;
1442 u8 tx_retry;
1443
1444 u32 bcn_period;
1445 u32 busy_t;
1446 u32 tx_time;
1447 u32 client_cnt;
1448 u32 rx_rate_drop_cnt;
1449 u32 noa_duration;
1450
1451 u32 active: 1;
1452 u32 noa: 1;
1453 u32 client_ps: 1;
1454 u32 connected: 2;
1455 };
1456
1457 union rtw89_btc_wl_state_map {
1458 u32 val;
1459 struct rtw89_btc_wl_smap map;
1460 };
1461
1462 struct rtw89_btc_bt_hfp_desc {
1463 u32 exist: 1;
1464 u32 type: 2;
1465 u32 rsvd: 29;
1466 };
1467
1468 struct rtw89_btc_bt_hid_desc {
1469 u32 exist: 1;
1470 u32 slot_info: 2;
1471 u32 pair_cnt: 2;
1472 u32 type: 8;
1473 u32 rsvd: 19;
1474 };
1475
1476 struct rtw89_btc_bt_a2dp_desc {
1477 u8 exist: 1;
1478 u8 exist_last: 1;
1479 u8 play_latency: 1;
1480 u8 type: 3;
1481 u8 active: 1;
1482 u8 sink: 1;
1483 u32 handle_update: 1;
1484 u32 devinfo_query: 1;
1485 u32 no_empty_streak_2s: 8;
1486 u32 no_empty_streak_max: 8;
1487 u32 rsvd: 6;
1488
1489 u8 bitpool;
1490 u16 vendor_id;
1491 u32 device_name;
1492 u32 flush_time;
1493 };
1494
1495 struct rtw89_btc_bt_pan_desc {
1496 u32 exist: 1;
1497 u32 type: 1;
1498 u32 active: 1;
1499 u32 rsvd: 29;
1500 };
1501
1502 struct rtw89_btc_bt_rfk_info {
1503 u32 run: 1;
1504 u32 req: 1;
1505 u32 timeout: 1;
1506 u32 rsvd: 29;
1507 };
1508
1509 union rtw89_btc_bt_rfk_info_map {
1510 u32 val;
1511 struct rtw89_btc_bt_rfk_info map;
1512 };
1513
1514 struct rtw89_btc_bt_ver_info {
1515 u32 fw_coex; /* match with which coex_ver */
1516 u32 fw;
1517 };
1518
1519 struct rtw89_btc_bool_sta_chg {
1520 u32 now: 1;
1521 u32 last: 1;
1522 u32 remain: 1;
1523 u32 srvd: 29;
1524 };
1525
1526 struct rtw89_btc_u8_sta_chg {
1527 u8 now;
1528 u8 last;
1529 u8 remain;
1530 u8 rsvd;
1531 };
1532
1533 struct rtw89_btc_wl_scan_info {
1534 u8 band[RTW89_PHY_MAX];
1535 u8 phy_map;
1536 u8 rsvd;
1537 };
1538
1539 struct rtw89_btc_wl_dbcc_info {
1540 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */
1541 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */
1542 u8 real_band[RTW89_PHY_MAX];
1543 u8 role[RTW89_PHY_MAX]; /* role in each phy */
1544 };
1545
1546 struct rtw89_btc_wl_active_role {
1547 u8 connected: 1;
1548 u8 pid: 3;
1549 u8 phy: 1;
1550 u8 noa: 1;
1551 u8 band: 2;
1552
1553 u8 client_ps: 1;
1554 u8 bw: 7;
1555
1556 u8 role;
1557 u8 ch;
1558
1559 u16 tx_lvl;
1560 u16 rx_lvl;
1561 u16 tx_rate;
1562 u16 rx_rate;
1563 };
1564
1565 struct rtw89_btc_wl_active_role_v1 {
1566 u8 connected: 1;
1567 u8 pid: 3;
1568 u8 phy: 1;
1569 u8 noa: 1;
1570 u8 band: 2;
1571
1572 u8 client_ps: 1;
1573 u8 bw: 7;
1574
1575 u8 role;
1576 u8 ch;
1577
1578 u16 tx_lvl;
1579 u16 rx_lvl;
1580 u16 tx_rate;
1581 u16 rx_rate;
1582
1583 u32 noa_duration; /* ms */
1584 };
1585
1586 struct rtw89_btc_wl_active_role_v2 {
1587 u8 connected: 1;
1588 u8 pid: 3;
1589 u8 phy: 1;
1590 u8 noa: 1;
1591 u8 band: 2;
1592
1593 u8 client_ps: 1;
1594 u8 bw: 7;
1595
1596 u8 role;
1597 u8 ch;
1598
1599 u32 noa_duration; /* ms */
1600 };
1601
1602 struct rtw89_btc_wl_active_role_v7 {
1603 u8 connected;
1604 u8 pid;
1605 u8 phy;
1606 u8 noa;
1607
1608 u8 band;
1609 u8 client_ps;
1610 u8 bw;
1611 u8 role;
1612
1613 u8 ch;
1614 u8 noa_dur;
1615 u8 client_cnt;
1616 u8 rsvd2;
1617 } __packed;
1618
1619 struct rtw89_btc_wl_role_info_bpos {
1620 u16 none: 1;
1621 u16 station: 1;
1622 u16 ap: 1;
1623 u16 vap: 1;
1624 u16 adhoc: 1;
1625 u16 adhoc_master: 1;
1626 u16 mesh: 1;
1627 u16 moniter: 1;
1628 u16 p2p_device: 1;
1629 u16 p2p_gc: 1;
1630 u16 p2p_go: 1;
1631 u16 nan: 1;
1632 };
1633
1634 struct rtw89_btc_wl_scc_ctrl {
1635 u8 null_role1;
1636 u8 null_role2;
1637 u8 ebt_null; /* if tx null at EBT slot */
1638 };
1639
1640 union rtw89_btc_wl_role_info_map {
1641 u16 val;
1642 struct rtw89_btc_wl_role_info_bpos role;
1643 };
1644
1645 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */
1646 u8 connect_cnt;
1647 u8 link_mode;
1648 union rtw89_btc_wl_role_info_map role_map;
1649 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM];
1650 };
1651
1652 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */
1653 u8 connect_cnt;
1654 u8 link_mode;
1655 union rtw89_btc_wl_role_info_map role_map;
1656 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM];
1657 u32 mrole_type; /* btc_wl_mrole_type */
1658 u32 mrole_noa_duration; /* ms */
1659
1660 u32 dbcc_en: 1;
1661 u32 dbcc_chg: 1;
1662 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1663 u32 link_mode_chg: 1;
1664 u32 rsvd: 27;
1665 };
1666
1667 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */
1668 u8 connect_cnt;
1669 u8 link_mode;
1670 union rtw89_btc_wl_role_info_map role_map;
1671 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM];
1672 u32 mrole_type; /* btc_wl_mrole_type */
1673 u32 mrole_noa_duration; /* ms */
1674
1675 u32 dbcc_en: 1;
1676 u32 dbcc_chg: 1;
1677 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1678 u32 link_mode_chg: 1;
1679 u32 rsvd: 27;
1680 };
1681
1682 struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */
1683 u8 connected;
1684 u8 pid;
1685 u8 phy;
1686 u8 noa;
1687
1688 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */
1689 u8 active; /* 0:rlink is under doze */
1690 u8 bw; /* enum channel_width */
1691 u8 role; /*enum role_type */
1692
1693 u8 ch;
1694 u8 noa_dur; /* ms */
1695 u8 client_cnt; /* for Role = P2P-Go/AP */
1696 u8 mode; /* wifi protocol */
1697 } __packed;
1698
1699 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6
1700 struct rtw89_btc_wl_role_info_v7 { /* struct size must be n*4 bytes */
1701 u8 connect_cnt;
1702 u8 link_mode;
1703 u8 link_mode_chg;
1704 u8 p2p_2g;
1705
1706 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER];
1707
1708 u32 role_map;
1709 u32 mrole_type; /* btc_wl_mrole_type */
1710 u32 mrole_noa_duration; /* ms */
1711 u32 dbcc_en;
1712 u32 dbcc_chg;
1713 u32 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1714 } __packed;
1715
1716 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */
1717 u8 connect_cnt;
1718 u8 link_mode;
1719 u8 link_mode_chg;
1720 u8 p2p_2g;
1721
1722 u8 pta_req_band;
1723 u8 dbcc_en; /* 1+1 and 2.4G-included */
1724 u8 dbcc_chg;
1725 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1726
1727 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM];
1728
1729 u32 role_map;
1730 u32 mrole_type; /* btc_wl_mrole_type */
1731 u32 mrole_noa_duration; /* ms */
1732 } __packed;
1733
1734 struct rtw89_btc_wl_ver_info {
1735 u32 fw_coex; /* match with which coex_ver */
1736 u32 fw;
1737 u32 mac;
1738 u32 bb;
1739 u32 rf;
1740 };
1741
1742 struct rtw89_btc_wl_afh_info {
1743 u8 en;
1744 u8 ch;
1745 u8 bw;
1746 u8 rsvd;
1747 } __packed;
1748
1749 struct rtw89_btc_wl_rfk_info {
1750 u32 state: 2;
1751 u32 path_map: 4;
1752 u32 phy_map: 2;
1753 u32 band: 2;
1754 u32 type: 8;
1755 u32 rsvd: 14;
1756
1757 u32 start_time;
1758 u32 proc_time;
1759 };
1760
1761 struct rtw89_btc_bt_smap {
1762 u32 connect: 1;
1763 u32 ble_connect: 1;
1764 u32 acl_busy: 1;
1765 u32 sco_busy: 1;
1766 u32 mesh_busy: 1;
1767 u32 inq_pag: 1;
1768 };
1769
1770 union rtw89_btc_bt_state_map {
1771 u32 val;
1772 struct rtw89_btc_bt_smap map;
1773 };
1774
1775 #define BTC_BT_RSSI_THMAX 4
1776 #define BTC_BT_AFH_GROUP 12
1777 #define BTC_BT_AFH_LE_GROUP 5
1778
1779 struct rtw89_btc_bt_link_info {
1780 struct rtw89_btc_u8_sta_chg profile_cnt;
1781 struct rtw89_btc_bool_sta_chg multi_link;
1782 struct rtw89_btc_bool_sta_chg relink;
1783 struct rtw89_btc_bt_hfp_desc hfp_desc;
1784 struct rtw89_btc_bt_hid_desc hid_desc;
1785 struct rtw89_btc_bt_a2dp_desc a2dp_desc;
1786 struct rtw89_btc_bt_pan_desc pan_desc;
1787 union rtw89_btc_bt_state_map status;
1788
1789 u8 sut_pwr_level[BTC_PROFILE_MAX];
1790 u8 golden_rx_shift[BTC_PROFILE_MAX];
1791 u8 rssi_state[BTC_BT_RSSI_THMAX];
1792 u8 afh_map[BTC_BT_AFH_GROUP];
1793 u8 afh_map_le[BTC_BT_AFH_LE_GROUP];
1794
1795 u32 role_sw: 1;
1796 u32 slave_role: 1;
1797 u32 afh_update: 1;
1798 u32 cqddr: 1;
1799 u32 rssi: 8;
1800 u32 tx_3m: 1;
1801 u32 rsvd: 19;
1802 };
1803
1804 struct rtw89_btc_3rdcx_info {
1805 u8 type; /* 0: none, 1:zigbee, 2:LTE */
1806 u8 hw_coex;
1807 u16 rsvd;
1808 };
1809
1810 struct rtw89_btc_dm_emap {
1811 u32 init: 1;
1812 u32 pta_owner: 1;
1813 u32 wl_rfk_timeout: 1;
1814 u32 bt_rfk_timeout: 1;
1815 u32 wl_fw_hang: 1;
1816 u32 cycle_hang: 1;
1817 u32 w1_hang: 1;
1818 u32 b1_hang: 1;
1819 u32 tdma_no_sync: 1;
1820 u32 slot_no_sync: 1;
1821 u32 wl_slot_drift: 1;
1822 u32 bt_slot_drift: 1;
1823 u32 role_num_mismatch: 1;
1824 u32 null1_tx_late: 1;
1825 u32 bt_afh_conflict: 1;
1826 u32 bt_leafh_conflict: 1;
1827 u32 bt_slot_flood: 1;
1828 u32 wl_e2g_hang: 1;
1829 u32 wl_ver_mismatch: 1;
1830 u32 bt_ver_mismatch: 1;
1831 u32 rfe_type0: 1;
1832 u32 h2c_buffer_over: 1;
1833 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/
1834 u32 wl_no_sta_ntfy: 1;
1835
1836 u32 h2c_bmap_mismatch: 1;
1837 u32 c2h_bmap_mismatch: 1;
1838 u32 h2c_struct_invalid: 1;
1839 u32 c2h_struct_invalid: 1;
1840 u32 h2c_c2h_buffer_mismatch: 1;
1841 };
1842
1843 union rtw89_btc_dm_error_map {
1844 u32 val;
1845 struct rtw89_btc_dm_emap map;
1846 };
1847
1848 struct rtw89_btc_rf_para {
1849 u32 tx_pwr_freerun;
1850 u32 rx_gain_freerun;
1851 u32 tx_pwr_perpkt;
1852 u32 rx_gain_perpkt;
1853 };
1854
1855 struct rtw89_btc_wl_nhm {
1856 u8 instant_wl_nhm_dbm;
1857 u8 instant_wl_nhm_per_mhz;
1858 u16 valid_record_times;
1859 s8 record_pwr[16];
1860 u8 record_ratio[16];
1861 s8 pwr; /* dbm_per_MHz */
1862 u8 ratio;
1863 u8 current_status;
1864 u8 refresh;
1865 bool start_flag;
1866 s8 pwr_max;
1867 s8 pwr_min;
1868 };
1869
1870 struct rtw89_btc_wl_info {
1871 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM];
1872 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM];
1873 struct rtw89_btc_wl_rfk_info rfk_info;
1874 struct rtw89_btc_wl_ver_info ver_info;
1875 struct rtw89_btc_wl_afh_info afh_info;
1876 struct rtw89_btc_wl_role_info role_info;
1877 struct rtw89_btc_wl_role_info_v1 role_info_v1;
1878 struct rtw89_btc_wl_role_info_v2 role_info_v2;
1879 struct rtw89_btc_wl_role_info_v7 role_info_v7;
1880 struct rtw89_btc_wl_role_info_v8 role_info_v8;
1881 struct rtw89_btc_wl_scan_info scan_info;
1882 struct rtw89_btc_wl_dbcc_info dbcc_info;
1883 struct rtw89_btc_rf_para rf_para;
1884 struct rtw89_btc_wl_nhm nhm;
1885 union rtw89_btc_wl_state_map status;
1886
1887 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX];
1888 u8 rssi_level;
1889 u8 cn_report;
1890 u8 coex_mode;
1891 u8 pta_req_mac;
1892 u8 bt_polut_type[RTW89_PHY_MAX]; /* BT polluted WL-Tx type for phy0/1 */
1893
1894 bool is_5g_hi_channel;
1895 bool pta_reg_mac_chg;
1896 bool bg_mode;
1897 bool he_mode;
1898 bool scbd_change;
1899 bool fw_ver_mismatch;
1900 bool client_cnt_inc_2g;
1901 u32 scbd;
1902 };
1903
1904 struct rtw89_btc_module {
1905 struct rtw89_btc_ant_info ant;
1906 u8 rfe_type;
1907 u8 cv;
1908
1909 u8 bt_solo: 1;
1910 u8 bt_pos: 1;
1911 u8 switch_type: 1;
1912 u8 wa_type: 3;
1913
1914 u8 kt_ver_adie;
1915 };
1916
1917 struct rtw89_btc_module_v7 {
1918 u8 rfe_type;
1919 u8 kt_ver;
1920 u8 bt_solo;
1921 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/
1922
1923 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */
1924 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */
1925 u8 kt_ver_adie;
1926 u8 rsvd;
1927
1928 struct rtw89_btc_ant_info_v7 ant;
1929 } __packed;
1930
1931 union rtw89_btc_module_info {
1932 struct rtw89_btc_module md;
1933 struct rtw89_btc_module_v7 md_v7;
1934 };
1935
1936 #define RTW89_BTC_DM_MAXSTEP 30
1937 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8)
1938
1939 struct rtw89_btc_dm_step {
1940 u16 step[RTW89_BTC_DM_MAXSTEP];
1941 u8 step_pos;
1942 bool step_ov;
1943 };
1944
1945 struct rtw89_btc_init_info {
1946 struct rtw89_btc_module module;
1947 u8 wl_guard_ch;
1948
1949 u8 wl_only: 1;
1950 u8 wl_init_ok: 1;
1951 u8 dbcc_en: 1;
1952 u8 cx_other: 1;
1953 u8 bt_only: 1;
1954
1955 u16 rsvd;
1956 };
1957
1958 struct rtw89_btc_init_info_v7 {
1959 u8 wl_guard_ch;
1960 u8 wl_only;
1961 u8 wl_init_ok;
1962 u8 rsvd3;
1963
1964 u8 cx_other;
1965 u8 bt_only;
1966 u8 pta_mode;
1967 u8 pta_direction;
1968
1969 struct rtw89_btc_module_v7 module;
1970 } __packed;
1971
1972 union rtw89_btc_init_info_u {
1973 struct rtw89_btc_init_info init;
1974 struct rtw89_btc_init_info_v7 init_v7;
1975 };
1976
1977 struct rtw89_btc_wl_tx_limit_para {
1978 u16 enable;
1979 u32 tx_time; /* unit: us */
1980 u16 tx_retry;
1981 };
1982
1983 enum rtw89_btc_bt_scan_type {
1984 BTC_SCAN_INQ = 0,
1985 BTC_SCAN_PAGE,
1986 BTC_SCAN_BLE,
1987 BTC_SCAN_INIT,
1988 BTC_SCAN_TV,
1989 BTC_SCAN_ADV,
1990 BTC_SCAN_MAX1,
1991 };
1992
1993 enum rtw89_btc_ble_scan_type {
1994 CXSCAN_BG = 0,
1995 CXSCAN_INIT,
1996 CXSCAN_LE,
1997 CXSCAN_MAX
1998 };
1999
2000 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0)
2001 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1)
2002
2003 struct rtw89_btc_bt_scan_info_v1 {
2004 __le16 win;
2005 __le16 intvl;
2006 __le32 flags;
2007 } __packed;
2008
2009 struct rtw89_btc_bt_scan_info_v2 {
2010 __le16 win;
2011 __le16 intvl;
2012 } __packed;
2013
2014 struct rtw89_btc_fbtc_btscan_v1 {
2015 u8 fver; /* btc_ver::fcxbtscan */
2016 u8 rsvd;
2017 __le16 rsvd2;
2018 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1];
2019 } __packed;
2020
2021 struct rtw89_btc_fbtc_btscan_v2 {
2022 u8 fver; /* btc_ver::fcxbtscan */
2023 u8 type;
2024 __le16 rsvd2;
2025 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX];
2026 } __packed;
2027
2028 struct rtw89_btc_fbtc_btscan_v7 {
2029 u8 fver; /* btc_ver::fcxbtscan */
2030 u8 type;
2031 u8 rsvd0;
2032 u8 rsvd1;
2033 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX];
2034 } __packed;
2035
2036 union rtw89_btc_fbtc_btscan {
2037 struct rtw89_btc_fbtc_btscan_v1 v1;
2038 struct rtw89_btc_fbtc_btscan_v2 v2;
2039 struct rtw89_btc_fbtc_btscan_v7 v7;
2040 };
2041
2042 struct rtw89_btc_bt_info {
2043 struct rtw89_btc_bt_link_info link_info;
2044 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1];
2045 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX];
2046 struct rtw89_btc_bt_ver_info ver_info;
2047 struct rtw89_btc_bool_sta_chg enable;
2048 struct rtw89_btc_bool_sta_chg inq_pag;
2049 struct rtw89_btc_rf_para rf_para;
2050 union rtw89_btc_bt_rfk_info_map rfk_info;
2051
2052 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */
2053 u8 rssi_level;
2054
2055 u32 scbd;
2056 u32 feature;
2057
2058 u32 mbx_avl: 1;
2059 u32 whql_test: 1;
2060 u32 igno_wl: 1;
2061 u32 reinit: 1;
2062 u32 ble_scan_en: 1;
2063 u32 btg_type: 1;
2064 u32 inq: 1;
2065 u32 pag: 1;
2066 u32 run_patch_code: 1;
2067 u32 hi_lna_rx: 1;
2068 u32 scan_rx_low_pri: 1;
2069 u32 scan_info_update: 1;
2070 u32 lna_constrain: 3;
2071 u32 rsvd: 17;
2072 };
2073
2074 struct rtw89_btc_cx {
2075 struct rtw89_btc_wl_info wl;
2076 struct rtw89_btc_bt_info bt;
2077 struct rtw89_btc_3rdcx_info other;
2078 u32 state_map;
2079 u32 cnt_bt[BTC_BCNT_NUM];
2080 u32 cnt_wl[BTC_WCNT_NUM];
2081 };
2082
2083 struct rtw89_btc_fbtc_tdma {
2084 u8 type; /* btc_ver::fcxtdma */
2085 u8 rxflctrl;
2086 u8 txpause;
2087 u8 wtgle_n;
2088 u8 leak_n;
2089 u8 ext_ctrl;
2090 u8 rxflctrl_role;
2091 u8 option_ctrl;
2092 } __packed;
2093
2094 struct rtw89_btc_fbtc_tdma_v3 {
2095 u8 fver; /* btc_ver::fcxtdma */
2096 u8 rsvd;
2097 __le16 rsvd1;
2098 struct rtw89_btc_fbtc_tdma tdma;
2099 } __packed;
2100
2101 union rtw89_btc_fbtc_tdma_le32 {
2102 struct rtw89_btc_fbtc_tdma v1;
2103 struct rtw89_btc_fbtc_tdma_v3 v3;
2104 };
2105
2106 #define CXMREG_MAX 30
2107 #define CXMREG_MAX_V2 20
2108 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/
2109 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */
2110
2111 enum rtw89_btc_bt_sta_counter {
2112 BTC_BCNT_RFK_REQ = 0,
2113 BTC_BCNT_RFK_GO = 1,
2114 BTC_BCNT_RFK_REJECT = 2,
2115 BTC_BCNT_RFK_FAIL = 3,
2116 BTC_BCNT_RFK_TIMEOUT = 4,
2117 BTC_BCNT_HI_TX = 5,
2118 BTC_BCNT_HI_RX = 6,
2119 BTC_BCNT_LO_TX = 7,
2120 BTC_BCNT_LO_RX = 8,
2121 BTC_BCNT_POLLUTED = 9,
2122 BTC_BCNT_STA_MAX
2123 };
2124
2125 enum rtw89_btc_bt_sta_counter_v105 {
2126 BTC_BCNT_RFK_REQ_V105 = 0,
2127 BTC_BCNT_HI_TX_V105 = 1,
2128 BTC_BCNT_HI_RX_V105 = 2,
2129 BTC_BCNT_LO_TX_V105 = 3,
2130 BTC_BCNT_LO_RX_V105 = 4,
2131 BTC_BCNT_POLLUTED_V105 = 5,
2132 BTC_BCNT_STA_MAX_V105
2133 };
2134
2135 struct rtw89_btc_fbtc_rpt_ctrl_v1 {
2136 u16 fver; /* btc_ver::fcxbtcrpt */
2137 u16 rpt_cnt; /* tmr counters */
2138 u32 wl_fw_coex_ver; /* match which driver's coex version */
2139 u32 wl_fw_cx_offload;
2140 u32 wl_fw_ver;
2141 u32 rpt_enable;
2142 u32 rpt_para; /* ms */
2143 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */
2144 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */
2145 u32 mb_recv_cnt; /* fw recv mailbox counter */
2146 u32 mb_a2dp_empty_cnt; /* a2dp empty count */
2147 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */
2148 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */
2149 u32 bt_rfk_cnt[BTC_BCNT_HI_TX];
2150 u32 c2h_cnt; /* fw send c2h counter */
2151 u32 h2c_cnt; /* fw recv h2c counter */
2152 } __packed;
2153
2154 struct rtw89_btc_fbtc_rpt_ctrl_info {
2155 __le32 cnt; /* fw report counter */
2156 __le32 en; /* report map */
2157 __le32 para; /* not used */
2158
2159 __le32 cnt_c2h; /* fw send c2h counter */
2160 __le32 cnt_h2c; /* fw recv h2c counter */
2161 __le32 len_c2h; /* The total length of the last C2H */
2162
2163 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
2164 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
2165 } __packed;
2166
2167 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 {
2168 __le32 cx_ver; /* match which driver's coex version */
2169 __le32 fw_ver;
2170 __le32 en; /* report map */
2171
2172 __le16 cnt; /* fw report counter */
2173 __le16 cnt_c2h; /* fw send c2h counter */
2174 __le16 cnt_h2c; /* fw recv h2c counter */
2175 __le16 len_c2h; /* The total length of the last C2H */
2176
2177 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
2178 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
2179 } __packed;
2180
2181 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 {
2182 __le16 cnt; /* fw report counter */
2183 __le16 cnt_c2h; /* fw send c2h counter */
2184 __le16 cnt_h2c; /* fw recv h2c counter */
2185 __le16 len_c2h; /* The total length of the last C2H */
2186
2187 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
2188 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
2189
2190 __le32 cx_ver; /* match which driver's coex version */
2191 __le32 fw_ver;
2192 __le32 en; /* report map */
2193 } __packed;
2194
2195 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info {
2196 __le32 cx_ver; /* match which driver's coex version */
2197 __le32 cx_offload;
2198 __le32 fw_ver;
2199 } __packed;
2200
2201 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty {
2202 __le32 cnt_empty; /* a2dp empty count */
2203 __le32 cnt_flowctrl; /* a2dp empty flow control counter */
2204 __le32 cnt_tx;
2205 __le32 cnt_ack;
2206 __le32 cnt_nack;
2207 } __packed;
2208
2209 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox {
2210 __le32 cnt_send_ok; /* fw send mailbox ok counter */
2211 __le32 cnt_send_fail; /* fw send mailbox fail counter */
2212 __le32 cnt_recv; /* fw recv mailbox counter */
2213 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp;
2214 } __packed;
2215
2216 struct rtw89_btc_fbtc_rpt_ctrl_v4 {
2217 u8 fver;
2218 u8 rsvd;
2219 __le16 rsvd1;
2220 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info;
2221 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info;
2222 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2223 __le32 bt_cnt[BTC_BCNT_STA_MAX];
2224 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX];
2225 } __packed;
2226
2227 struct rtw89_btc_fbtc_rpt_ctrl_v5 {
2228 u8 fver;
2229 u8 rsvd;
2230 __le16 rsvd1;
2231
2232 u8 gnt_val[RTW89_PHY_MAX][4];
2233 __le16 bt_cnt[BTC_BCNT_STA_MAX];
2234
2235 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
2236 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2237 } __packed;
2238
2239 struct rtw89_btc_fbtc_rpt_ctrl_v105 {
2240 u8 fver;
2241 u8 rsvd;
2242 __le16 rsvd1;
2243
2244 u8 gnt_val[RTW89_PHY_MAX][4];
2245 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
2246
2247 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
2248 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2249 } __packed;
2250
2251 struct rtw89_btc_fbtc_rpt_ctrl_v7 {
2252 u8 fver;
2253 u8 rsvd0;
2254 u8 rsvd1;
2255 u8 rsvd2;
2256
2257 u8 gnt_val[RTW89_PHY_MAX][4];
2258 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
2259
2260 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info;
2261 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2262 } __packed;
2263
2264 struct rtw89_btc_fbtc_rpt_ctrl_v8 {
2265 u8 fver;
2266 u8 rsvd0;
2267 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */
2268 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */
2269
2270 u8 gnt_val[RTW89_PHY_MAX][4];
2271 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
2272
2273 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info;
2274 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2275 } __packed;
2276
2277 union rtw89_btc_fbtc_rpt_ctrl_ver_info {
2278 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1;
2279 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4;
2280 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5;
2281 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105;
2282 struct rtw89_btc_fbtc_rpt_ctrl_v7 v7;
2283 struct rtw89_btc_fbtc_rpt_ctrl_v8 v8;
2284 };
2285
2286 enum rtw89_fbtc_ext_ctrl_type {
2287 CXECTL_OFF = 0x0, /* tdma off */
2288 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */
2289 CXECTL_EXT = 0x2,
2290 CXECTL_MAX
2291 };
2292
2293 union rtw89_btc_fbtc_rxflct {
2294 u8 val;
2295 u8 type: 3;
2296 u8 tgln_n: 5;
2297 };
2298
2299 enum rtw89_btc_cxst_state {
2300 CXST_OFF = 0x0,
2301 CXST_B2W = 0x1,
2302 CXST_W1 = 0x2,
2303 CXST_W2 = 0x3,
2304 CXST_W2B = 0x4,
2305 CXST_B1 = 0x5,
2306 CXST_B2 = 0x6,
2307 CXST_B3 = 0x7,
2308 CXST_B4 = 0x8,
2309 CXST_LK = 0x9,
2310 CXST_BLK = 0xa,
2311 CXST_E2G = 0xb,
2312 CXST_E5G = 0xc,
2313 CXST_EBT = 0xd,
2314 CXST_ENULL = 0xe,
2315 CXST_WLK = 0xf,
2316 CXST_W1FDD = 0x10,
2317 CXST_B1FDD = 0x11,
2318 CXST_MAX = 0x12,
2319 };
2320
2321 enum rtw89_btc_cxevnt {
2322 CXEVNT_TDMA_ENTRY = 0x0,
2323 CXEVNT_WL_TMR,
2324 CXEVNT_B1_TMR,
2325 CXEVNT_B2_TMR,
2326 CXEVNT_B3_TMR,
2327 CXEVNT_B4_TMR,
2328 CXEVNT_W2B_TMR,
2329 CXEVNT_B2W_TMR,
2330 CXEVNT_BCN_EARLY,
2331 CXEVNT_A2DP_EMPTY,
2332 CXEVNT_LK_END,
2333 CXEVNT_RX_ISR,
2334 CXEVNT_RX_FC0,
2335 CXEVNT_RX_FC1,
2336 CXEVNT_BT_RELINK,
2337 CXEVNT_BT_RETRY,
2338 CXEVNT_E2G,
2339 CXEVNT_E5G,
2340 CXEVNT_EBT,
2341 CXEVNT_ENULL,
2342 CXEVNT_DRV_WLK,
2343 CXEVNT_BCN_OK,
2344 CXEVNT_BT_CHANGE,
2345 CXEVNT_EBT_EXTEND,
2346 CXEVNT_E2G_NULL1,
2347 CXEVNT_B1FDD_TMR,
2348 CXEVNT_MAX
2349 };
2350
2351 enum {
2352 CXBCN_ALL = 0x0,
2353 CXBCN_ALL_OK,
2354 CXBCN_BT_SLOT,
2355 CXBCN_BT_OK,
2356 CXBCN_MAX
2357 };
2358
2359 enum btc_slot_type {
2360 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */
2361 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/
2362 CXSTYPE_NUM,
2363 };
2364
2365 enum { /* TIME */
2366 CXT_BT = 0x0,
2367 CXT_WL = 0x1,
2368 CXT_MAX
2369 };
2370
2371 enum { /* TIME-A2DP */
2372 CXT_FLCTRL_OFF = 0x0,
2373 CXT_FLCTRL_ON = 0x1,
2374 CXT_FLCTRL_MAX
2375 };
2376
2377 enum { /* STEP TYPE */
2378 CXSTEP_NONE = 0x0,
2379 CXSTEP_EVNT = 0x1,
2380 CXSTEP_SLOT = 0x2,
2381 CXSTEP_MAX,
2382 };
2383
2384 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */
2385 RPT_BT_AFH_SEQ_LEGACY = 0x10,
2386 RPT_BT_AFH_SEQ_LE = 0x20
2387 };
2388
2389 #define BTC_DBG_MAX1 32
2390 struct rtw89_btc_fbtc_gpio_dbg_v1 {
2391 u8 fver; /* btc_ver::fcxgpiodbg */
2392 u8 rsvd;
2393 __le16 rsvd2;
2394 __le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */
2395 __le32 pre_state; /* the debug signal is 1 or 0 */
2396 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */
2397 } __packed;
2398
2399 struct rtw89_btc_fbtc_gpio_dbg_v7 {
2400 u8 fver;
2401 u8 rsvd0;
2402 u8 rsvd1;
2403 u8 rsvd2;
2404
2405 u8 gpio_map[BTC_DBG_MAX1];
2406
2407 __le32 en_map;
2408 __le32 pre_state;
2409 } __packed;
2410
2411 union rtw89_btc_fbtc_gpio_dbg {
2412 struct rtw89_btc_fbtc_gpio_dbg_v1 v1;
2413 struct rtw89_btc_fbtc_gpio_dbg_v7 v7;
2414 };
2415
2416 struct rtw89_btc_fbtc_mreg_val_v1 {
2417 u8 fver; /* btc_ver::fcxmreg */
2418 u8 reg_num;
2419 __le16 rsvd;
2420 __le32 mreg_val[CXMREG_MAX];
2421 } __packed;
2422
2423 struct rtw89_btc_fbtc_mreg_val_v2 {
2424 u8 fver; /* btc_ver::fcxmreg */
2425 u8 reg_num;
2426 __le16 rsvd;
2427 __le32 mreg_val[CXMREG_MAX_V2];
2428 } __packed;
2429
2430 struct rtw89_btc_fbtc_mreg_val_v7 {
2431 u8 fver;
2432 u8 reg_num;
2433 u8 rsvd0;
2434 u8 rsvd1;
2435 __le32 mreg_val[CXMREG_MAX_V2];
2436 } __packed;
2437
2438 union rtw89_btc_fbtc_mreg_val {
2439 struct rtw89_btc_fbtc_mreg_val_v1 v1;
2440 struct rtw89_btc_fbtc_mreg_val_v2 v2;
2441 struct rtw89_btc_fbtc_mreg_val_v7 v7;
2442 };
2443
2444 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \
2445 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \
2446 .offset = cpu_to_le32(__offset), }
2447
2448 struct rtw89_btc_fbtc_mreg {
2449 __le16 type;
2450 __le16 bytes;
2451 __le32 offset;
2452 } __packed;
2453
2454 struct rtw89_btc_fbtc_slot {
2455 __le16 dur;
2456 __le32 cxtbl;
2457 __le16 cxtype;
2458 } __packed;
2459
2460 struct rtw89_btc_fbtc_slots {
2461 u8 fver; /* btc_ver::fcxslots */
2462 u8 tbl_num;
2463 __le16 rsvd;
2464 __le32 update_map;
2465 struct rtw89_btc_fbtc_slot slot[CXST_MAX];
2466 } __packed;
2467
2468 struct rtw89_btc_fbtc_slot_v7 {
2469 __le16 dur; /* slot duration */
2470 __le16 cxtype;
2471 __le32 cxtbl;
2472 } __packed;
2473
2474 struct rtw89_btc_fbtc_slot_u16 {
2475 __le16 dur; /* slot duration */
2476 __le16 cxtype;
2477 __le16 cxtbl_l16; /* coex table [15:0] */
2478 __le16 cxtbl_h16; /* coex table [31:16] */
2479 } __packed;
2480
2481 struct rtw89_btc_fbtc_1slot_v7 {
2482 u8 fver;
2483 u8 sid; /* slot id */
2484 __le16 rsvd;
2485 struct rtw89_btc_fbtc_slot_v7 slot;
2486 } __packed;
2487
2488 struct rtw89_btc_fbtc_slots_v7 {
2489 u8 fver;
2490 u8 slot_cnt;
2491 u8 rsvd0;
2492 u8 rsvd1;
2493 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX];
2494 __le32 update_map;
2495 } __packed;
2496
2497 union rtw89_btc_fbtc_slots_info {
2498 struct rtw89_btc_fbtc_slots v1;
2499 struct rtw89_btc_fbtc_slots_v7 v7;
2500 } __packed;
2501
2502 struct rtw89_btc_fbtc_step {
2503 u8 type;
2504 u8 val;
2505 __le16 difft;
2506 } __packed;
2507
2508 struct rtw89_btc_fbtc_steps_v2 {
2509 u8 fver; /* btc_ver::fcxstep */
2510 u8 rsvd;
2511 __le16 cnt;
2512 __le16 pos_old;
2513 __le16 pos_new;
2514 struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
2515 } __packed;
2516
2517 struct rtw89_btc_fbtc_steps_v3 {
2518 u8 fver;
2519 u8 en;
2520 __le16 rsvd;
2521 __le32 cnt;
2522 struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
2523 } __packed;
2524
2525 union rtw89_btc_fbtc_steps_info {
2526 struct rtw89_btc_fbtc_steps_v2 v2;
2527 struct rtw89_btc_fbtc_steps_v3 v3;
2528 };
2529
2530 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */
2531 u8 fver; /* btc_ver::fcxcysta */
2532 u8 rsvd;
2533 __le16 cycles; /* total cycle number */
2534 __le16 cycles_a2dp[CXT_FLCTRL_MAX];
2535 __le16 a2dpept; /* a2dp empty cnt */
2536 __le16 a2dpeptto; /* a2dp empty timeout cnt*/
2537 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */
2538 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */
2539 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2540 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */
2541 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */
2542 __le16 tavg_a2dpept; /* avg a2dp empty time */
2543 __le16 tmax_a2dpept; /* max a2dp empty time */
2544 __le16 tavg_lk; /* avg leak-slot time */
2545 __le16 tmax_lk; /* max leak-slot time */
2546 __le32 slot_cnt[CXST_MAX]; /* slot count */
2547 __le32 bcn_cnt[CXBCN_MAX];
2548 __le32 leakrx_cnt; /* the rximr occur at leak slot */
2549 __le32 collision_cnt; /* counter for event/timer occur at same time */
2550 __le32 skip_cnt;
2551 __le32 exception;
2552 __le32 except_cnt;
2553 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX];
2554 } __packed;
2555
2556 struct rtw89_btc_fbtc_fdd_try_info {
2557 __le16 cycles[CXT_FLCTRL_MAX];
2558 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */
2559 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */
2560 } __packed;
2561
2562 struct rtw89_btc_fbtc_cycle_time_info {
2563 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2564 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2565 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2566 } __packed;
2567
2568 struct rtw89_btc_fbtc_cycle_time_info_v5 {
2569 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2570 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2571 } __packed;
2572
2573 struct rtw89_btc_fbtc_a2dp_trx_stat {
2574 u8 empty_cnt;
2575 u8 retry_cnt;
2576 u8 tx_rate;
2577 u8 tx_cnt;
2578 u8 ack_cnt;
2579 u8 nack_cnt;
2580 u8 rsvd1;
2581 u8 rsvd2;
2582 } __packed;
2583
2584 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 {
2585 u8 empty_cnt;
2586 u8 retry_cnt;
2587 u8 tx_rate;
2588 u8 tx_cnt;
2589 u8 ack_cnt;
2590 u8 nack_cnt;
2591 u8 no_empty_cnt;
2592 u8 rsvd;
2593 } __packed;
2594
2595 struct rtw89_btc_fbtc_cycle_a2dp_empty_info {
2596 __le16 cnt; /* a2dp empty cnt */
2597 __le16 cnt_timeout; /* a2dp empty timeout cnt*/
2598 __le16 tavg; /* avg a2dp empty time */
2599 __le16 tmax; /* max a2dp empty time */
2600 } __packed;
2601
2602 struct rtw89_btc_fbtc_cycle_leak_info {
2603 __le32 cnt_rximr; /* the rximr occur at leak slot */
2604 __le16 tavg; /* avg leak-slot time */
2605 __le16 tmax; /* max leak-slot time */
2606 } __packed;
2607
2608 struct rtw89_btc_fbtc_cycle_leak_info_v7 {
2609 __le16 tavg;
2610 __le16 tamx;
2611 __le32 cnt_rximr;
2612 } __packed;
2613
2614 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0)
2615 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10)
2616
2617 struct rtw89_btc_fbtc_cycle_fddt_info {
2618 __le16 train_cycle;
2619 __le16 tp;
2620
2621 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2622 s8 bt_tx_power; /* decrease Tx power (dB) */
2623 s8 bt_rx_gain; /* LNA constrain level */
2624 u8 no_empty_cnt;
2625
2626 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2627 u8 cn; /* condition_num */
2628 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2629 u8 train_result; /* refer to enum btc_fddt_check_map */
2630 } __packed;
2631
2632 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0)
2633 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4)
2634
2635 struct rtw89_btc_fbtc_cycle_fddt_info_v5 {
2636 __le16 train_cycle;
2637 __le16 tp;
2638
2639 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2640 s8 bt_tx_power; /* decrease Tx power (dB) */
2641 s8 bt_rx_gain; /* LNA constrain level */
2642 u8 no_empty_cnt;
2643
2644 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2645 u8 cn; /* condition_num */
2646 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2647 u8 train_result; /* refer to enum btc_fddt_check_map */
2648 } __packed;
2649
2650 struct rtw89_btc_fbtc_fddt_cell_status {
2651 s8 wl_tx_pwr;
2652 s8 bt_tx_pwr;
2653 s8 bt_rx_gain;
2654 u8 state_phase; /* [0:3] train state, [4:7] train phase */
2655 } __packed;
2656
2657 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */
2658 u8 fver;
2659 u8 rsvd;
2660 __le16 cycles; /* total cycle number */
2661 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX];
2662 struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2663 struct rtw89_btc_fbtc_fdd_try_info fdd_try;
2664 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2665 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX];
2666 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2667 __le32 slot_cnt[CXST_MAX]; /* slot count */
2668 __le32 bcn_cnt[CXBCN_MAX];
2669 __le32 collision_cnt; /* counter for event/timer occur at the same time */
2670 __le32 skip_cnt;
2671 __le32 except_cnt;
2672 __le32 except_map;
2673 } __packed;
2674
2675 #define FDD_TRAIN_WL_DIRECTION 2
2676 #define FDD_TRAIN_WL_RSSI_LEVEL 5
2677 #define FDD_TRAIN_BT_RSSI_LEVEL 5
2678
2679 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */
2680 u8 fver;
2681 u8 rsvd;
2682 u8 collision_cnt; /* counter for event/timer occur at the same time */
2683 u8 except_cnt;
2684
2685 __le16 skip_cnt;
2686 __le16 cycles; /* total cycle number */
2687
2688 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2689 __le16 slot_cnt[CXST_MAX]; /* slot count */
2690 __le16 bcn_cnt[CXBCN_MAX];
2691 struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2692 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2693 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2694 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2695 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX];
2696 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION]
2697 [FDD_TRAIN_WL_RSSI_LEVEL]
2698 [FDD_TRAIN_BT_RSSI_LEVEL];
2699 __le32 except_map;
2700 } __packed;
2701
2702 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */
2703 u8 fver;
2704 u8 rsvd;
2705 u8 collision_cnt; /* counter for event/timer occur at the same time */
2706 u8 except_cnt;
2707 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX];
2708
2709 __le16 skip_cnt;
2710 __le16 cycles; /* total cycle number */
2711
2712 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2713 __le16 slot_cnt[CXST_MAX]; /* slot count */
2714 __le16 bcn_cnt[CXBCN_MAX];
2715 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time;
2716 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2717 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2718 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2719 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX];
2720 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION]
2721 [FDD_TRAIN_WL_RSSI_LEVEL]
2722 [FDD_TRAIN_BT_RSSI_LEVEL];
2723 __le32 except_map;
2724 } __packed;
2725
2726 struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */
2727 u8 fver;
2728 u8 rsvd;
2729 u8 collision_cnt; /* counter for event/timer occur at the same time */
2730 u8 except_cnt;
2731
2732 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX];
2733
2734 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2735
2736 __le16 skip_cnt;
2737 __le16 cycles; /* total cycle number */
2738
2739 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2740 __le16 slot_cnt[CXST_MAX]; /* slot count */
2741 __le16 bcn_cnt[CXBCN_MAX];
2742
2743 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time;
2744 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2745 struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot;
2746
2747 __le32 except_map;
2748 } __packed;
2749
2750 union rtw89_btc_fbtc_cysta_info {
2751 struct rtw89_btc_fbtc_cysta_v2 v2;
2752 struct rtw89_btc_fbtc_cysta_v3 v3;
2753 struct rtw89_btc_fbtc_cysta_v4 v4;
2754 struct rtw89_btc_fbtc_cysta_v5 v5;
2755 struct rtw89_btc_fbtc_cysta_v7 v7;
2756 };
2757
2758 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */
2759 u8 fver; /* btc_ver::fcxnullsta */
2760 u8 rsvd;
2761 __le16 rsvd2;
2762 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2763 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2764 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */
2765 } __packed;
2766
2767 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */
2768 u8 fver; /* btc_ver::fcxnullsta */
2769 u8 rsvd;
2770 __le16 rsvd2;
2771 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2772 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2773 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */
2774 } __packed;
2775
2776 struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */
2777 u8 fver;
2778 u8 rsvd0;
2779 u8 rsvd1;
2780 u8 rsvd2;
2781
2782 __le32 tmax[2];
2783 __le32 tavg[2];
2784 __le32 result[2][5];
2785 } __packed;
2786
2787 union rtw89_btc_fbtc_cynullsta_info {
2788 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */
2789 struct rtw89_btc_fbtc_cynullsta_v2 v2;
2790 struct rtw89_btc_fbtc_cynullsta_v7 v7;
2791 };
2792
2793 struct rtw89_btc_fbtc_btver_v1 {
2794 u8 fver; /* btc_ver::fcxbtver */
2795 u8 rsvd;
2796 __le16 rsvd2;
2797 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
2798 __le32 fw_ver;
2799 __le32 feature;
2800 } __packed;
2801
2802 struct rtw89_btc_fbtc_btver_v7 {
2803 u8 fver;
2804 u8 rsvd0;
2805 u8 rsvd1;
2806 u8 rsvd2;
2807
2808 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
2809 __le32 fw_ver;
2810 __le32 feature;
2811 } __packed;
2812
2813 union rtw89_btc_fbtc_btver {
2814 struct rtw89_btc_fbtc_btver_v1 v1;
2815 struct rtw89_btc_fbtc_btver_v7 v7;
2816 } __packed;
2817
2818 struct rtw89_btc_fbtc_btafh {
2819 u8 fver; /* btc_ver::fcxbtafh */
2820 u8 rsvd;
2821 __le16 rsvd2;
2822 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */
2823 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */
2824 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */
2825 } __packed;
2826
2827 struct rtw89_btc_fbtc_btafh_v2 {
2828 u8 fver; /* btc_ver::fcxbtafh */
2829 u8 rsvd;
2830 u8 rsvd2;
2831 u8 map_type;
2832 u8 afh_l[4];
2833 u8 afh_m[4];
2834 u8 afh_h[4];
2835 u8 afh_le_a[4];
2836 u8 afh_le_b[4];
2837 } __packed;
2838
2839 struct rtw89_btc_fbtc_btafh_v7 {
2840 u8 fver;
2841 u8 map_type;
2842 u8 rsvd0;
2843 u8 rsvd1;
2844 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */
2845 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */
2846 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */
2847 u8 afh_le_a[4];
2848 u8 afh_le_b[4];
2849 } __packed;
2850
2851 struct rtw89_btc_fbtc_btdevinfo {
2852 u8 fver; /* btc_ver::fcxbtdevinfo */
2853 u8 rsvd;
2854 __le16 vendor_id;
2855 __le32 dev_name; /* only 24 bits valid */
2856 __le32 flush_time;
2857 } __packed;
2858
2859 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0)
2860 struct rtw89_btc_rf_trx_para {
2861 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2862 u32 wl_rx_gain; /* rx gain table index (TBD.) */
2863 u8 bt_tx_power; /* decrease Tx power (dB) */
2864 u8 bt_rx_gain; /* LNA constrain level */
2865 };
2866
2867 struct rtw89_btc_trx_info {
2868 u8 tx_lvl;
2869 u8 rx_lvl;
2870 u8 wl_rssi;
2871 u8 bt_rssi;
2872
2873 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2874 s8 rx_gain; /* rx gain table index (TBD.) */
2875 s8 bt_tx_power; /* decrease Tx power (dB) */
2876 s8 bt_rx_gain; /* LNA constrain level */
2877
2878 u8 cn; /* condition_num */
2879 s8 nhm;
2880 u8 bt_profile;
2881 u8 rsvd2;
2882
2883 u16 tx_rate;
2884 u16 rx_rate;
2885
2886 u32 tx_tp;
2887 u32 rx_tp;
2888 u32 rx_err_ratio;
2889 };
2890
2891 union rtw89_btc_fbtc_slot_u {
2892 struct rtw89_btc_fbtc_slot v1[CXST_MAX];
2893 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX];
2894 };
2895
2896 struct rtw89_btc_dm {
2897 union rtw89_btc_fbtc_slot_u slot;
2898 union rtw89_btc_fbtc_slot_u slot_now;
2899 struct rtw89_btc_fbtc_tdma tdma;
2900 struct rtw89_btc_fbtc_tdma tdma_now;
2901 struct rtw89_mac_ax_coex_gnt gnt;
2902 union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */
2903 struct rtw89_btc_rf_trx_para rf_trx_para;
2904 struct rtw89_btc_wl_tx_limit_para wl_tx_limit;
2905 struct rtw89_btc_dm_step dm_step;
2906 struct rtw89_btc_wl_scc_ctrl wl_scc;
2907 struct rtw89_btc_trx_info trx_info;
2908 union rtw89_btc_dm_error_map error;
2909 u32 cnt_dm[BTC_DCNT_NUM];
2910 u32 cnt_notify[BTC_NCNT_NUM];
2911
2912 u32 update_slot_map;
2913 u32 set_ant_path;
2914 u32 e2g_slot_limit;
2915 u32 e2g_slot_nulltx_time;
2916
2917 u32 wl_only: 1;
2918 u32 wl_fw_cx_offload: 1;
2919 u32 freerun: 1;
2920 u32 fddt_train: 1;
2921 u32 wl_ps_ctrl: 2;
2922 u32 wl_mimo_ps: 1;
2923 u32 leak_ap: 1;
2924 u32 noisy_level: 3;
2925 u32 coex_info_map: 8;
2926 u32 bt_only: 1;
2927 u32 wl_btg_rx: 2;
2928 u32 trx_para_level: 8;
2929 u32 wl_stb_chg: 1;
2930 u32 pta_owner: 1;
2931
2932 u32 tdma_instant_excute: 1;
2933 u32 wl_btg_rx_rb: 2;
2934
2935 u16 slot_dur[CXST_MAX];
2936 u16 bt_slot_flood;
2937
2938 u8 run_reason;
2939 u8 run_action;
2940
2941 u8 wl_pre_agc: 2;
2942 u8 wl_lna2: 1;
2943 u8 wl_pre_agc_rb: 2;
2944 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */
2945 u8 slot_req_more: 1;
2946 };
2947
2948 struct rtw89_btc_ctrl {
2949 u32 manual: 1;
2950 u32 igno_bt: 1;
2951 u32 always_freerun: 1;
2952 u32 trace_step: 16;
2953 u32 rsvd: 12;
2954 };
2955
2956 struct rtw89_btc_ctrl_v7 {
2957 u8 manual;
2958 u8 igno_bt;
2959 u8 always_freerun;
2960 u8 rsvd;
2961 } __packed;
2962
2963 union rtw89_btc_ctrl_list {
2964 struct rtw89_btc_ctrl ctrl;
2965 struct rtw89_btc_ctrl_v7 ctrl_v7;
2966 };
2967
2968 struct rtw89_btc_dbg {
2969 /* cmd "rb" */
2970 bool rb_done;
2971 u32 rb_val;
2972 };
2973
2974 enum rtw89_btc_btf_fw_event {
2975 BTF_EVNT_RPT = 0,
2976 BTF_EVNT_BT_INFO = 1,
2977 BTF_EVNT_BT_SCBD = 2,
2978 BTF_EVNT_BT_REG = 3,
2979 BTF_EVNT_CX_RUNINFO = 4,
2980 BTF_EVNT_BT_PSD = 5,
2981 BTF_EVNT_BUF_OVERFLOW,
2982 BTF_EVNT_C2H_LOOPBACK,
2983 BTF_EVNT_MAX,
2984 };
2985
2986 enum btf_fw_event_report {
2987 BTC_RPT_TYPE_CTRL = 0x0,
2988 BTC_RPT_TYPE_TDMA,
2989 BTC_RPT_TYPE_SLOT,
2990 BTC_RPT_TYPE_CYSTA,
2991 BTC_RPT_TYPE_STEP,
2992 BTC_RPT_TYPE_NULLSTA,
2993 BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */
2994 BTC_RPT_TYPE_MREG,
2995 BTC_RPT_TYPE_GPIO_DBG,
2996 BTC_RPT_TYPE_BT_VER,
2997 BTC_RPT_TYPE_BT_SCAN,
2998 BTC_RPT_TYPE_BT_AFH,
2999 BTC_RPT_TYPE_BT_DEVICE,
3000 BTC_RPT_TYPE_TEST,
3001 BTC_RPT_TYPE_MAX = 31,
3002
3003 __BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA,
3004 __BTC_RPT_TYPE_V0_MAX = 12,
3005 };
3006
3007 enum rtw_btc_btf_reg_type {
3008 REG_MAC = 0x0,
3009 REG_BB = 0x1,
3010 REG_RF = 0x2,
3011 REG_BT_RF = 0x3,
3012 REG_BT_MODEM = 0x4,
3013 REG_BT_BLUEWIZE = 0x5,
3014 REG_BT_VENDOR = 0x6,
3015 REG_BT_LE = 0x7,
3016 REG_MAX_TYPE,
3017 };
3018
3019 struct rtw89_btc_rpt_cmn_info {
3020 u32 rx_cnt;
3021 u32 rx_len;
3022 u32 req_len; /* expected rsp len */
3023 u8 req_fver; /* expected rsp fver */
3024 u8 rsp_fver; /* fver from fw */
3025 u8 valid;
3026 } __packed;
3027
3028 union rtw89_btc_fbtc_btafh_info {
3029 struct rtw89_btc_fbtc_btafh v1;
3030 struct rtw89_btc_fbtc_btafh_v2 v2;
3031 };
3032
3033 struct rtw89_btc_report_ctrl_state {
3034 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3035 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo;
3036 };
3037
3038 struct rtw89_btc_rpt_fbtc_tdma {
3039 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3040 union rtw89_btc_fbtc_tdma_le32 finfo;
3041 };
3042
3043 struct rtw89_btc_rpt_fbtc_slots {
3044 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3045 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */
3046 };
3047
3048 struct rtw89_btc_rpt_fbtc_cysta {
3049 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3050 union rtw89_btc_fbtc_cysta_info finfo;
3051 };
3052
3053 struct rtw89_btc_rpt_fbtc_step {
3054 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3055 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */
3056 };
3057
3058 struct rtw89_btc_rpt_fbtc_nullsta {
3059 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3060 union rtw89_btc_fbtc_cynullsta_info finfo;
3061 };
3062
3063 struct rtw89_btc_rpt_fbtc_mreg {
3064 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3065 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */
3066 };
3067
3068 struct rtw89_btc_rpt_fbtc_gpio_dbg {
3069 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3070 union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */
3071 };
3072
3073 struct rtw89_btc_rpt_fbtc_btver {
3074 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3075 union rtw89_btc_fbtc_btver finfo; /* info from fw */
3076 };
3077
3078 struct rtw89_btc_rpt_fbtc_btscan {
3079 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3080 union rtw89_btc_fbtc_btscan finfo; /* info from fw */
3081 };
3082
3083 struct rtw89_btc_rpt_fbtc_btafh {
3084 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3085 union rtw89_btc_fbtc_btafh_info finfo;
3086 };
3087
3088 struct rtw89_btc_rpt_fbtc_btdev {
3089 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3090 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */
3091 };
3092
3093 enum rtw89_btc_btfre_type {
3094 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */
3095 BTFRE_UNDEF_TYPE,
3096 BTFRE_EXCEPTION,
3097 BTFRE_MAX,
3098 };
3099
3100 struct rtw89_btc_btf_fwinfo {
3101 u32 cnt_c2h;
3102 u32 cnt_h2c;
3103 u32 cnt_h2c_fail;
3104 u32 event[BTF_EVNT_MAX];
3105
3106 u32 err[BTFRE_MAX];
3107 u32 len_mismch;
3108 u32 fver_mismch;
3109 u32 rpt_en_map;
3110
3111 struct rtw89_btc_report_ctrl_state rpt_ctrl;
3112 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma;
3113 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots;
3114 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta;
3115 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step;
3116 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta;
3117 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval;
3118 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg;
3119 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver;
3120 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan;
3121 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh;
3122 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev;
3123 };
3124
3125 struct rtw89_btc_ver {
3126 enum rtw89_core_chip_id chip_id;
3127 u32 fw_ver_code;
3128
3129 u8 fcxbtcrpt;
3130 u8 fcxtdma;
3131 u8 fcxslots;
3132 u8 fcxcysta;
3133 u8 fcxstep;
3134 u8 fcxnullsta;
3135 u8 fcxmreg;
3136 u8 fcxgpiodbg;
3137 u8 fcxbtver;
3138 u8 fcxbtscan;
3139 u8 fcxbtafh;
3140 u8 fcxbtdevinfo;
3141 u8 fwlrole;
3142 u8 frptmap;
3143 u8 fcxctrl;
3144 u8 fcxinit;
3145
3146 u8 fwevntrptl;
3147 u8 drvinfo_type;
3148 u16 info_buf;
3149 u8 max_role_num;
3150 };
3151
3152 #define RTW89_BTC_POLICY_MAXLEN 512
3153
3154 struct rtw89_btc {
3155 const struct rtw89_btc_ver *ver;
3156
3157 struct rtw89_btc_cx cx;
3158 struct rtw89_btc_dm dm;
3159 union rtw89_btc_ctrl_list ctrl;
3160 union rtw89_btc_module_info mdinfo;
3161 struct rtw89_btc_btf_fwinfo fwinfo;
3162 struct rtw89_btc_dbg dbg;
3163
3164 struct work_struct eapol_notify_work;
3165 struct work_struct arp_notify_work;
3166 struct work_struct dhcp_notify_work;
3167 struct work_struct icmp_notify_work;
3168
3169 u32 bt_req_len;
3170
3171 u8 policy[RTW89_BTC_POLICY_MAXLEN];
3172 u8 ant_type;
3173 u8 btg_pos;
3174 u16 policy_len;
3175 u16 policy_type;
3176 u32 hubmsg_cnt;
3177 bool bt_req_en;
3178 bool update_policy_force;
3179 bool lps;
3180 bool manual_ctrl;
3181 };
3182
3183 enum rtw89_btc_hmsg {
3184 RTW89_BTC_HMSG_TMR_EN = 0x0,
3185 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1,
3186 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2,
3187 RTW89_BTC_HMSG_FW_EV = 0x3,
3188 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4,
3189 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5,
3190
3191 NUM_OF_RTW89_BTC_HMSG,
3192 };
3193
3194 enum rtw89_ra_mode {
3195 RTW89_RA_MODE_CCK = BIT(0),
3196 RTW89_RA_MODE_OFDM = BIT(1),
3197 RTW89_RA_MODE_HT = BIT(2),
3198 RTW89_RA_MODE_VHT = BIT(3),
3199 RTW89_RA_MODE_HE = BIT(4),
3200 RTW89_RA_MODE_EHT = BIT(5),
3201 };
3202
3203 enum rtw89_ra_report_mode {
3204 RTW89_RA_RPT_MODE_LEGACY,
3205 RTW89_RA_RPT_MODE_HT,
3206 RTW89_RA_RPT_MODE_VHT,
3207 RTW89_RA_RPT_MODE_HE,
3208 RTW89_RA_RPT_MODE_EHT,
3209 };
3210
3211 enum rtw89_dig_noisy_level {
3212 RTW89_DIG_NOISY_LEVEL0 = -1,
3213 RTW89_DIG_NOISY_LEVEL1 = 0,
3214 RTW89_DIG_NOISY_LEVEL2 = 1,
3215 RTW89_DIG_NOISY_LEVEL3 = 2,
3216 RTW89_DIG_NOISY_LEVEL_MAX = 3,
3217 };
3218
3219 enum rtw89_gi_ltf {
3220 RTW89_GILTF_LGI_4XHE32 = 0,
3221 RTW89_GILTF_SGI_4XHE08 = 1,
3222 RTW89_GILTF_2XHE16 = 2,
3223 RTW89_GILTF_2XHE08 = 3,
3224 RTW89_GILTF_1XHE16 = 4,
3225 RTW89_GILTF_1XHE08 = 5,
3226 RTW89_GILTF_MAX
3227 };
3228
3229 enum rtw89_rx_frame_type {
3230 RTW89_RX_TYPE_MGNT = 0,
3231 RTW89_RX_TYPE_CTRL = 1,
3232 RTW89_RX_TYPE_DATA = 2,
3233 RTW89_RX_TYPE_RSVD = 3,
3234 };
3235
3236 enum rtw89_efuse_block {
3237 RTW89_EFUSE_BLOCK_SYS = 0,
3238 RTW89_EFUSE_BLOCK_RF = 1,
3239 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2,
3240 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3,
3241 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4,
3242 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5,
3243 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6,
3244 RTW89_EFUSE_BLOCK_ADIE = 7,
3245
3246 RTW89_EFUSE_BLOCK_NUM,
3247 RTW89_EFUSE_BLOCK_IGNORE,
3248 };
3249
3250 struct rtw89_ra_info {
3251 u8 is_dis_ra:1;
3252 /* Bit0 : CCK
3253 * Bit1 : OFDM
3254 * Bit2 : HT
3255 * Bit3 : VHT
3256 * Bit4 : HE
3257 * Bit5 : EHT
3258 */
3259 u8 mode_ctrl:6;
3260 u8 bw_cap:3; /* enum rtw89_bandwidth */
3261 u8 macid;
3262 u8 dcm_cap:1;
3263 u8 er_cap:1;
3264 u8 init_rate_lv:2;
3265 u8 upd_all:1;
3266 u8 en_sgi:1;
3267 u8 ldpc_cap:1;
3268 u8 stbc_cap:1;
3269 u8 ss_num:3;
3270 u8 giltf:3;
3271 u8 upd_bw_nss_mask:1;
3272 u8 upd_mask:1;
3273 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */
3274 /* BFee CSI */
3275 u8 band_num;
3276 u8 ra_csi_rate_en:1;
3277 u8 fixed_csi_rate_en:1;
3278 u8 cr_tbl_sel:1;
3279 u8 fix_giltf_en:1;
3280 u8 fix_giltf:3;
3281 u8 rsvd2:1;
3282 u8 csi_mcs_ss_idx;
3283 u8 csi_mode:2;
3284 u8 csi_gi_ltf:3;
3285 u8 csi_bw:3;
3286 };
3287
3288 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4
3289 #define RTW89_PPDU_MAC_INFO_SIZE 8
3290 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96
3291 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128
3292
3293 #define RTW89_MAX_RX_AGG_NUM 64
3294 #define RTW89_MAX_TX_AGG_NUM 128
3295
3296 struct rtw89_ampdu_params {
3297 u16 agg_num;
3298 bool amsdu;
3299 };
3300
3301 struct rtw89_ra_report {
3302 struct rate_info txrate;
3303 u32 bit_rate;
3304 u16 hw_rate;
3305 bool might_fallback_legacy;
3306 };
3307
3308 DECLARE_EWMA(rssi, 10, 16);
3309 DECLARE_EWMA(evm, 10, 16);
3310 DECLARE_EWMA(snr, 10, 16);
3311
3312 struct rtw89_ba_cam_entry {
3313 struct list_head list;
3314 u8 tid;
3315 };
3316
3317 #define RTW89_MAX_ADDR_CAM_NUM 128
3318 #define RTW89_MAX_BSSID_CAM_NUM 20
3319 #define RTW89_MAX_SEC_CAM_NUM 128
3320 #define RTW89_MAX_BA_CAM_NUM 24
3321 #define RTW89_SEC_CAM_IN_ADDR_CAM 7
3322
3323 struct rtw89_addr_cam_entry {
3324 u8 addr_cam_idx;
3325 u8 offset;
3326 u8 len;
3327 u8 valid : 1;
3328 u8 addr_mask : 6;
3329 u8 wapi : 1;
3330 u8 mask_sel : 2;
3331 u8 bssid_cam_idx: 6;
3332
3333 u8 sec_ent_mode;
3334 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM);
3335 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM];
3336 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM];
3337 };
3338
3339 struct rtw89_bssid_cam_entry {
3340 u8 bssid[ETH_ALEN];
3341 u8 phy_idx;
3342 u8 bssid_cam_idx;
3343 u8 offset;
3344 u8 len;
3345 u8 valid : 1;
3346 u8 num;
3347 };
3348
3349 struct rtw89_sec_cam_entry {
3350 u8 sec_cam_idx;
3351 u8 offset;
3352 u8 len;
3353 u8 type : 4;
3354 u8 ext_key : 1;
3355 u8 spp_mode : 1;
3356 /* 256 bits */
3357 u8 key[32];
3358 };
3359
3360 struct rtw89_sta_link {
3361 struct rtw89_sta *rtwsta;
3362 unsigned int link_id;
3363
3364 u8 mac_id;
3365 bool er_cap;
3366 struct rtw89_vif_link *rtwvif_link;
3367 struct rtw89_ra_info ra;
3368 struct rtw89_ra_report ra_report;
3369 int max_agg_wait;
3370 u8 prev_rssi;
3371 struct ewma_rssi avg_rssi;
3372 struct ewma_rssi rssi[RF_PATH_MAX];
3373 struct ewma_snr avg_snr;
3374 struct ewma_evm evm_1ss;
3375 struct ewma_evm evm_min[RF_PATH_MAX];
3376 struct ewma_evm evm_max[RF_PATH_MAX];
3377 struct ieee80211_rx_status rx_status;
3378 u16 rx_hw_rate;
3379 __le32 htc_template;
3380 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */
3381 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */
3382 struct list_head ba_cam_list;
3383
3384 bool use_cfg_mask;
3385 struct cfg80211_bitrate_mask mask;
3386
3387 bool cctl_tx_time;
3388 u32 ampdu_max_time:4;
3389 bool cctl_tx_retry_limit;
3390 u32 data_tx_cnt_lmt:6;
3391 };
3392
3393 struct rtw89_efuse {
3394 bool valid;
3395 bool power_k_valid;
3396 u8 xtal_cap;
3397 u8 addr[ETH_ALEN];
3398 u8 rfe_type;
3399 char country_code[2];
3400 };
3401
3402 struct rtw89_phy_rate_pattern {
3403 u64 ra_mask;
3404 u16 rate;
3405 u8 ra_mode;
3406 bool enable;
3407 };
3408
3409 #define RTW89_TX_WAIT_WORK_TIMEOUT msecs_to_jiffies(500)
3410 struct rtw89_tx_wait_info {
3411 struct rcu_head rcu_head;
3412 struct list_head list;
3413 struct completion completion;
3414 struct sk_buff *skb;
3415 bool tx_done;
3416 };
3417
3418 struct rtw89_tx_skb_data {
3419 struct rtw89_tx_wait_info __rcu *wait;
3420 u8 hci_priv[];
3421 };
3422
3423 #define RTW89_ROC_IDLE_TIMEOUT 500
3424 #define RTW89_ROC_TX_TIMEOUT 30
3425 enum rtw89_roc_state {
3426 RTW89_ROC_IDLE,
3427 RTW89_ROC_NORMAL,
3428 RTW89_ROC_MGMT,
3429 };
3430
3431 #define RTW89_ROC_BY_LINK_INDEX 0
3432
3433 struct rtw89_roc {
3434 struct ieee80211_channel chan;
3435 struct delayed_work roc_work;
3436 enum ieee80211_roc_type type;
3437 enum rtw89_roc_state state;
3438 int duration;
3439 };
3440
3441 #define RTW89_P2P_MAX_NOA_NUM 2
3442
3443 struct rtw89_p2p_ie_head {
3444 u8 eid;
3445 u8 ie_len;
3446 u8 oui[3];
3447 u8 oui_type;
3448 } __packed;
3449
3450 struct rtw89_noa_attr_head {
3451 u8 attr_type;
3452 __le16 attr_len;
3453 u8 index;
3454 u8 oppps_ctwindow;
3455 } __packed;
3456
3457 struct rtw89_p2p_noa_ie {
3458 struct rtw89_p2p_ie_head p2p_head;
3459 struct rtw89_noa_attr_head noa_head;
3460 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM];
3461 } __packed;
3462
3463 struct rtw89_p2p_noa_setter {
3464 struct rtw89_p2p_noa_ie ie;
3465 u8 noa_count;
3466 u8 noa_index;
3467 };
3468
3469 struct rtw89_vif_link {
3470 struct rtw89_vif *rtwvif;
3471 unsigned int link_id;
3472
3473 bool chanctx_assigned; /* only valid when running with chanctx_ops */
3474 enum rtw89_chanctx_idx chanctx_idx;
3475 enum rtw89_reg_6ghz_power reg_6ghz_power;
3476 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe;
3477
3478 u8 mac_id;
3479 u8 port;
3480 u8 mac_addr[ETH_ALEN];
3481 u8 bssid[ETH_ALEN];
3482 u8 phy_idx;
3483 u8 mac_idx;
3484 u8 net_type;
3485 u8 wifi_role;
3486 u8 self_role;
3487 u8 wmm;
3488 u8 bcn_hit_cond;
3489 u8 hit_rule;
3490 u8 last_noa_nr;
3491 u64 sync_bcn_tsf;
3492 bool trigger;
3493 bool lsig_txop;
3494 u8 tgt_ind;
3495 u8 frm_tgt_ind;
3496 bool wowlan_pattern;
3497 bool wowlan_uc;
3498 bool wowlan_magic;
3499 bool is_hesta;
3500 bool last_a_ctrl;
3501 bool dyn_tb_bedge_en;
3502 bool pre_pwr_diff_en;
3503 bool pwr_diff_en;
3504 u8 def_tri_idx;
3505 struct work_struct update_beacon_work;
3506 struct rtw89_addr_cam_entry addr_cam;
3507 struct rtw89_bssid_cam_entry bssid_cam;
3508 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
3509 struct rtw89_phy_rate_pattern rate_pattern;
3510 struct list_head general_pkt_list;
3511 struct rtw89_p2p_noa_setter p2p_noa;
3512 };
3513
3514 enum rtw89_lv1_rcvy_step {
3515 RTW89_LV1_RCVY_STEP_1,
3516 RTW89_LV1_RCVY_STEP_2,
3517 };
3518
3519 struct rtw89_hci_ops {
3520 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req);
3521 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch);
3522 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop);
3523 void (*reset)(struct rtw89_dev *rtwdev);
3524 int (*start)(struct rtw89_dev *rtwdev);
3525 void (*stop)(struct rtw89_dev *rtwdev);
3526 void (*pause)(struct rtw89_dev *rtwdev, bool pause);
3527 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power);
3528 void (*recalc_int_mit)(struct rtw89_dev *rtwdev);
3529
3530 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr);
3531 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr);
3532 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr);
3533 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data);
3534 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data);
3535 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data);
3536
3537 int (*mac_pre_init)(struct rtw89_dev *rtwdev);
3538 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev);
3539 int (*mac_post_init)(struct rtw89_dev *rtwdev);
3540 int (*deinit)(struct rtw89_dev *rtwdev);
3541
3542 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch);
3543 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step);
3544 void (*dump_err_status)(struct rtw89_dev *rtwdev);
3545 int (*napi_poll)(struct napi_struct *napi, int budget);
3546
3547 /* Deal with locks inside recovery_start and recovery_complete callbacks
3548 * by hci instance, and handle things which need to consider under SER.
3549 * e.g. turn on/off interrupts except for the one for halt notification.
3550 */
3551 void (*recovery_start)(struct rtw89_dev *rtwdev);
3552 void (*recovery_complete)(struct rtw89_dev *rtwdev);
3553
3554 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable);
3555 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable);
3556 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable);
3557 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev);
3558 void (*clr_idx_all)(struct rtw89_dev *rtwdev);
3559 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev);
3560 void (*disable_intr)(struct rtw89_dev *rtwdev);
3561 void (*enable_intr)(struct rtw89_dev *rtwdev);
3562 int (*rst_bdram)(struct rtw89_dev *rtwdev);
3563 };
3564
3565 struct rtw89_hci_info {
3566 const struct rtw89_hci_ops *ops;
3567 enum rtw89_hci_type type;
3568 u32 rpwm_addr;
3569 u32 cpwm_addr;
3570 bool paused;
3571 };
3572
3573 struct rtw89_chip_ops {
3574 int (*enable_bb_rf)(struct rtw89_dev *rtwdev);
3575 int (*disable_bb_rf)(struct rtw89_dev *rtwdev);
3576 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3577 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3578 void (*bb_reset)(struct rtw89_dev *rtwdev,
3579 enum rtw89_phy_idx phy_idx);
3580 void (*bb_sethw)(struct rtw89_dev *rtwdev);
3581 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3582 u32 addr, u32 mask);
3583 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3584 u32 addr, u32 mask, u32 data);
3585 void (*set_channel)(struct rtw89_dev *rtwdev,
3586 const struct rtw89_chan *chan,
3587 enum rtw89_mac_idx mac_idx,
3588 enum rtw89_phy_idx phy_idx);
3589 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter,
3590 struct rtw89_channel_help_params *p,
3591 const struct rtw89_chan *chan,
3592 enum rtw89_mac_idx mac_idx,
3593 enum rtw89_phy_idx phy_idx);
3594 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map,
3595 enum rtw89_efuse_block block);
3596 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map);
3597 void (*fem_setup)(struct rtw89_dev *rtwdev);
3598 void (*rfe_gpio)(struct rtw89_dev *rtwdev);
3599 void (*rfk_hw_init)(struct rtw89_dev *rtwdev);
3600 void (*rfk_init)(struct rtw89_dev *rtwdev);
3601 void (*rfk_init_late)(struct rtw89_dev *rtwdev);
3602 void (*rfk_channel)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
3603 void (*rfk_band_changed)(struct rtw89_dev *rtwdev,
3604 enum rtw89_phy_idx phy_idx,
3605 const struct rtw89_chan *chan);
3606 void (*rfk_scan)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
3607 bool start);
3608 void (*rfk_track)(struct rtw89_dev *rtwdev);
3609 void (*power_trim)(struct rtw89_dev *rtwdev);
3610 void (*set_txpwr)(struct rtw89_dev *rtwdev,
3611 const struct rtw89_chan *chan,
3612 enum rtw89_phy_idx phy_idx);
3613 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev,
3614 enum rtw89_phy_idx phy_idx);
3615 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3616 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path);
3617 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en,
3618 enum rtw89_phy_idx phy_idx);
3619 void (*query_ppdu)(struct rtw89_dev *rtwdev,
3620 struct rtw89_rx_phy_ppdu *phy_ppdu,
3621 struct ieee80211_rx_status *status);
3622 void (*convert_rpl_to_rssi)(struct rtw89_dev *rtwdev,
3623 struct rtw89_rx_phy_ppdu *phy_ppdu);
3624 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en,
3625 enum rtw89_phy_idx phy_idx);
3626 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev);
3627 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev,
3628 s8 pw_ofst, enum rtw89_mac_idx mac_idx);
3629 void (*digital_pwr_comp)(struct rtw89_dev *rtwdev,
3630 enum rtw89_phy_idx phy_idx);
3631 int (*pwr_on_func)(struct rtw89_dev *rtwdev);
3632 int (*pwr_off_func)(struct rtw89_dev *rtwdev);
3633 void (*query_rxdesc)(struct rtw89_dev *rtwdev,
3634 struct rtw89_rx_desc_info *desc_info,
3635 u8 *data, u32 data_offset);
3636 void (*fill_txdesc)(struct rtw89_dev *rtwdev,
3637 struct rtw89_tx_desc_info *desc_info,
3638 void *txdesc);
3639 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev,
3640 struct rtw89_tx_desc_info *desc_info,
3641 void *txdesc);
3642 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl);
3643 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev,
3644 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
3645 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx,
3646 u32 *tx_en, enum rtw89_sch_tx_sel sel);
3647 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
3648 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev,
3649 struct rtw89_vif_link *rtwvif_link,
3650 struct rtw89_sta_link *rtwsta_link);
3651 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev,
3652 struct rtw89_vif_link *rtwvif_link,
3653 struct rtw89_sta_link *rtwsta_link);
3654 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev,
3655 struct rtw89_vif_link *rtwvif_link,
3656 struct rtw89_sta_link *rtwsta_link);
3657 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev,
3658 struct rtw89_vif_link *rtwvif_link,
3659 struct rtw89_sta_link *rtwsta_link);
3660 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev,
3661 struct rtw89_vif_link *rtwvif_link,
3662 struct rtw89_sta_link *rtwsta_link);
3663 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev,
3664 struct rtw89_vif_link *rtwvif_link);
3665 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev,
3666 struct rtw89_vif_link *rtwvif_link,
3667 struct rtw89_sta_link *rtwsta_link,
3668 bool valid, struct ieee80211_ampdu_params *params);
3669
3670 void (*btc_set_rfe)(struct rtw89_dev *rtwdev);
3671 void (*btc_init_cfg)(struct rtw89_dev *rtwdev);
3672 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state);
3673 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val);
3674 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val);
3675 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev);
3676 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state);
3677 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type);
3678 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level);
3679 };
3680
3681 enum rtw89_dma_ch {
3682 RTW89_DMA_ACH0 = 0,
3683 RTW89_DMA_ACH1 = 1,
3684 RTW89_DMA_ACH2 = 2,
3685 RTW89_DMA_ACH3 = 3,
3686 RTW89_DMA_ACH4 = 4,
3687 RTW89_DMA_ACH5 = 5,
3688 RTW89_DMA_ACH6 = 6,
3689 RTW89_DMA_ACH7 = 7,
3690 RTW89_DMA_B0MG = 8,
3691 RTW89_DMA_B0HI = 9,
3692 RTW89_DMA_B1MG = 10,
3693 RTW89_DMA_B1HI = 11,
3694 RTW89_DMA_H2C = 12,
3695 RTW89_DMA_CH_NUM = 13
3696 };
3697
3698 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0))
3699
3700 enum rtw89_mlo_dbcc_mode {
3701 MLO_DBCC_NOT_SUPPORT = 1,
3702 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1),
3703 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2),
3704 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1),
3705 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2),
3706 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1),
3707 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2),
3708 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2),
3709 DBCC_LEGACY = 0xffffffff,
3710 };
3711
3712 enum rtw89_scan_be_operation {
3713 RTW89_SCAN_OP_STOP,
3714 RTW89_SCAN_OP_START,
3715 RTW89_SCAN_OP_SETPARM,
3716 RTW89_SCAN_OP_GETRPT,
3717 RTW89_SCAN_OP_NUM
3718 };
3719
3720 enum rtw89_scan_be_mode {
3721 RTW89_SCAN_MODE_SA,
3722 RTW89_SCAN_MODE_MACC,
3723 RTW89_SCAN_MODE_NUM
3724 };
3725
3726 enum rtw89_scan_be_opmode {
3727 RTW89_SCAN_OPMODE_NONE,
3728 RTW89_SCAN_OPMODE_TBTT,
3729 RTW89_SCAN_OPMODE_INTV,
3730 RTW89_SCAN_OPMODE_CNT,
3731 RTW89_SCAN_OPMODE_NUM,
3732 };
3733
3734 struct rtw89_scan_option {
3735 bool enable;
3736 bool target_ch_mode;
3737 u8 num_macc_role;
3738 u8 num_opch;
3739 u8 repeat;
3740 u16 norm_pd;
3741 u16 slow_pd;
3742 u16 norm_cy;
3743 u8 opch_end;
3744 u16 delay;
3745 u64 prohib_chan;
3746 enum rtw89_phy_idx band;
3747 enum rtw89_scan_be_operation operation;
3748 enum rtw89_scan_be_mode scan_mode;
3749 enum rtw89_mlo_dbcc_mode mlo_mode;
3750 };
3751
3752 enum rtw89_qta_mode {
3753 RTW89_QTA_SCC,
3754 RTW89_QTA_DBCC,
3755 RTW89_QTA_DLFW,
3756 RTW89_QTA_WOW,
3757
3758 /* keep last */
3759 RTW89_QTA_INVALID,
3760 };
3761
3762 struct rtw89_hfc_ch_cfg {
3763 u16 min;
3764 u16 max;
3765 #define grp_0 0
3766 #define grp_1 1
3767 #define grp_num 2
3768 u8 grp;
3769 };
3770
3771 struct rtw89_hfc_ch_info {
3772 u16 aval;
3773 u16 used;
3774 };
3775
3776 struct rtw89_hfc_pub_cfg {
3777 u16 grp0;
3778 u16 grp1;
3779 u16 pub_max;
3780 u16 wp_thrd;
3781 };
3782
3783 struct rtw89_hfc_pub_info {
3784 u16 g0_used;
3785 u16 g1_used;
3786 u16 g0_aval;
3787 u16 g1_aval;
3788 u16 pub_aval;
3789 u16 wp_aval;
3790 };
3791
3792 struct rtw89_hfc_prec_cfg {
3793 u16 ch011_prec;
3794 u16 h2c_prec;
3795 u16 wp_ch07_prec;
3796 u16 wp_ch811_prec;
3797 u8 ch011_full_cond;
3798 u8 h2c_full_cond;
3799 u8 wp_ch07_full_cond;
3800 u8 wp_ch811_full_cond;
3801 };
3802
3803 struct rtw89_hfc_param {
3804 bool en;
3805 bool h2c_en;
3806 u8 mode;
3807 const struct rtw89_hfc_ch_cfg *ch_cfg;
3808 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM];
3809 struct rtw89_hfc_pub_cfg pub_cfg;
3810 struct rtw89_hfc_pub_info pub_info;
3811 struct rtw89_hfc_prec_cfg prec_cfg;
3812 };
3813
3814 struct rtw89_hfc_param_ini {
3815 const struct rtw89_hfc_ch_cfg *ch_cfg;
3816 const struct rtw89_hfc_pub_cfg *pub_cfg;
3817 const struct rtw89_hfc_prec_cfg *prec_cfg;
3818 u8 mode;
3819 };
3820
3821 struct rtw89_dle_size {
3822 u16 pge_size;
3823 u16 lnk_pge_num;
3824 u16 unlnk_pge_num;
3825 /* for WiFi 7 chips below */
3826 u32 srt_ofst;
3827 };
3828
3829 struct rtw89_wde_quota {
3830 u16 hif;
3831 u16 wcpu;
3832 u16 pkt_in;
3833 u16 cpu_io;
3834 };
3835
3836 struct rtw89_ple_quota {
3837 u16 cma0_tx;
3838 u16 cma1_tx;
3839 u16 c2h;
3840 u16 h2c;
3841 u16 wcpu;
3842 u16 mpdu_proc;
3843 u16 cma0_dma;
3844 u16 cma1_dma;
3845 u16 bb_rpt;
3846 u16 wd_rel;
3847 u16 cpu_io;
3848 u16 tx_rpt;
3849 /* for WiFi 7 chips below */
3850 u16 h2d;
3851 };
3852
3853 struct rtw89_rsvd_quota {
3854 u16 mpdu_info_tbl;
3855 u16 b0_csi;
3856 u16 b1_csi;
3857 u16 b0_lmr;
3858 u16 b1_lmr;
3859 u16 b0_ftm;
3860 u16 b1_ftm;
3861 u16 b0_smr;
3862 u16 b1_smr;
3863 u16 others;
3864 };
3865
3866 struct rtw89_dle_rsvd_size {
3867 u32 srt_ofst;
3868 u32 size;
3869 };
3870
3871 struct rtw89_dle_mem {
3872 enum rtw89_qta_mode mode;
3873 const struct rtw89_dle_size *wde_size;
3874 const struct rtw89_dle_size *ple_size;
3875 const struct rtw89_wde_quota *wde_min_qt;
3876 const struct rtw89_wde_quota *wde_max_qt;
3877 const struct rtw89_ple_quota *ple_min_qt;
3878 const struct rtw89_ple_quota *ple_max_qt;
3879 /* for WiFi 7 chips below */
3880 const struct rtw89_rsvd_quota *rsvd_qt;
3881 const struct rtw89_dle_rsvd_size *rsvd0_size;
3882 const struct rtw89_dle_rsvd_size *rsvd1_size;
3883 };
3884
3885 struct rtw89_reg_def {
3886 u32 addr;
3887 u32 mask;
3888 };
3889
3890 struct rtw89_reg2_def {
3891 u32 addr;
3892 u32 data;
3893 };
3894
3895 struct rtw89_reg3_def {
3896 u32 addr;
3897 u32 mask;
3898 u32 data;
3899 };
3900
3901 struct rtw89_reg5_def {
3902 u8 flag; /* recognized by parsers */
3903 u8 path;
3904 u32 addr;
3905 u32 mask;
3906 u32 data;
3907 };
3908
3909 struct rtw89_reg_imr {
3910 u32 addr;
3911 u32 clr;
3912 u32 set;
3913 };
3914
3915 struct rtw89_phy_table {
3916 const struct rtw89_reg2_def *regs;
3917 u32 n_regs;
3918 enum rtw89_rf_path rf_path;
3919 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
3920 enum rtw89_rf_path rf_path, void *data);
3921 };
3922
3923 struct rtw89_txpwr_table {
3924 const void *data;
3925 u32 size;
3926 void (*load)(struct rtw89_dev *rtwdev,
3927 const struct rtw89_txpwr_table *tbl);
3928 };
3929
3930 struct rtw89_txpwr_rule_2ghz {
3931 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
3932 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3933 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
3934 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3935 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
3936 };
3937
3938 struct rtw89_txpwr_rule_5ghz {
3939 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
3940 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3941 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
3942 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3943 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
3944 };
3945
3946 struct rtw89_txpwr_rule_6ghz {
3947 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
3948 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3949 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
3950 [RTW89_6G_CH_NUM];
3951 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3952 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
3953 [RTW89_6G_CH_NUM];
3954 };
3955
3956 struct rtw89_tx_shape {
3957 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM];
3958 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM];
3959 };
3960
3961 struct rtw89_rfe_parms {
3962 const struct rtw89_txpwr_table *byr_tbl;
3963 struct rtw89_txpwr_rule_2ghz rule_2ghz;
3964 struct rtw89_txpwr_rule_5ghz rule_5ghz;
3965 struct rtw89_txpwr_rule_6ghz rule_6ghz;
3966 struct rtw89_tx_shape tx_shape;
3967 };
3968
3969 struct rtw89_rfe_parms_conf {
3970 const struct rtw89_rfe_parms *rfe_parms;
3971 u8 rfe_type;
3972 };
3973
3974 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0
3975
3976 struct rtw89_txpwr_conf {
3977 u8 rfe_type;
3978 u8 ent_sz;
3979 u32 num_ents;
3980 const void *data;
3981 };
3982
rtw89_txpwr_entcpy(void * entry,const void * cursor,u8 size,const struct rtw89_txpwr_conf * conf)3983 static inline bool rtw89_txpwr_entcpy(void *entry, const void *cursor, u8 size,
3984 const struct rtw89_txpwr_conf *conf)
3985 {
3986 u8 valid_size = min(size, conf->ent_sz);
3987
3988 memcpy(entry, cursor, valid_size);
3989 return true;
3990 }
3991
3992 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data)
3993
3994 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \
3995 for (typecheck(const void *, cursor), (cursor) = (conf)->data; \
3996 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \
3997 (cursor) += (conf)->ent_sz) \
3998 if (rtw89_txpwr_entcpy(&(entry), cursor, sizeof(entry), conf))
3999
4000 struct rtw89_txpwr_byrate_data {
4001 struct rtw89_txpwr_conf conf;
4002 struct rtw89_txpwr_table tbl;
4003 };
4004
4005 struct rtw89_txpwr_lmt_2ghz_data {
4006 struct rtw89_txpwr_conf conf;
4007 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
4008 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4009 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
4010 };
4011
4012 struct rtw89_txpwr_lmt_5ghz_data {
4013 struct rtw89_txpwr_conf conf;
4014 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
4015 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4016 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
4017 };
4018
4019 struct rtw89_txpwr_lmt_6ghz_data {
4020 struct rtw89_txpwr_conf conf;
4021 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
4022 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4023 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
4024 [RTW89_6G_CH_NUM];
4025 };
4026
4027 struct rtw89_txpwr_lmt_ru_2ghz_data {
4028 struct rtw89_txpwr_conf conf;
4029 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
4030 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
4031 };
4032
4033 struct rtw89_txpwr_lmt_ru_5ghz_data {
4034 struct rtw89_txpwr_conf conf;
4035 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
4036 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
4037 };
4038
4039 struct rtw89_txpwr_lmt_ru_6ghz_data {
4040 struct rtw89_txpwr_conf conf;
4041 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
4042 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
4043 [RTW89_6G_CH_NUM];
4044 };
4045
4046 struct rtw89_tx_shape_lmt_data {
4047 struct rtw89_txpwr_conf conf;
4048 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM];
4049 };
4050
4051 struct rtw89_tx_shape_lmt_ru_data {
4052 struct rtw89_txpwr_conf conf;
4053 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM];
4054 };
4055
4056 struct rtw89_rfe_data {
4057 struct rtw89_txpwr_byrate_data byrate;
4058 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz;
4059 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz;
4060 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz;
4061 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz;
4062 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz;
4063 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz;
4064 struct rtw89_tx_shape_lmt_data tx_shape_lmt;
4065 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru;
4066 struct rtw89_rfe_parms rfe_parms;
4067 };
4068
4069 struct rtw89_page_regs {
4070 u32 hci_fc_ctrl;
4071 u32 ch_page_ctrl;
4072 u32 ach_page_ctrl;
4073 u32 ach_page_info;
4074 u32 pub_page_info3;
4075 u32 pub_page_ctrl1;
4076 u32 pub_page_ctrl2;
4077 u32 pub_page_info1;
4078 u32 pub_page_info2;
4079 u32 wp_page_ctrl1;
4080 u32 wp_page_ctrl2;
4081 u32 wp_page_info1;
4082 };
4083
4084 struct rtw89_imr_info {
4085 u32 wdrls_imr_set;
4086 u32 wsec_imr_reg;
4087 u32 wsec_imr_set;
4088 u32 mpdu_tx_imr_set;
4089 u32 mpdu_rx_imr_set;
4090 u32 sta_sch_imr_set;
4091 u32 txpktctl_imr_b0_reg;
4092 u32 txpktctl_imr_b0_clr;
4093 u32 txpktctl_imr_b0_set;
4094 u32 txpktctl_imr_b1_reg;
4095 u32 txpktctl_imr_b1_clr;
4096 u32 txpktctl_imr_b1_set;
4097 u32 wde_imr_clr;
4098 u32 wde_imr_set;
4099 u32 ple_imr_clr;
4100 u32 ple_imr_set;
4101 u32 host_disp_imr_clr;
4102 u32 host_disp_imr_set;
4103 u32 cpu_disp_imr_clr;
4104 u32 cpu_disp_imr_set;
4105 u32 other_disp_imr_clr;
4106 u32 other_disp_imr_set;
4107 u32 bbrpt_com_err_imr_reg;
4108 u32 bbrpt_chinfo_err_imr_reg;
4109 u32 bbrpt_err_imr_set;
4110 u32 bbrpt_dfs_err_imr_reg;
4111 u32 ptcl_imr_clr;
4112 u32 ptcl_imr_set;
4113 u32 cdma_imr_0_reg;
4114 u32 cdma_imr_0_clr;
4115 u32 cdma_imr_0_set;
4116 u32 cdma_imr_1_reg;
4117 u32 cdma_imr_1_clr;
4118 u32 cdma_imr_1_set;
4119 u32 phy_intf_imr_reg;
4120 u32 phy_intf_imr_clr;
4121 u32 phy_intf_imr_set;
4122 u32 rmac_imr_reg;
4123 u32 rmac_imr_clr;
4124 u32 rmac_imr_set;
4125 u32 tmac_imr_reg;
4126 u32 tmac_imr_clr;
4127 u32 tmac_imr_set;
4128 };
4129
4130 struct rtw89_imr_table {
4131 const struct rtw89_reg_imr *regs;
4132 u32 n_regs;
4133 };
4134
4135 struct rtw89_xtal_info {
4136 u32 xcap_reg;
4137 u32 sc_xo_mask;
4138 u32 sc_xi_mask;
4139 };
4140
4141 struct rtw89_rrsr_cfgs {
4142 struct rtw89_reg3_def ref_rate;
4143 struct rtw89_reg3_def rsc;
4144 };
4145
4146 struct rtw89_rfkill_regs {
4147 struct rtw89_reg3_def pinmux;
4148 struct rtw89_reg3_def mode;
4149 };
4150
4151 struct rtw89_dig_regs {
4152 u32 seg0_pd_reg;
4153 u32 pd_lower_bound_mask;
4154 u32 pd_spatial_reuse_en;
4155 u32 bmode_pd_reg;
4156 u32 bmode_cca_rssi_limit_en;
4157 u32 bmode_pd_lower_bound_reg;
4158 u32 bmode_rssi_nocca_low_th_mask;
4159 struct rtw89_reg_def p0_lna_init;
4160 struct rtw89_reg_def p1_lna_init;
4161 struct rtw89_reg_def p0_tia_init;
4162 struct rtw89_reg_def p1_tia_init;
4163 struct rtw89_reg_def p0_rxb_init;
4164 struct rtw89_reg_def p1_rxb_init;
4165 struct rtw89_reg_def p0_p20_pagcugc_en;
4166 struct rtw89_reg_def p0_s20_pagcugc_en;
4167 struct rtw89_reg_def p1_p20_pagcugc_en;
4168 struct rtw89_reg_def p1_s20_pagcugc_en;
4169 };
4170
4171 struct rtw89_edcca_regs {
4172 u32 edcca_level;
4173 u32 edcca_mask;
4174 u32 edcca_p_mask;
4175 u32 ppdu_level;
4176 u32 ppdu_mask;
4177 u32 rpt_a;
4178 u32 rpt_b;
4179 u32 rpt_sel;
4180 u32 rpt_sel_mask;
4181 u32 rpt_sel_be;
4182 u32 rpt_sel_be_mask;
4183 u32 tx_collision_t2r_st;
4184 u32 tx_collision_t2r_st_mask;
4185 };
4186
4187 struct rtw89_phy_ul_tb_info {
4188 bool dyn_tb_tri_en;
4189 u8 def_if_bandedge;
4190 };
4191
4192 struct rtw89_antdiv_stats {
4193 struct ewma_rssi cck_rssi_avg;
4194 struct ewma_rssi ofdm_rssi_avg;
4195 struct ewma_rssi non_legacy_rssi_avg;
4196 u16 pkt_cnt_cck;
4197 u16 pkt_cnt_ofdm;
4198 u16 pkt_cnt_non_legacy;
4199 u32 evm;
4200 };
4201
4202 struct rtw89_antdiv_info {
4203 struct rtw89_antdiv_stats target_stats;
4204 struct rtw89_antdiv_stats main_stats;
4205 struct rtw89_antdiv_stats aux_stats;
4206 u8 training_count;
4207 u8 rssi_pre;
4208 bool get_stats;
4209 };
4210
4211 enum rtw89_chanctx_state {
4212 RTW89_CHANCTX_STATE_MCC_START,
4213 RTW89_CHANCTX_STATE_MCC_STOP,
4214 };
4215
4216 enum rtw89_chanctx_callbacks {
4217 RTW89_CHANCTX_CALLBACK_PLACEHOLDER,
4218 RTW89_CHANCTX_CALLBACK_RFK,
4219
4220 NUM_OF_RTW89_CHANCTX_CALLBACKS,
4221 };
4222
4223 struct rtw89_chanctx_listener {
4224 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS])
4225 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state);
4226 };
4227
4228 struct rtw89_chip_info {
4229 enum rtw89_core_chip_id chip_id;
4230 enum rtw89_chip_gen chip_gen;
4231 const struct rtw89_chip_ops *ops;
4232 const struct rtw89_mac_gen_def *mac_def;
4233 const struct rtw89_phy_gen_def *phy_def;
4234 const char *fw_basename;
4235 u8 fw_format_max;
4236 bool try_ce_fw;
4237 u8 bbmcu_nr;
4238 u32 needed_fw_elms;
4239 const struct rtw89_fw_blacklist *fw_blacklist;
4240 u32 fifo_size;
4241 bool small_fifo_size;
4242 u32 dle_scc_rsvd_size;
4243 u16 max_amsdu_limit;
4244 bool dis_2g_40m_ul_ofdma;
4245 u32 rsvd_ple_ofst;
4246 const struct rtw89_hfc_param_ini *hfc_param_ini;
4247 const struct rtw89_dle_mem *dle_mem;
4248 u8 wde_qempty_acq_grpnum;
4249 u8 wde_qempty_mgq_grpsel;
4250 u32 rf_base_addr[2];
4251 u8 support_macid_num;
4252 u8 support_link_num;
4253 u8 support_chanctx_num;
4254 u8 support_bands;
4255 u16 support_bandwidths;
4256 bool support_unii4;
4257 bool support_rnr;
4258 bool ul_tb_waveform_ctrl;
4259 bool ul_tb_pwr_diff;
4260 bool hw_sec_hdr;
4261 bool hw_mgmt_tx_encrypt;
4262 u8 rf_path_num;
4263 u8 tx_nss;
4264 u8 rx_nss;
4265 u8 acam_num;
4266 u8 bcam_num;
4267 u8 scam_num;
4268 u8 bacam_num;
4269 u8 bacam_dynamic_num;
4270 enum rtw89_bacam_ver bacam_ver;
4271 u8 ppdu_max_usr;
4272
4273 u8 sec_ctrl_efuse_size;
4274 u32 physical_efuse_size;
4275 u32 logical_efuse_size;
4276 u32 limit_efuse_size;
4277 u32 dav_phy_efuse_size;
4278 u32 dav_log_efuse_size;
4279 u32 phycap_addr;
4280 u32 phycap_size;
4281 const struct rtw89_efuse_block_cfg *efuse_blocks;
4282
4283 const struct rtw89_pwr_cfg * const *pwr_on_seq;
4284 const struct rtw89_pwr_cfg * const *pwr_off_seq;
4285 const struct rtw89_phy_table *bb_table;
4286 const struct rtw89_phy_table *bb_gain_table;
4287 const struct rtw89_phy_table *rf_table[RF_PATH_MAX];
4288 const struct rtw89_phy_table *nctl_table;
4289 const struct rtw89_rfk_tbl *nctl_post_table;
4290 const struct rtw89_phy_dig_gain_table *dig_table;
4291 const struct rtw89_dig_regs *dig_regs;
4292 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table;
4293
4294 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */
4295 const struct rtw89_rfe_parms_conf *rfe_parms_conf;
4296 const struct rtw89_rfe_parms *dflt_parms;
4297 const struct rtw89_chanctx_listener *chanctx_listener;
4298
4299 u8 txpwr_factor_rf;
4300 u8 txpwr_factor_mac;
4301
4302 u32 para_ver;
4303 u32 wlcx_desired;
4304 u8 btcx_desired;
4305 u8 scbd;
4306 u8 mailbox;
4307
4308 u8 afh_guard_ch;
4309 const u8 *wl_rssi_thres;
4310 const u8 *bt_rssi_thres;
4311 u8 rssi_tol;
4312
4313 u8 mon_reg_num;
4314 const struct rtw89_btc_fbtc_mreg *mon_reg;
4315 u8 rf_para_ulink_num;
4316 const struct rtw89_btc_rf_trx_para *rf_para_ulink;
4317 u8 rf_para_dlink_num;
4318 const struct rtw89_btc_rf_trx_para *rf_para_dlink;
4319 u8 ps_mode_supported;
4320 u8 low_power_hci_modes;
4321
4322 u32 h2c_cctl_func_id;
4323 u32 hci_func_en_addr;
4324 u32 h2c_desc_size;
4325 u32 txwd_body_size;
4326 u32 txwd_info_size;
4327 u32 h2c_ctrl_reg;
4328 const u32 *h2c_regs;
4329 struct rtw89_reg_def h2c_counter_reg;
4330 u32 c2h_ctrl_reg;
4331 const u32 *c2h_regs;
4332 struct rtw89_reg_def c2h_counter_reg;
4333 const struct rtw89_page_regs *page_regs;
4334 const u32 *wow_reason_reg;
4335 bool cfo_src_fd;
4336 bool cfo_hw_comp;
4337 const struct rtw89_reg_def *dcfo_comp;
4338 u8 dcfo_comp_sft;
4339 const struct rtw89_imr_info *imr_info;
4340 const struct rtw89_imr_table *imr_dmac_table;
4341 const struct rtw89_imr_table *imr_cmac_table;
4342 const struct rtw89_rrsr_cfgs *rrsr_cfgs;
4343 struct rtw89_reg_def bss_clr_vld;
4344 u32 bss_clr_map_reg;
4345 const struct rtw89_rfkill_regs *rfkill_init;
4346 struct rtw89_reg_def rfkill_get;
4347 u32 dma_ch_mask;
4348 const struct rtw89_edcca_regs *edcca_regs;
4349 const struct wiphy_wowlan_support *wowlan_stub;
4350 const struct rtw89_xtal_info *xtal_info;
4351 };
4352
4353 union rtw89_bus_info {
4354 const struct rtw89_pci_info *pci;
4355 };
4356
4357 struct rtw89_driver_info {
4358 const struct rtw89_chip_info *chip;
4359 const struct dmi_system_id *quirks;
4360 union rtw89_bus_info bus;
4361 };
4362
4363 enum rtw89_hcifc_mode {
4364 RTW89_HCIFC_POH = 0,
4365 RTW89_HCIFC_STF = 1,
4366 RTW89_HCIFC_SDIO = 2,
4367
4368 /* keep last */
4369 RTW89_HCIFC_MODE_INVALID,
4370 };
4371
4372 struct rtw89_dle_info {
4373 const struct rtw89_rsvd_quota *rsvd_qt;
4374 enum rtw89_qta_mode qta_mode;
4375 u16 ple_pg_size;
4376 u16 ple_free_pg;
4377 u16 c0_rx_qta;
4378 u16 c1_rx_qta;
4379 };
4380
4381 enum rtw89_host_rpr_mode {
4382 RTW89_RPR_MODE_POH = 0,
4383 RTW89_RPR_MODE_STF
4384 };
4385
4386 #define RTW89_COMPLETION_BUF_SIZE 40
4387 #define RTW89_WAIT_COND_IDLE UINT_MAX
4388
4389 struct rtw89_completion_data {
4390 bool err;
4391 u8 buf[RTW89_COMPLETION_BUF_SIZE];
4392 };
4393
4394 struct rtw89_wait_info {
4395 atomic_t cond;
4396 struct completion completion;
4397 struct rtw89_completion_data data;
4398 };
4399
4400 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100)
4401
rtw89_init_wait(struct rtw89_wait_info * wait)4402 static inline void rtw89_init_wait(struct rtw89_wait_info *wait)
4403 {
4404 init_completion(&wait->completion);
4405 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
4406 }
4407
4408 struct rtw89_mac_info {
4409 struct rtw89_dle_info dle_info;
4410 struct rtw89_hfc_param hfc_param;
4411 enum rtw89_qta_mode qta_mode;
4412 u8 rpwm_seq_num;
4413 u8 cpwm_seq_num;
4414
4415 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */
4416 struct rtw89_wait_info fw_ofld_wait;
4417 /* see RTW89_PS_WAIT_COND series for wait condition */
4418 struct rtw89_wait_info ps_wait;
4419 };
4420
4421 enum rtw89_fwdl_check_type {
4422 RTW89_FWDL_CHECK_FREERTOS_DONE,
4423 RTW89_FWDL_CHECK_WCPU_FWDL_DONE,
4424 RTW89_FWDL_CHECK_DCPU_FWDL_DONE,
4425 RTW89_FWDL_CHECK_BB0_FWDL_DONE,
4426 RTW89_FWDL_CHECK_BB1_FWDL_DONE,
4427 };
4428
4429 enum rtw89_fw_type {
4430 RTW89_FW_NORMAL = 1,
4431 RTW89_FW_WOWLAN = 3,
4432 RTW89_FW_NORMAL_CE = 5,
4433 RTW89_FW_BBMCU0 = 64,
4434 RTW89_FW_BBMCU1 = 65,
4435 RTW89_FW_LOGFMT = 255,
4436 };
4437
4438 enum rtw89_fw_feature {
4439 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT,
4440 RTW89_FW_FEATURE_SCAN_OFFLOAD,
4441 RTW89_FW_FEATURE_TX_WAKE,
4442 RTW89_FW_FEATURE_CRASH_TRIGGER,
4443 RTW89_FW_FEATURE_NO_PACKET_DROP,
4444 RTW89_FW_FEATURE_NO_DEEP_PS,
4445 RTW89_FW_FEATURE_NO_LPS_PG,
4446 RTW89_FW_FEATURE_BEACON_FILTER,
4447 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP,
4448 RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V0,
4449 RTW89_FW_FEATURE_WOW_REASON_V1,
4450 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V0,
4451 };
4452
4453 struct rtw89_fw_suit {
4454 enum rtw89_fw_type type;
4455 const u8 *data;
4456 u32 size;
4457 u8 major_ver;
4458 u8 minor_ver;
4459 u8 sub_ver;
4460 u8 sub_idex;
4461 u16 build_year;
4462 u16 build_mon;
4463 u16 build_date;
4464 u16 build_hour;
4465 u16 build_min;
4466 u8 cmd_ver;
4467 u8 hdr_ver;
4468 u32 commitid;
4469 };
4470
4471 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \
4472 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx))
4473 #define RTW89_FW_SUIT_VER_CODE(s) \
4474 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex)
4475
4476 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \
4477 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \
4478 (mfw_hdr)->ver.minor, \
4479 (mfw_hdr)->ver.sub, \
4480 (mfw_hdr)->ver.idx)
4481
4482 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \
4483 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \
4484 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \
4485 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \
4486 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX))
4487
4488 struct rtw89_fw_req_info {
4489 const struct firmware *firmware;
4490 struct completion completion;
4491 };
4492
4493 struct rtw89_fw_log {
4494 struct rtw89_fw_suit suit;
4495 bool enable;
4496 u32 last_fmt_id;
4497 u32 fmt_count;
4498 const __le32 *fmt_ids;
4499 const char *(*fmts)[];
4500 };
4501
4502 struct rtw89_fw_elm_info {
4503 struct rtw89_phy_table *bb_tbl;
4504 struct rtw89_phy_table *bb_gain;
4505 struct rtw89_phy_table *rf_radio[RF_PATH_MAX];
4506 struct rtw89_phy_table *rf_nctl;
4507 struct rtw89_fw_txpwr_track_cfg *txpwr_trk;
4508 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt;
4509 };
4510
4511 enum rtw89_fw_mss_dev_type {
4512 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF,
4513 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF,
4514 };
4515
4516 struct rtw89_fw_secure {
4517 bool secure_boot;
4518 u32 sb_sel_mgn;
4519 u8 mss_dev_type;
4520 u8 mss_cust_idx;
4521 u8 mss_key_num;
4522 };
4523
4524 struct rtw89_fw_info {
4525 struct rtw89_fw_req_info req;
4526 int fw_format;
4527 u8 h2c_seq;
4528 u8 rec_seq;
4529 u8 h2c_counter;
4530 u8 c2h_counter;
4531 struct rtw89_fw_suit normal;
4532 struct rtw89_fw_suit wowlan;
4533 struct rtw89_fw_suit bbmcu0;
4534 struct rtw89_fw_suit bbmcu1;
4535 struct rtw89_fw_log log;
4536 u32 feature_map;
4537 struct rtw89_fw_elm_info elm_info;
4538 struct rtw89_fw_secure sec;
4539 };
4540
4541 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \
4542 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat)))
4543
4544 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \
4545 ((_fw)->feature_map |= BIT(_fw_feature))
4546
4547 struct rtw89_cam_info {
4548 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM);
4549 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM);
4550 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM);
4551 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM);
4552 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM];
4553 const struct rtw89_sec_cam_entry *sec_entries[RTW89_MAX_SEC_CAM_NUM];
4554 };
4555
4556 enum rtw89_sar_sources {
4557 RTW89_SAR_SOURCE_NONE,
4558 RTW89_SAR_SOURCE_COMMON,
4559
4560 RTW89_SAR_SOURCE_NR,
4561 };
4562
4563 enum rtw89_sar_subband {
4564 RTW89_SAR_2GHZ_SUBBAND,
4565 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */
4566 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */
4567 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */
4568 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */
4569 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */
4570 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */
4571 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */
4572 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */
4573 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */
4574
4575 RTW89_SAR_SUBBAND_NR,
4576 };
4577
4578 struct rtw89_sar_cfg_common {
4579 bool set[RTW89_SAR_SUBBAND_NR];
4580 s32 cfg[RTW89_SAR_SUBBAND_NR];
4581 };
4582
4583 struct rtw89_sar_info {
4584 /* used to decide how to acces SAR cfg union */
4585 enum rtw89_sar_sources src;
4586
4587 /* reserved for different knids of SAR cfg struct.
4588 * supposed that a single cfg struct cannot handle various SAR sources.
4589 */
4590 union {
4591 struct rtw89_sar_cfg_common cfg_common;
4592 };
4593 };
4594
4595 enum rtw89_tas_state {
4596 RTW89_TAS_STATE_DPR_OFF,
4597 RTW89_TAS_STATE_DPR_ON,
4598 RTW89_TAS_STATE_DPR_FORBID,
4599 };
4600
4601 #define RTW89_TAS_MAX_WINDOW 50
4602 struct rtw89_tas_info {
4603 s16 txpwr_history[RTW89_TAS_MAX_WINDOW];
4604 s32 total_txpwr;
4605 u8 cur_idx;
4606 s8 dpr_gap;
4607 s8 delta;
4608 enum rtw89_tas_state state;
4609 bool enable;
4610 };
4611
4612 struct rtw89_chanctx_cfg {
4613 enum rtw89_chanctx_idx idx;
4614 int ref_count;
4615 };
4616
4617 enum rtw89_chanctx_changes {
4618 RTW89_CHANCTX_REMOTE_STA_CHANGE,
4619 RTW89_CHANCTX_BCN_OFFSET_CHANGE,
4620 RTW89_CHANCTX_P2P_PS_CHANGE,
4621 RTW89_CHANCTX_BT_SLOT_CHANGE,
4622 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE,
4623
4624 NUM_OF_RTW89_CHANCTX_CHANGES,
4625 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES,
4626 };
4627
4628 enum rtw89_entity_mode {
4629 RTW89_ENTITY_MODE_SCC_OR_SMLD,
4630 RTW89_ENTITY_MODE_MCC_PREPARE,
4631 RTW89_ENTITY_MODE_MCC,
4632
4633 NUM_OF_RTW89_ENTITY_MODE,
4634 RTW89_ENTITY_MODE_INVALID = -EINVAL,
4635 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH,
4636 };
4637
4638 #define RTW89_MAX_INTERFACE_NUM 2
4639
4640 /* only valid when running with chanctx_ops */
4641 struct rtw89_entity_mgnt {
4642 struct list_head active_list;
4643 struct rtw89_vif *active_roles[RTW89_MAX_INTERFACE_NUM];
4644 enum rtw89_chanctx_idx chanctx_tbl[RTW89_MAX_INTERFACE_NUM]
4645 [__RTW89_MLD_MAX_LINK_NUM];
4646 };
4647
4648 struct rtw89_chanctx {
4649 struct cfg80211_chan_def chandef;
4650 struct rtw89_chan chan;
4651 struct rtw89_chan_rcd rcd;
4652
4653 /* only assigned when running with chanctx_ops */
4654 struct rtw89_chanctx_cfg *cfg;
4655 };
4656
4657 struct rtw89_edcca_bak {
4658 u8 a;
4659 u8 p;
4660 u8 ppdu;
4661 u8 th_old;
4662 };
4663
4664 enum rtw89_dm_type {
4665 RTW89_DM_DYNAMIC_EDCCA,
4666 };
4667
4668 struct rtw89_hal {
4669 u32 rx_fltr;
4670 u8 cv;
4671 u8 acv;
4672 u32 antenna_tx;
4673 u32 antenna_rx;
4674 u8 tx_nss;
4675 u8 rx_nss;
4676 bool tx_path_diversity;
4677 bool ant_diversity;
4678 bool ant_diversity_fixed;
4679 bool support_cckpd;
4680 bool support_igi;
4681 atomic_t roc_chanctx_idx;
4682
4683 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES);
4684 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_CHANCTX);
4685 struct rtw89_chanctx chanctx[NUM_OF_RTW89_CHANCTX];
4686 struct cfg80211_chan_def roc_chandef;
4687
4688 bool entity_active[RTW89_PHY_MAX];
4689 bool entity_pause;
4690 enum rtw89_entity_mode entity_mode;
4691 struct rtw89_entity_mgnt entity_mgnt;
4692
4693 struct rtw89_edcca_bak edcca_bak;
4694 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */
4695 };
4696
4697 #define RTW89_MAX_MAC_ID_NUM 128
4698 #define RTW89_MAX_PKT_OFLD_NUM 255
4699
4700 enum rtw89_flags {
4701 RTW89_FLAG_POWERON,
4702 RTW89_FLAG_DMAC_FUNC,
4703 RTW89_FLAG_CMAC0_FUNC,
4704 RTW89_FLAG_CMAC1_FUNC,
4705 RTW89_FLAG_FW_RDY,
4706 RTW89_FLAG_RUNNING,
4707 RTW89_FLAG_PROBE_DONE,
4708 RTW89_FLAG_BFEE_MON,
4709 RTW89_FLAG_BFEE_EN,
4710 RTW89_FLAG_BFEE_TIMER_KEEP,
4711 RTW89_FLAG_NAPI_RUNNING,
4712 RTW89_FLAG_LEISURE_PS,
4713 RTW89_FLAG_LOW_POWER_MODE,
4714 RTW89_FLAG_INACTIVE_PS,
4715 RTW89_FLAG_CRASH_SIMULATING,
4716 RTW89_FLAG_SER_HANDLING,
4717 RTW89_FLAG_WOWLAN,
4718 RTW89_FLAG_FORBIDDEN_TRACK_WROK,
4719 RTW89_FLAG_CHANGING_INTERFACE,
4720 RTW89_FLAG_HW_RFKILL_STATE,
4721
4722 NUM_OF_RTW89_FLAGS,
4723 };
4724
4725 enum rtw89_quirks {
4726 RTW89_QUIRK_PCI_BER,
4727
4728 NUM_OF_RTW89_QUIRKS,
4729 };
4730
4731 enum rtw89_pkt_drop_sel {
4732 RTW89_PKT_DROP_SEL_MACID_BE_ONCE,
4733 RTW89_PKT_DROP_SEL_MACID_BK_ONCE,
4734 RTW89_PKT_DROP_SEL_MACID_VI_ONCE,
4735 RTW89_PKT_DROP_SEL_MACID_VO_ONCE,
4736 RTW89_PKT_DROP_SEL_MACID_ALL,
4737 RTW89_PKT_DROP_SEL_MG0_ONCE,
4738 RTW89_PKT_DROP_SEL_HIQ_ONCE,
4739 RTW89_PKT_DROP_SEL_HIQ_PORT,
4740 RTW89_PKT_DROP_SEL_HIQ_MBSSID,
4741 RTW89_PKT_DROP_SEL_BAND,
4742 RTW89_PKT_DROP_SEL_BAND_ONCE,
4743 RTW89_PKT_DROP_SEL_REL_MACID,
4744 RTW89_PKT_DROP_SEL_REL_HIQ_PORT,
4745 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID,
4746 };
4747
4748 struct rtw89_pkt_drop_params {
4749 enum rtw89_pkt_drop_sel sel;
4750 enum rtw89_mac_idx mac_band;
4751 u8 macid;
4752 u8 port;
4753 u8 mbssid;
4754 bool tf_trs;
4755 u32 macid_band_sel[4];
4756 };
4757
4758 struct rtw89_pkt_stat {
4759 u16 beacon_nr;
4760 u32 rx_rate_cnt[RTW89_HW_RATE_NR];
4761 };
4762
4763 DECLARE_EWMA(thermal, 4, 4);
4764
4765 struct rtw89_phy_stat {
4766 struct ewma_thermal avg_thermal[RF_PATH_MAX];
4767 struct rtw89_pkt_stat cur_pkt_stat;
4768 struct rtw89_pkt_stat last_pkt_stat;
4769 };
4770
4771 enum rtw89_rfk_report_state {
4772 RTW89_RFK_STATE_START = 0x0,
4773 RTW89_RFK_STATE_OK = 0x1,
4774 RTW89_RFK_STATE_FAIL = 0x2,
4775 RTW89_RFK_STATE_TIMEOUT = 0x3,
4776 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4,
4777 };
4778
4779 struct rtw89_rfk_wait_info {
4780 struct completion completion;
4781 ktime_t start_time;
4782 enum rtw89_rfk_report_state state;
4783 u8 version;
4784 };
4785
4786 #define RTW89_DACK_PATH_NR 2
4787 #define RTW89_DACK_IDX_NR 2
4788 #define RTW89_DACK_MSBK_NR 16
4789 struct rtw89_dack_info {
4790 bool dack_done;
4791 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR];
4792 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
4793 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
4794 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
4795 u32 dack_cnt;
4796 bool addck_timeout[RTW89_DACK_PATH_NR];
4797 bool dadck_timeout[RTW89_DACK_PATH_NR];
4798 bool msbk_timeout[RTW89_DACK_PATH_NR];
4799 };
4800
4801 enum rtw89_rfk_chs_nrs {
4802 __RTW89_RFK_CHS_NR_V0 = 2,
4803 __RTW89_RFK_CHS_NR_V1 = 3,
4804
4805 RTW89_RFK_CHS_NR = __RTW89_RFK_CHS_NR_V1,
4806 };
4807
4808 struct rtw89_rfk_mcc_info {
4809 u8 ch[RTW89_RFK_CHS_NR];
4810 u8 band[RTW89_RFK_CHS_NR];
4811 u8 bw[RTW89_RFK_CHS_NR];
4812 u8 table_idx;
4813 };
4814
4815 #define RTW89_IQK_CHS_NR 2
4816 #define RTW89_IQK_PATH_NR 4
4817
4818 struct rtw89_lck_info {
4819 u8 thermal[RF_PATH_MAX];
4820 };
4821
4822 struct rtw89_rx_dck_info {
4823 u8 thermal[RF_PATH_MAX];
4824 };
4825
4826 struct rtw89_iqk_info {
4827 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4828 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4829 bool lok_fail[RTW89_IQK_PATH_NR];
4830 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4831 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4832 u32 iqk_fail_cnt;
4833 bool is_iqk_init;
4834 u32 iqk_channel[RTW89_IQK_CHS_NR];
4835 u8 iqk_band[RTW89_IQK_PATH_NR];
4836 u8 iqk_ch[RTW89_IQK_PATH_NR];
4837 u8 iqk_bw[RTW89_IQK_PATH_NR];
4838 u8 iqk_times;
4839 u8 version;
4840 u32 nb_txcfir[RTW89_IQK_PATH_NR];
4841 u32 nb_rxcfir[RTW89_IQK_PATH_NR];
4842 u32 bp_txkresult[RTW89_IQK_PATH_NR];
4843 u32 bp_rxkresult[RTW89_IQK_PATH_NR];
4844 u32 bp_iqkenable[RTW89_IQK_PATH_NR];
4845 bool is_wb_txiqk[RTW89_IQK_PATH_NR];
4846 bool is_wb_rxiqk[RTW89_IQK_PATH_NR];
4847 bool is_nbiqk;
4848 bool iqk_fft_en;
4849 bool iqk_xym_en;
4850 bool iqk_sram_en;
4851 bool iqk_cfir_en;
4852 u32 syn1to2;
4853 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4854 u8 iqk_table_idx[RTW89_IQK_PATH_NR];
4855 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4856 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4857 };
4858
4859 #define RTW89_DPK_RF_PATH 2
4860 #define RTW89_DPK_AVG_THERMAL_NUM 8
4861 #define RTW89_DPK_BKUP_NUM 2
4862 struct rtw89_dpk_bkup_para {
4863 enum rtw89_band band;
4864 enum rtw89_bandwidth bw;
4865 u8 ch;
4866 bool path_ok;
4867 u8 mdpd_en;
4868 u8 txagc_dpk;
4869 u8 ther_dpk;
4870 u8 gs;
4871 u16 pwsf;
4872 };
4873
4874 struct rtw89_dpk_info {
4875 bool is_dpk_enable;
4876 bool is_dpk_reload_en;
4877 u8 dpk_gs[RTW89_PHY_MAX];
4878 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4879 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4880 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4881 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4882 u8 cur_idx[RTW89_DPK_RF_PATH];
4883 u8 cur_k_set;
4884 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4885 u8 max_dpk_txagc[RTW89_DPK_RF_PATH];
4886 u32 dpk_order[RTW89_DPK_RF_PATH];
4887 };
4888
4889 struct rtw89_fem_info {
4890 bool elna_2g;
4891 bool elna_5g;
4892 bool epa_2g;
4893 bool epa_5g;
4894 bool epa_6g;
4895 };
4896
4897 struct rtw89_phy_ch_info {
4898 u8 rssi_min;
4899 u16 rssi_min_macid;
4900 u8 pre_rssi_min;
4901 u8 rssi_max;
4902 u16 rssi_max_macid;
4903 u8 rxsc_160;
4904 u8 rxsc_80;
4905 u8 rxsc_40;
4906 u8 rxsc_20;
4907 u8 rxsc_l;
4908 u8 is_noisy;
4909 };
4910
4911 struct rtw89_agc_gaincode_set {
4912 u8 lna_idx;
4913 u8 tia_idx;
4914 u8 rxb_idx;
4915 };
4916
4917 #define IGI_RSSI_TH_NUM 5
4918 #define FA_TH_NUM 4
4919 #define LNA_GAIN_NUM 7
4920 #define TIA_GAIN_NUM 2
4921 struct rtw89_dig_info {
4922 struct rtw89_agc_gaincode_set cur_gaincode;
4923 bool force_gaincode_idx_en;
4924 struct rtw89_agc_gaincode_set force_gaincode;
4925 u8 igi_rssi_th[IGI_RSSI_TH_NUM];
4926 u16 fa_th[FA_TH_NUM];
4927 u8 igi_rssi;
4928 u8 igi_fa_rssi;
4929 u8 fa_rssi_ofst;
4930 u8 dyn_igi_max;
4931 u8 dyn_igi_min;
4932 bool dyn_pd_th_en;
4933 u8 dyn_pd_th_max;
4934 u8 pd_low_th_ofst;
4935 u8 ib_pbk;
4936 s8 ib_pkpwr;
4937 s8 lna_gain_a[LNA_GAIN_NUM];
4938 s8 lna_gain_g[LNA_GAIN_NUM];
4939 s8 *lna_gain;
4940 s8 tia_gain_a[TIA_GAIN_NUM];
4941 s8 tia_gain_g[TIA_GAIN_NUM];
4942 s8 *tia_gain;
4943 bool is_linked_pre;
4944 bool bypass_dig;
4945 };
4946
4947 enum rtw89_multi_cfo_mode {
4948 RTW89_PKT_BASED_AVG_MODE = 0,
4949 RTW89_ENTRY_BASED_AVG_MODE = 1,
4950 RTW89_TP_BASED_AVG_MODE = 2,
4951 };
4952
4953 enum rtw89_phy_cfo_status {
4954 RTW89_PHY_DCFO_STATE_NORMAL = 0,
4955 RTW89_PHY_DCFO_STATE_ENHANCE = 1,
4956 RTW89_PHY_DCFO_STATE_HOLD = 2,
4957 RTW89_PHY_DCFO_STATE_MAX
4958 };
4959
4960 enum rtw89_phy_cfo_ul_ofdma_acc_mode {
4961 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0,
4962 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1
4963 };
4964
4965 struct rtw89_cfo_tracking_info {
4966 u16 cfo_timer_ms;
4967 bool cfo_trig_by_timer_en;
4968 enum rtw89_phy_cfo_status phy_cfo_status;
4969 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode;
4970 u8 phy_cfo_trk_cnt;
4971 bool is_adjust;
4972 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode;
4973 bool apply_compensation;
4974 u8 crystal_cap;
4975 u8 crystal_cap_default;
4976 u8 def_x_cap;
4977 s8 x_cap_ofst;
4978 u32 sta_cfo_tolerance;
4979 s32 cfo_tail[CFO_TRACK_MAX_USER];
4980 u16 cfo_cnt[CFO_TRACK_MAX_USER];
4981 s32 cfo_avg_pre;
4982 s32 cfo_avg[CFO_TRACK_MAX_USER];
4983 s32 pre_cfo_avg[CFO_TRACK_MAX_USER];
4984 s32 dcfo_avg;
4985 s32 dcfo_avg_pre;
4986 u32 packet_count;
4987 u32 packet_count_pre;
4988 s32 residual_cfo_acc;
4989 u8 phy_cfotrk_state;
4990 u8 phy_cfotrk_cnt;
4991 bool divergence_lock_en;
4992 u8 x_cap_lb;
4993 u8 x_cap_ub;
4994 u8 lock_cnt;
4995 };
4996
4997 enum rtw89_tssi_mode {
4998 RTW89_TSSI_NORMAL = 0,
4999 RTW89_TSSI_SCAN = 1,
5000 };
5001
5002 enum rtw89_tssi_alimk_band {
5003 TSSI_ALIMK_2G = 0,
5004 TSSI_ALIMK_5GL,
5005 TSSI_ALIMK_5GM,
5006 TSSI_ALIMK_5GH,
5007 TSSI_ALIMK_MAX
5008 };
5009
5010 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */
5011 #define TSSI_TRIM_CH_GROUP_NUM 8
5012 #define TSSI_TRIM_CH_GROUP_NUM_6G 16
5013
5014 #define TSSI_CCK_CH_GROUP_NUM 6
5015 #define TSSI_MCS_2G_CH_GROUP_NUM 5
5016 #define TSSI_MCS_5G_CH_GROUP_NUM 14
5017 #define TSSI_MCS_6G_CH_GROUP_NUM 32
5018 #define TSSI_MCS_CH_GROUP_NUM \
5019 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM)
5020 #define TSSI_MAX_CH_NUM 67
5021 #define TSSI_ALIMK_VALUE_NUM 8
5022
5023 struct rtw89_tssi_info {
5024 u8 thermal[RF_PATH_MAX];
5025 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM];
5026 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G];
5027 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM];
5028 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM];
5029 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM];
5030 s8 extra_ofst[RF_PATH_MAX];
5031 bool tssi_tracking_check[RF_PATH_MAX];
5032 u8 default_txagc_offset[RF_PATH_MAX];
5033 u32 base_thermal[RF_PATH_MAX];
5034 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM];
5035 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM];
5036 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM];
5037 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX];
5038 u32 tssi_alimk_time;
5039 };
5040
5041 struct rtw89_power_trim_info {
5042 bool pg_thermal_trim;
5043 bool pg_pa_bias_trim;
5044 u8 thermal_trim[RF_PATH_MAX];
5045 u8 pa_bias_trim[RF_PATH_MAX];
5046 u8 pad_bias_trim[RF_PATH_MAX];
5047 };
5048
5049 struct rtw89_regd {
5050 char alpha2[3];
5051 u8 txpwr_regd[RTW89_BAND_NUM];
5052 };
5053
5054 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX
5055 #define RTW89_5GHZ_UNII4_CHANNEL_NUM 3
5056 #define RTW89_5GHZ_UNII4_START_INDEX 25
5057
5058 struct rtw89_regulatory_info {
5059 const struct rtw89_regd *regd;
5060 enum rtw89_reg_6ghz_power reg_6ghz_power;
5061 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe;
5062 DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM);
5063 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM);
5064 DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM);
5065 };
5066
5067 enum rtw89_ifs_clm_application {
5068 RTW89_IFS_CLM_INIT = 0,
5069 RTW89_IFS_CLM_BACKGROUND = 1,
5070 RTW89_IFS_CLM_ACS = 2,
5071 RTW89_IFS_CLM_DIG = 3,
5072 RTW89_IFS_CLM_TDMA_DIG = 4,
5073 RTW89_IFS_CLM_DBG = 5,
5074 RTW89_IFS_CLM_DBG_MANUAL = 6
5075 };
5076
5077 enum rtw89_env_racing_lv {
5078 RTW89_RAC_RELEASE = 0,
5079 RTW89_RAC_LV_1 = 1,
5080 RTW89_RAC_LV_2 = 2,
5081 RTW89_RAC_LV_3 = 3,
5082 RTW89_RAC_LV_4 = 4,
5083 RTW89_RAC_MAX_NUM = 5
5084 };
5085
5086 struct rtw89_ccx_para_info {
5087 enum rtw89_env_racing_lv rac_lv;
5088 u16 mntr_time;
5089 u8 nhm_manual_th_ofst;
5090 u8 nhm_manual_th0;
5091 enum rtw89_ifs_clm_application ifs_clm_app;
5092 u32 ifs_clm_manual_th_times;
5093 u32 ifs_clm_manual_th0;
5094 u8 fahm_manual_th_ofst;
5095 u8 fahm_manual_th0;
5096 u8 fahm_numer_opt;
5097 u8 fahm_denom_opt;
5098 };
5099
5100 enum rtw89_ccx_edcca_opt_sc_idx {
5101 RTW89_CCX_EDCCA_SEG0_P0 = 0,
5102 RTW89_CCX_EDCCA_SEG0_S1 = 1,
5103 RTW89_CCX_EDCCA_SEG0_S2 = 2,
5104 RTW89_CCX_EDCCA_SEG0_S3 = 3,
5105 RTW89_CCX_EDCCA_SEG1_P0 = 4,
5106 RTW89_CCX_EDCCA_SEG1_S1 = 5,
5107 RTW89_CCX_EDCCA_SEG1_S2 = 6,
5108 RTW89_CCX_EDCCA_SEG1_S3 = 7
5109 };
5110
5111 enum rtw89_ccx_edcca_opt_bw_idx {
5112 RTW89_CCX_EDCCA_BW20_0 = 0,
5113 RTW89_CCX_EDCCA_BW20_1 = 1,
5114 RTW89_CCX_EDCCA_BW20_2 = 2,
5115 RTW89_CCX_EDCCA_BW20_3 = 3,
5116 RTW89_CCX_EDCCA_BW20_4 = 4,
5117 RTW89_CCX_EDCCA_BW20_5 = 5,
5118 RTW89_CCX_EDCCA_BW20_6 = 6,
5119 RTW89_CCX_EDCCA_BW20_7 = 7
5120 };
5121
5122 #define RTW89_NHM_TH_NUM 11
5123 #define RTW89_FAHM_TH_NUM 11
5124 #define RTW89_NHM_RPT_NUM 12
5125 #define RTW89_FAHM_RPT_NUM 12
5126 #define RTW89_IFS_CLM_NUM 4
5127 struct rtw89_env_monitor_info {
5128 u8 ccx_watchdog_result;
5129 bool ccx_ongoing;
5130 u8 ccx_rac_lv;
5131 bool ccx_manual_ctrl;
5132 u16 ifs_clm_mntr_time;
5133 enum rtw89_ifs_clm_application ifs_clm_app;
5134 u16 ccx_period;
5135 u8 ccx_unit_idx;
5136 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM];
5137 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM];
5138 u16 ifs_clm_tx;
5139 u16 ifs_clm_edcca_excl_cca;
5140 u16 ifs_clm_ofdmfa;
5141 u16 ifs_clm_ofdmcca_excl_fa;
5142 u16 ifs_clm_cckfa;
5143 u16 ifs_clm_cckcca_excl_fa;
5144 u16 ifs_clm_total_ifs;
5145 u8 ifs_clm_his[RTW89_IFS_CLM_NUM];
5146 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM];
5147 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM];
5148 u8 ifs_clm_tx_ratio;
5149 u8 ifs_clm_edcca_excl_cca_ratio;
5150 u8 ifs_clm_cck_fa_ratio;
5151 u8 ifs_clm_ofdm_fa_ratio;
5152 u8 ifs_clm_cck_cca_excl_fa_ratio;
5153 u8 ifs_clm_ofdm_cca_excl_fa_ratio;
5154 u16 ifs_clm_cck_fa_permil;
5155 u16 ifs_clm_ofdm_fa_permil;
5156 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM];
5157 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM];
5158 };
5159
5160 enum rtw89_ser_rcvy_step {
5161 RTW89_SER_DRV_STOP_TX,
5162 RTW89_SER_DRV_STOP_RX,
5163 RTW89_SER_DRV_STOP_RUN,
5164 RTW89_SER_HAL_STOP_DMA,
5165 RTW89_SER_SUPPRESS_LOG,
5166 RTW89_NUM_OF_SER_FLAGS
5167 };
5168
5169 struct rtw89_ser {
5170 u8 state;
5171 u8 alarm_event;
5172 bool prehandle_l1;
5173
5174 struct work_struct ser_hdl_work;
5175 struct delayed_work ser_alarm_work;
5176 const struct state_ent *st_tbl;
5177 const struct event_ent *ev_tbl;
5178 struct list_head msg_q;
5179 spinlock_t msg_q_lock; /* lock when read/write ser msg */
5180 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS);
5181 };
5182
5183 enum rtw89_mac_ax_ps_mode {
5184 RTW89_MAC_AX_PS_MODE_ACTIVE = 0,
5185 RTW89_MAC_AX_PS_MODE_LEGACY = 1,
5186 RTW89_MAC_AX_PS_MODE_WMMPS = 2,
5187 RTW89_MAC_AX_PS_MODE_MAX = 3,
5188 };
5189
5190 enum rtw89_last_rpwm_mode {
5191 RTW89_LAST_RPWM_PS = 0x0,
5192 RTW89_LAST_RPWM_ACTIVE = 0x6,
5193 };
5194
5195 struct rtw89_lps_parm {
5196 u8 macid;
5197 u8 psmode; /* enum rtw89_mac_ax_ps_mode */
5198 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */
5199 };
5200
5201 struct rtw89_ppdu_sts_info {
5202 struct sk_buff_head rx_queue[RTW89_PHY_MAX];
5203 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX];
5204 };
5205
5206 struct rtw89_early_h2c {
5207 struct list_head list;
5208 u8 *h2c;
5209 u16 h2c_len;
5210 };
5211
5212 struct rtw89_hw_scan_info {
5213 struct rtw89_vif_link *scanning_vif;
5214 struct list_head pkt_list[NUM_NL80211_BANDS];
5215 struct rtw89_chan op_chan;
5216 bool abort;
5217 u32 last_chan_idx;
5218 };
5219
5220 enum rtw89_phy_bb_gain_band {
5221 RTW89_BB_GAIN_BAND_2G = 0,
5222 RTW89_BB_GAIN_BAND_5G_L = 1,
5223 RTW89_BB_GAIN_BAND_5G_M = 2,
5224 RTW89_BB_GAIN_BAND_5G_H = 3,
5225 RTW89_BB_GAIN_BAND_6G_L = 4,
5226 RTW89_BB_GAIN_BAND_6G_M = 5,
5227 RTW89_BB_GAIN_BAND_6G_H = 6,
5228 RTW89_BB_GAIN_BAND_6G_UH = 7,
5229
5230 RTW89_BB_GAIN_BAND_NR,
5231 };
5232
5233 enum rtw89_phy_gain_band_be {
5234 RTW89_BB_GAIN_BAND_2G_BE = 0,
5235 RTW89_BB_GAIN_BAND_5G_L_BE = 1,
5236 RTW89_BB_GAIN_BAND_5G_M_BE = 2,
5237 RTW89_BB_GAIN_BAND_5G_H_BE = 3,
5238 RTW89_BB_GAIN_BAND_6G_L0_BE = 4,
5239 RTW89_BB_GAIN_BAND_6G_L1_BE = 5,
5240 RTW89_BB_GAIN_BAND_6G_M0_BE = 6,
5241 RTW89_BB_GAIN_BAND_6G_M1_BE = 7,
5242 RTW89_BB_GAIN_BAND_6G_H0_BE = 8,
5243 RTW89_BB_GAIN_BAND_6G_H1_BE = 9,
5244 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10,
5245 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11,
5246
5247 RTW89_BB_GAIN_BAND_NR_BE,
5248 };
5249
5250 enum rtw89_phy_bb_bw_be {
5251 RTW89_BB_BW_20_40 = 0,
5252 RTW89_BB_BW_80_160_320 = 1,
5253
5254 RTW89_BB_BW_NR_BE,
5255 };
5256
5257 enum rtw89_bw20_sc {
5258 RTW89_BW20_SC_20M = 1,
5259 RTW89_BW20_SC_40M = 2,
5260 RTW89_BW20_SC_80M = 4,
5261 RTW89_BW20_SC_160M = 8,
5262 RTW89_BW20_SC_320M = 16,
5263 };
5264
5265 enum rtw89_cmac_table_bw {
5266 RTW89_CMAC_BW_20M = 0,
5267 RTW89_CMAC_BW_40M = 1,
5268 RTW89_CMAC_BW_80M = 2,
5269 RTW89_CMAC_BW_160M = 3,
5270 RTW89_CMAC_BW_320M = 4,
5271
5272 RTW89_CMAC_BW_NR,
5273 };
5274
5275 enum rtw89_phy_bb_rxsc_num {
5276 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */
5277 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */
5278 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */
5279 };
5280
5281 struct rtw89_phy_bb_gain_info {
5282 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
5283 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM];
5284 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
5285 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
5286 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5287 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */
5288 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX];
5289 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5290 [RTW89_BB_RXSC_NUM_40];
5291 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5292 [RTW89_BB_RXSC_NUM_80];
5293 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5294 [RTW89_BB_RXSC_NUM_160];
5295 };
5296
5297 struct rtw89_phy_bb_gain_info_be {
5298 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX]
5299 [LNA_GAIN_NUM];
5300 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX]
5301 [TIA_GAIN_NUM];
5302 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
5303 [RF_PATH_MAX][LNA_GAIN_NUM];
5304 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
5305 [RF_PATH_MAX][LNA_GAIN_NUM];
5306 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
5307 [RF_PATH_MAX][LNA_GAIN_NUM + 1];
5308 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5309 [RTW89_BW20_SC_20M];
5310 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5311 [RTW89_BW20_SC_40M];
5312 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5313 [RTW89_BW20_SC_80M];
5314 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5315 [RTW89_BW20_SC_160M];
5316 };
5317
5318 struct rtw89_phy_efuse_gain {
5319 bool offset_valid;
5320 bool comp_valid;
5321 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */
5322 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */
5323 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */
5324 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */
5325 };
5326
5327 #define RTW89_MAX_PATTERN_NUM 18
5328 #define RTW89_MAX_PATTERN_MASK_SIZE 4
5329 #define RTW89_MAX_PATTERN_SIZE 128
5330
5331 struct rtw89_wow_cam_info {
5332 bool r_w;
5333 u8 idx;
5334 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE];
5335 u16 crc;
5336 bool negative_pattern_match;
5337 bool skip_mac_hdr;
5338 bool uc;
5339 bool mc;
5340 bool bc;
5341 bool valid;
5342 };
5343
5344 struct rtw89_wow_key_info {
5345 u8 ptk_tx_iv[8];
5346 u8 valid_check;
5347 u8 symbol_check_en;
5348 u8 gtk_keyidx;
5349 u8 rsvd[5];
5350 u8 ptk_rx_iv[8];
5351 u8 gtk_rx_iv[4][8];
5352 } __packed;
5353
5354 struct rtw89_wow_gtk_info {
5355 u8 kck[32];
5356 u8 kek[32];
5357 u8 tk1[16];
5358 u8 txmickey[8];
5359 u8 rxmickey[8];
5360 __le32 igtk_keyid;
5361 __le64 ipn;
5362 u8 igtk[2][32];
5363 u8 psk[32];
5364 } __packed;
5365
5366 struct rtw89_wow_aoac_report {
5367 u8 rpt_ver;
5368 u8 sec_type;
5369 u8 key_idx;
5370 u8 pattern_idx;
5371 u8 rekey_ok;
5372 u8 ptk_tx_iv[8];
5373 u8 eapol_key_replay_count[8];
5374 u8 gtk[32];
5375 u8 ptk_rx_iv[8];
5376 u8 gtk_rx_iv[4][8];
5377 u64 igtk_key_id;
5378 u64 igtk_ipn;
5379 u8 igtk[32];
5380 u8 csa_pri_ch;
5381 u8 csa_bw;
5382 u8 csa_ch_offset;
5383 u8 csa_chsw_failed;
5384 u8 csa_ch_band;
5385 };
5386
5387 struct rtw89_wow_param {
5388 struct rtw89_vif_link *rtwvif_link;
5389 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM);
5390 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM];
5391 struct rtw89_wow_key_info key_info;
5392 struct rtw89_wow_gtk_info gtk_info;
5393 struct rtw89_wow_aoac_report aoac_rpt;
5394 u8 pattern_cnt;
5395 u8 ptk_alg;
5396 u8 gtk_alg;
5397 u8 ptk_keyidx;
5398 u8 akm;
5399
5400 /* see RTW89_WOW_WAIT_COND series for wait condition */
5401 struct rtw89_wait_info wait;
5402
5403 bool pno_inited;
5404 struct list_head pno_pkt_list;
5405 struct cfg80211_sched_scan_request *nd_config;
5406 };
5407
5408 struct rtw89_mcc_limit {
5409 bool enable;
5410 u16 max_tob; /* TU; max time offset behind */
5411 u16 max_toa; /* TU; max time offset ahead */
5412 u16 max_dur; /* TU */
5413 };
5414
5415 struct rtw89_mcc_policy {
5416 u8 c2h_rpt;
5417 u8 tx_null_early;
5418 u8 dis_tx_null;
5419 u8 in_curr_ch;
5420 u8 dis_sw_retry;
5421 u8 sw_retry_count;
5422 };
5423
5424 struct rtw89_mcc_role {
5425 struct rtw89_vif_link *rtwvif_link;
5426 struct rtw89_mcc_policy policy;
5427 struct rtw89_mcc_limit limit;
5428
5429 /* only valid when running with FW MRC mechanism */
5430 u8 slot_idx;
5431
5432 /* byte-array in LE order for FW */
5433 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)];
5434
5435 u16 duration; /* TU */
5436 u16 beacon_interval; /* TU */
5437 bool is_2ghz;
5438 bool is_go;
5439 bool is_gc;
5440 };
5441
5442 struct rtw89_mcc_bt_role {
5443 u16 duration; /* TU */
5444 };
5445
5446 struct rtw89_mcc_courtesy {
5447 bool enable;
5448 u8 slot_num;
5449 u8 macid_src;
5450 u8 macid_tgt;
5451 };
5452
5453 enum rtw89_mcc_plan {
5454 RTW89_MCC_PLAN_TAIL_BT,
5455 RTW89_MCC_PLAN_MID_BT,
5456 RTW89_MCC_PLAN_NO_BT,
5457
5458 NUM_OF_RTW89_MCC_PLAN,
5459 };
5460
5461 struct rtw89_mcc_pattern {
5462 s16 tob_ref; /* TU; time offset behind of reference role */
5463 s16 toa_ref; /* TU; time offset ahead of reference role */
5464 s16 tob_aux; /* TU; time offset behind of auxiliary role */
5465 s16 toa_aux; /* TU; time offset ahead of auxiliary role */
5466
5467 enum rtw89_mcc_plan plan;
5468 struct rtw89_mcc_courtesy courtesy;
5469 };
5470
5471 struct rtw89_mcc_sync {
5472 bool enable;
5473 u16 offset; /* TU */
5474 u8 macid_src;
5475 u8 band_src;
5476 u8 port_src;
5477 u8 macid_tgt;
5478 u8 band_tgt;
5479 u8 port_tgt;
5480 };
5481
5482 struct rtw89_mcc_config {
5483 struct rtw89_mcc_pattern pattern;
5484 struct rtw89_mcc_sync sync;
5485 u64 start_tsf;
5486 u16 mcc_interval; /* TU */
5487 u16 beacon_offset; /* TU */
5488 };
5489
5490 enum rtw89_mcc_mode {
5491 RTW89_MCC_MODE_GO_STA,
5492 RTW89_MCC_MODE_GC_STA,
5493 };
5494
5495 struct rtw89_mcc_info {
5496 struct rtw89_wait_info wait;
5497
5498 u8 group;
5499 enum rtw89_mcc_mode mode;
5500 struct rtw89_mcc_role role_ref; /* reference role */
5501 struct rtw89_mcc_role role_aux; /* auxiliary role */
5502 struct rtw89_mcc_bt_role bt_role;
5503 struct rtw89_mcc_config config;
5504 };
5505
5506 struct rtw89_dev {
5507 struct ieee80211_hw *hw;
5508 struct device *dev;
5509 const struct ieee80211_ops *ops;
5510
5511 bool dbcc_en;
5512 bool support_mlo;
5513 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode;
5514 struct rtw89_hw_scan_info scan_info;
5515 const struct rtw89_chip_info *chip;
5516 const struct rtw89_pci_info *pci_info;
5517 const struct rtw89_rfe_parms *rfe_parms;
5518 struct rtw89_hal hal;
5519 struct rtw89_mcc_info mcc;
5520 struct rtw89_mac_info mac;
5521 struct rtw89_fw_info fw;
5522 struct rtw89_hci_info hci;
5523 struct rtw89_efuse efuse;
5524 struct rtw89_traffic_stats stats;
5525 struct rtw89_rfe_data *rfe_data;
5526
5527 /* ensures exclusive access from mac80211 callbacks */
5528 struct mutex mutex;
5529 struct list_head rtwvifs_list;
5530 /* used to protect rf read write */
5531 struct mutex rf_mutex;
5532 struct workqueue_struct *txq_wq;
5533 struct work_struct txq_work;
5534 struct delayed_work txq_reinvoke_work;
5535 /* used to protect ba_list and forbid_ba_list */
5536 spinlock_t ba_lock;
5537 /* txqs to setup ba session */
5538 struct list_head ba_list;
5539 /* txqs to forbid ba session */
5540 struct list_head forbid_ba_list;
5541 struct work_struct ba_work;
5542 /* used to protect rpwm */
5543 spinlock_t rpwm_lock;
5544
5545 struct list_head tx_waits;
5546 struct wiphy_delayed_work tx_wait_work;
5547
5548 struct rtw89_cam_info cam_info;
5549
5550 struct sk_buff_head c2h_queue;
5551 struct work_struct c2h_work;
5552 struct work_struct ips_work;
5553 struct work_struct load_firmware_work;
5554 struct work_struct cancel_6ghz_probe_work;
5555
5556 struct list_head early_h2c_list;
5557
5558 struct rtw89_ser ser;
5559
5560 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM);
5561 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM);
5562 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS);
5563 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM);
5564 DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS);
5565
5566 struct rtw89_phy_stat phystat;
5567 struct rtw89_rfk_wait_info rfk_wait;
5568 struct rtw89_dack_info dack;
5569 struct rtw89_iqk_info iqk;
5570 struct rtw89_dpk_info dpk;
5571 struct rtw89_rfk_mcc_info rfk_mcc;
5572 struct rtw89_lck_info lck;
5573 struct rtw89_rx_dck_info rx_dck;
5574 bool is_tssi_mode[RF_PATH_MAX];
5575 bool is_bt_iqk_timeout;
5576
5577 struct rtw89_fem_info fem;
5578 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM];
5579 struct rtw89_tssi_info tssi;
5580 struct rtw89_power_trim_info pwr_trim;
5581
5582 struct rtw89_cfo_tracking_info cfo_tracking;
5583 struct rtw89_env_monitor_info env_monitor;
5584 struct rtw89_dig_info dig;
5585 struct rtw89_phy_ch_info ch_info;
5586 union {
5587 struct rtw89_phy_bb_gain_info ax;
5588 struct rtw89_phy_bb_gain_info_be be;
5589 } bb_gain;
5590 struct rtw89_phy_efuse_gain efuse_gain;
5591 struct rtw89_phy_ul_tb_info ul_tb_info;
5592 struct rtw89_antdiv_info antdiv;
5593
5594 struct delayed_work track_work;
5595 struct delayed_work chanctx_work;
5596 struct delayed_work coex_act1_work;
5597 struct delayed_work coex_bt_devinfo_work;
5598 struct delayed_work coex_rfk_chk_work;
5599 struct delayed_work cfo_track_work;
5600 struct delayed_work forbid_ba_work;
5601 struct delayed_work roc_work;
5602 struct delayed_work antdiv_work;
5603 struct rtw89_ppdu_sts_info ppdu_sts;
5604 u8 total_sta_assoc;
5605 bool scanning;
5606
5607 struct rtw89_regulatory_info regulatory;
5608 struct rtw89_sar_info sar;
5609 struct rtw89_tas_info tas;
5610
5611 struct rtw89_btc btc;
5612 enum rtw89_ps_mode ps_mode;
5613 bool lps_enabled;
5614
5615 struct rtw89_wow_param wow;
5616
5617 /* napi structure */
5618 struct net_device *netdev;
5619 struct napi_struct napi;
5620 int napi_budget_countdown;
5621
5622 struct rtw89_debugfs *debugfs;
5623
5624 /* HCI related data, keep last */
5625 u8 priv[] __aligned(sizeof(void *));
5626 };
5627
5628 struct rtw89_vif {
5629 struct rtw89_dev *rtwdev;
5630 struct list_head list;
5631 struct list_head mgnt_entry;
5632
5633 u8 mac_addr[ETH_ALEN];
5634 __be32 ip_addr;
5635
5636 struct rtw89_traffic_stats stats;
5637 u32 tdls_peer;
5638
5639 struct ieee80211_scan_ies *scan_ies;
5640 struct cfg80211_scan_request *scan_req;
5641
5642 struct rtw89_roc roc;
5643 bool offchan;
5644
5645 u8 links_inst_valid_num;
5646 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM);
5647 struct rtw89_vif_link *links[IEEE80211_MLD_MAX_NUM_LINKS];
5648 struct rtw89_vif_link links_inst[] __counted_by(links_inst_valid_num);
5649 };
5650
rtw89_vif_assign_link_is_valid(struct rtw89_vif_link ** rtwvif_link,const struct rtw89_vif * rtwvif,unsigned int link_id)5651 static inline bool rtw89_vif_assign_link_is_valid(struct rtw89_vif_link **rtwvif_link,
5652 const struct rtw89_vif *rtwvif,
5653 unsigned int link_id)
5654 {
5655 *rtwvif_link = rtwvif->links[link_id];
5656 return !!*rtwvif_link;
5657 }
5658
5659 #define rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) \
5660 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \
5661 if (rtw89_vif_assign_link_is_valid(&(rtwvif_link), rtwvif, link_id))
5662
5663 struct rtw89_sta {
5664 struct rtw89_dev *rtwdev;
5665 struct rtw89_vif *rtwvif;
5666
5667 bool disassoc;
5668
5669 struct sk_buff_head roc_queue;
5670
5671 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS];
5672 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS);
5673
5674 u8 links_inst_valid_num;
5675 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM);
5676 struct rtw89_sta_link *links[IEEE80211_MLD_MAX_NUM_LINKS];
5677 struct rtw89_sta_link links_inst[] __counted_by(links_inst_valid_num);
5678 };
5679
rtw89_sta_assign_link_is_valid(struct rtw89_sta_link ** rtwsta_link,const struct rtw89_sta * rtwsta,unsigned int link_id)5680 static inline bool rtw89_sta_assign_link_is_valid(struct rtw89_sta_link **rtwsta_link,
5681 const struct rtw89_sta *rtwsta,
5682 unsigned int link_id)
5683 {
5684 *rtwsta_link = rtwsta->links[link_id];
5685 return !!*rtwsta_link;
5686 }
5687
5688 #define rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) \
5689 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \
5690 if (rtw89_sta_assign_link_is_valid(&(rtwsta_link), rtwsta, link_id))
5691
rtw89_vif_get_main_macid(struct rtw89_vif * rtwvif)5692 static inline u8 rtw89_vif_get_main_macid(struct rtw89_vif *rtwvif)
5693 {
5694 /* const after init, so no need to check if active first */
5695 return rtwvif->links_inst[0].mac_id;
5696 }
5697
rtw89_vif_get_main_port(struct rtw89_vif * rtwvif)5698 static inline u8 rtw89_vif_get_main_port(struct rtw89_vif *rtwvif)
5699 {
5700 /* const after init, so no need to check if active first */
5701 return rtwvif->links_inst[0].port;
5702 }
5703
5704 static inline struct rtw89_vif_link *
rtw89_vif_get_link_inst(struct rtw89_vif * rtwvif,u8 index)5705 rtw89_vif_get_link_inst(struct rtw89_vif *rtwvif, u8 index)
5706 {
5707 if (index >= rtwvif->links_inst_valid_num ||
5708 !test_bit(index, rtwvif->links_inst_map))
5709 return NULL;
5710 return &rtwvif->links_inst[index];
5711 }
5712
5713 static inline
rtw89_vif_link_inst_get_index(struct rtw89_vif_link * rtwvif_link)5714 u8 rtw89_vif_link_inst_get_index(struct rtw89_vif_link *rtwvif_link)
5715 {
5716 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
5717
5718 return rtwvif_link - rtwvif->links_inst;
5719 }
5720
rtw89_sta_get_main_macid(struct rtw89_sta * rtwsta)5721 static inline u8 rtw89_sta_get_main_macid(struct rtw89_sta *rtwsta)
5722 {
5723 /* const after init, so no need to check if active first */
5724 return rtwsta->links_inst[0].mac_id;
5725 }
5726
5727 static inline struct rtw89_sta_link *
rtw89_sta_get_link_inst(struct rtw89_sta * rtwsta,u8 index)5728 rtw89_sta_get_link_inst(struct rtw89_sta *rtwsta, u8 index)
5729 {
5730 if (index >= rtwsta->links_inst_valid_num ||
5731 !test_bit(index, rtwsta->links_inst_map))
5732 return NULL;
5733 return &rtwsta->links_inst[index];
5734 }
5735
5736 static inline
rtw89_sta_link_inst_get_index(struct rtw89_sta_link * rtwsta_link)5737 u8 rtw89_sta_link_inst_get_index(struct rtw89_sta_link *rtwsta_link)
5738 {
5739 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta;
5740
5741 return rtwsta_link - rtwsta->links_inst;
5742 }
5743
rtw89_tx_wait_release(struct rtw89_tx_wait_info * wait)5744 static inline void rtw89_tx_wait_release(struct rtw89_tx_wait_info *wait)
5745 {
5746 dev_kfree_skb_any(wait->skb);
5747 kfree_rcu(wait, rcu_head);
5748 }
5749
rtw89_tx_wait_list_clear(struct rtw89_dev * rtwdev)5750 static inline void rtw89_tx_wait_list_clear(struct rtw89_dev *rtwdev)
5751 {
5752 struct rtw89_tx_wait_info *wait, *tmp;
5753
5754 lockdep_assert_wiphy(rtwdev->hw->wiphy);
5755
5756 list_for_each_entry_safe(wait, tmp, &rtwdev->tx_waits, list) {
5757 if (!completion_done(&wait->completion))
5758 continue;
5759 list_del(&wait->list);
5760 rtw89_tx_wait_release(wait);
5761 }
5762 }
5763
rtw89_hci_tx_write(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)5764 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev,
5765 struct rtw89_core_tx_request *tx_req)
5766 {
5767 return rtwdev->hci.ops->tx_write(rtwdev, tx_req);
5768 }
5769
rtw89_hci_reset(struct rtw89_dev * rtwdev)5770 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev)
5771 {
5772 rtwdev->hci.ops->reset(rtwdev);
5773 rtw89_tx_wait_list_clear(rtwdev);
5774 }
5775
rtw89_hci_start(struct rtw89_dev * rtwdev)5776 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev)
5777 {
5778 return rtwdev->hci.ops->start(rtwdev);
5779 }
5780
rtw89_hci_stop(struct rtw89_dev * rtwdev)5781 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev)
5782 {
5783 rtwdev->hci.ops->stop(rtwdev);
5784 }
5785
rtw89_hci_deinit(struct rtw89_dev * rtwdev)5786 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev)
5787 {
5788 return rtwdev->hci.ops->deinit(rtwdev);
5789 }
5790
rtw89_hci_pause(struct rtw89_dev * rtwdev,bool pause)5791 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause)
5792 {
5793 rtwdev->hci.ops->pause(rtwdev, pause);
5794 }
5795
rtw89_hci_switch_mode(struct rtw89_dev * rtwdev,bool low_power)5796 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power)
5797 {
5798 rtwdev->hci.ops->switch_mode(rtwdev, low_power);
5799 }
5800
rtw89_hci_recalc_int_mit(struct rtw89_dev * rtwdev)5801 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev)
5802 {
5803 rtwdev->hci.ops->recalc_int_mit(rtwdev);
5804 }
5805
rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev * rtwdev,u8 txch)5806 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch)
5807 {
5808 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch);
5809 }
5810
rtw89_hci_tx_kick_off(struct rtw89_dev * rtwdev,u8 txch)5811 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch)
5812 {
5813 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch);
5814 }
5815
rtw89_hci_mac_pre_deinit(struct rtw89_dev * rtwdev)5816 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev)
5817 {
5818 return rtwdev->hci.ops->mac_pre_deinit(rtwdev);
5819 }
5820
rtw89_hci_flush_queues(struct rtw89_dev * rtwdev,u32 queues,bool drop)5821 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues,
5822 bool drop)
5823 {
5824 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
5825 return;
5826
5827 if (rtwdev->hci.ops->flush_queues)
5828 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop);
5829 }
5830
rtw89_hci_recovery_start(struct rtw89_dev * rtwdev)5831 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev)
5832 {
5833 if (rtwdev->hci.ops->recovery_start)
5834 rtwdev->hci.ops->recovery_start(rtwdev);
5835 }
5836
rtw89_hci_recovery_complete(struct rtw89_dev * rtwdev)5837 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev)
5838 {
5839 if (rtwdev->hci.ops->recovery_complete)
5840 rtwdev->hci.ops->recovery_complete(rtwdev);
5841 }
5842
rtw89_hci_enable_intr(struct rtw89_dev * rtwdev)5843 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev)
5844 {
5845 if (rtwdev->hci.ops->enable_intr)
5846 rtwdev->hci.ops->enable_intr(rtwdev);
5847 }
5848
rtw89_hci_disable_intr(struct rtw89_dev * rtwdev)5849 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev)
5850 {
5851 if (rtwdev->hci.ops->disable_intr)
5852 rtwdev->hci.ops->disable_intr(rtwdev);
5853 }
5854
rtw89_hci_ctrl_txdma_ch(struct rtw89_dev * rtwdev,bool enable)5855 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable)
5856 {
5857 if (rtwdev->hci.ops->ctrl_txdma_ch)
5858 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable);
5859 }
5860
rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev * rtwdev,bool enable)5861 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable)
5862 {
5863 if (rtwdev->hci.ops->ctrl_txdma_fw_ch)
5864 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable);
5865 }
5866
rtw89_hci_ctrl_trxhci(struct rtw89_dev * rtwdev,bool enable)5867 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable)
5868 {
5869 if (rtwdev->hci.ops->ctrl_trxhci)
5870 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable);
5871 }
5872
rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev * rtwdev)5873 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev)
5874 {
5875 int ret = 0;
5876
5877 if (rtwdev->hci.ops->poll_txdma_ch_idle)
5878 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev);
5879 return ret;
5880 }
5881
rtw89_hci_clr_idx_all(struct rtw89_dev * rtwdev)5882 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev)
5883 {
5884 if (rtwdev->hci.ops->clr_idx_all)
5885 rtwdev->hci.ops->clr_idx_all(rtwdev);
5886 }
5887
rtw89_hci_rst_bdram(struct rtw89_dev * rtwdev)5888 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev)
5889 {
5890 int ret = 0;
5891
5892 if (rtwdev->hci.ops->rst_bdram)
5893 ret = rtwdev->hci.ops->rst_bdram(rtwdev);
5894 return ret;
5895 }
5896
rtw89_hci_clear(struct rtw89_dev * rtwdev,struct pci_dev * pdev)5897 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev)
5898 {
5899 if (rtwdev->hci.ops->clear)
5900 rtwdev->hci.ops->clear(rtwdev, pdev);
5901 }
5902
5903 static inline
RTW89_TX_SKB_CB(struct sk_buff * skb)5904 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb)
5905 {
5906 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
5907
5908 return (struct rtw89_tx_skb_data *)info->status.status_driver_data;
5909 }
5910
rtw89_read8(struct rtw89_dev * rtwdev,u32 addr)5911 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr)
5912 {
5913 return rtwdev->hci.ops->read8(rtwdev, addr);
5914 }
5915
rtw89_read16(struct rtw89_dev * rtwdev,u32 addr)5916 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr)
5917 {
5918 return rtwdev->hci.ops->read16(rtwdev, addr);
5919 }
5920
rtw89_read32(struct rtw89_dev * rtwdev,u32 addr)5921 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr)
5922 {
5923 return rtwdev->hci.ops->read32(rtwdev, addr);
5924 }
5925
rtw89_write8(struct rtw89_dev * rtwdev,u32 addr,u8 data)5926 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data)
5927 {
5928 rtwdev->hci.ops->write8(rtwdev, addr, data);
5929 }
5930
rtw89_write16(struct rtw89_dev * rtwdev,u32 addr,u16 data)5931 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data)
5932 {
5933 rtwdev->hci.ops->write16(rtwdev, addr, data);
5934 }
5935
rtw89_write32(struct rtw89_dev * rtwdev,u32 addr,u32 data)5936 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data)
5937 {
5938 rtwdev->hci.ops->write32(rtwdev, addr, data);
5939 }
5940
5941 static inline void
rtw89_write8_set(struct rtw89_dev * rtwdev,u32 addr,u8 bit)5942 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
5943 {
5944 u8 val;
5945
5946 val = rtw89_read8(rtwdev, addr);
5947 rtw89_write8(rtwdev, addr, val | bit);
5948 }
5949
5950 static inline void
rtw89_write16_set(struct rtw89_dev * rtwdev,u32 addr,u16 bit)5951 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
5952 {
5953 u16 val;
5954
5955 val = rtw89_read16(rtwdev, addr);
5956 rtw89_write16(rtwdev, addr, val | bit);
5957 }
5958
5959 static inline void
rtw89_write32_set(struct rtw89_dev * rtwdev,u32 addr,u32 bit)5960 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
5961 {
5962 u32 val;
5963
5964 val = rtw89_read32(rtwdev, addr);
5965 rtw89_write32(rtwdev, addr, val | bit);
5966 }
5967
5968 static inline void
rtw89_write8_clr(struct rtw89_dev * rtwdev,u32 addr,u8 bit)5969 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
5970 {
5971 u8 val;
5972
5973 val = rtw89_read8(rtwdev, addr);
5974 rtw89_write8(rtwdev, addr, val & ~bit);
5975 }
5976
5977 static inline void
rtw89_write16_clr(struct rtw89_dev * rtwdev,u32 addr,u16 bit)5978 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
5979 {
5980 u16 val;
5981
5982 val = rtw89_read16(rtwdev, addr);
5983 rtw89_write16(rtwdev, addr, val & ~bit);
5984 }
5985
5986 static inline void
rtw89_write32_clr(struct rtw89_dev * rtwdev,u32 addr,u32 bit)5987 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
5988 {
5989 u32 val;
5990
5991 val = rtw89_read32(rtwdev, addr);
5992 rtw89_write32(rtwdev, addr, val & ~bit);
5993 }
5994
5995 static inline u32
rtw89_read32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)5996 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
5997 {
5998 u32 shift = __ffs(mask);
5999 u32 orig;
6000 u32 ret;
6001
6002 orig = rtw89_read32(rtwdev, addr);
6003 ret = (orig & mask) >> shift;
6004
6005 return ret;
6006 }
6007
6008 static inline u16
rtw89_read16_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)6009 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
6010 {
6011 u32 shift = __ffs(mask);
6012 u32 orig;
6013 u32 ret;
6014
6015 orig = rtw89_read16(rtwdev, addr);
6016 ret = (orig & mask) >> shift;
6017
6018 return ret;
6019 }
6020
6021 static inline u8
rtw89_read8_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)6022 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
6023 {
6024 u32 shift = __ffs(mask);
6025 u32 orig;
6026 u32 ret;
6027
6028 orig = rtw89_read8(rtwdev, addr);
6029 ret = (orig & mask) >> shift;
6030
6031 return ret;
6032 }
6033
6034 static inline void
rtw89_write32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 data)6035 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data)
6036 {
6037 u32 shift = __ffs(mask);
6038 u32 orig;
6039 u32 set;
6040
6041 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr);
6042
6043 orig = rtw89_read32(rtwdev, addr);
6044 set = (orig & ~mask) | ((data << shift) & mask);
6045 rtw89_write32(rtwdev, addr, set);
6046 }
6047
6048 static inline void
rtw89_write16_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u16 data)6049 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data)
6050 {
6051 u32 shift;
6052 u16 orig, set;
6053
6054 mask &= 0xffff;
6055 shift = __ffs(mask);
6056
6057 orig = rtw89_read16(rtwdev, addr);
6058 set = (orig & ~mask) | ((data << shift) & mask);
6059 rtw89_write16(rtwdev, addr, set);
6060 }
6061
6062 static inline void
rtw89_write8_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u8 data)6063 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data)
6064 {
6065 u32 shift;
6066 u8 orig, set;
6067
6068 mask &= 0xff;
6069 shift = __ffs(mask);
6070
6071 orig = rtw89_read8(rtwdev, addr);
6072 set = (orig & ~mask) | ((data << shift) & mask);
6073 rtw89_write8(rtwdev, addr, set);
6074 }
6075
6076 static inline u32
rtw89_read_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)6077 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
6078 u32 addr, u32 mask)
6079 {
6080 u32 val;
6081
6082 mutex_lock(&rtwdev->rf_mutex);
6083 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask);
6084 mutex_unlock(&rtwdev->rf_mutex);
6085
6086 return val;
6087 }
6088
6089 static inline void
rtw89_write_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)6090 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
6091 u32 addr, u32 mask, u32 data)
6092 {
6093 mutex_lock(&rtwdev->rf_mutex);
6094 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data);
6095 mutex_unlock(&rtwdev->rf_mutex);
6096 }
6097
rtw89_txq_to_txq(struct rtw89_txq * rtwtxq)6098 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq)
6099 {
6100 void *p = rtwtxq;
6101
6102 return container_of(p, struct ieee80211_txq, drv_priv);
6103 }
6104
rtw89_core_txq_init(struct rtw89_dev * rtwdev,struct ieee80211_txq * txq)6105 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev,
6106 struct ieee80211_txq *txq)
6107 {
6108 struct rtw89_txq *rtwtxq;
6109
6110 if (!txq)
6111 return;
6112
6113 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
6114 INIT_LIST_HEAD(&rtwtxq->list);
6115 }
6116
rtwvif_to_vif(struct rtw89_vif * rtwvif)6117 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif)
6118 {
6119 void *p = rtwvif;
6120
6121 return container_of(p, struct ieee80211_vif, drv_priv);
6122 }
6123
rtwvif_to_vif_safe(struct rtw89_vif * rtwvif)6124 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif)
6125 {
6126 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL;
6127 }
6128
6129 static inline
rtwvif_link_to_vif(struct rtw89_vif_link * rtwvif_link)6130 struct ieee80211_vif *rtwvif_link_to_vif(struct rtw89_vif_link *rtwvif_link)
6131 {
6132 return rtwvif_to_vif(rtwvif_link->rtwvif);
6133 }
6134
6135 static inline
rtwvif_link_to_vif_safe(struct rtw89_vif_link * rtwvif_link)6136 struct ieee80211_vif *rtwvif_link_to_vif_safe(struct rtw89_vif_link *rtwvif_link)
6137 {
6138 return rtwvif_link ? rtwvif_link_to_vif(rtwvif_link) : NULL;
6139 }
6140
vif_to_rtwvif(struct ieee80211_vif * vif)6141 static inline struct rtw89_vif *vif_to_rtwvif(struct ieee80211_vif *vif)
6142 {
6143 return (struct rtw89_vif *)vif->drv_priv;
6144 }
6145
vif_to_rtwvif_safe(struct ieee80211_vif * vif)6146 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif)
6147 {
6148 return vif ? vif_to_rtwvif(vif) : NULL;
6149 }
6150
rtwsta_to_sta(struct rtw89_sta * rtwsta)6151 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta)
6152 {
6153 void *p = rtwsta;
6154
6155 return container_of(p, struct ieee80211_sta, drv_priv);
6156 }
6157
rtwsta_to_sta_safe(struct rtw89_sta * rtwsta)6158 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta)
6159 {
6160 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL;
6161 }
6162
6163 static inline
rtwsta_link_to_sta(struct rtw89_sta_link * rtwsta_link)6164 struct ieee80211_sta *rtwsta_link_to_sta(struct rtw89_sta_link *rtwsta_link)
6165 {
6166 return rtwsta_to_sta(rtwsta_link->rtwsta);
6167 }
6168
6169 static inline
rtwsta_link_to_sta_safe(struct rtw89_sta_link * rtwsta_link)6170 struct ieee80211_sta *rtwsta_link_to_sta_safe(struct rtw89_sta_link *rtwsta_link)
6171 {
6172 return rtwsta_link ? rtwsta_link_to_sta(rtwsta_link) : NULL;
6173 }
6174
sta_to_rtwsta(struct ieee80211_sta * sta)6175 static inline struct rtw89_sta *sta_to_rtwsta(struct ieee80211_sta *sta)
6176 {
6177 return (struct rtw89_sta *)sta->drv_priv;
6178 }
6179
sta_to_rtwsta_safe(struct ieee80211_sta * sta)6180 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta)
6181 {
6182 return sta ? sta_to_rtwsta(sta) : NULL;
6183 }
6184
6185 static inline struct ieee80211_bss_conf *
__rtw89_vif_rcu_dereference_link(struct rtw89_vif_link * rtwvif_link,bool * nolink)6186 __rtw89_vif_rcu_dereference_link(struct rtw89_vif_link *rtwvif_link, bool *nolink)
6187 {
6188 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
6189 struct ieee80211_bss_conf *bss_conf;
6190
6191 bss_conf = rcu_dereference(vif->link_conf[rtwvif_link->link_id]);
6192 if (unlikely(!bss_conf)) {
6193 *nolink = true;
6194 return &vif->bss_conf;
6195 }
6196
6197 *nolink = false;
6198 return bss_conf;
6199 }
6200
6201 #define rtw89_vif_rcu_dereference_link(rtwvif_link, assert) \
6202 ({ \
6203 typeof(rtwvif_link) p = rtwvif_link; \
6204 struct ieee80211_bss_conf *bss_conf; \
6205 bool nolink; \
6206 \
6207 bss_conf = __rtw89_vif_rcu_dereference_link(p, &nolink); \
6208 if (unlikely(nolink) && (assert)) \
6209 rtw89_err(p->rtwvif->rtwdev, \
6210 "%s: cannot find exact bss_conf for link_id %u\n",\
6211 __func__, p->link_id); \
6212 bss_conf; \
6213 })
6214
6215 static inline struct ieee80211_link_sta *
__rtw89_sta_rcu_dereference_link(struct rtw89_sta_link * rtwsta_link,bool * nolink)6216 __rtw89_sta_rcu_dereference_link(struct rtw89_sta_link *rtwsta_link, bool *nolink)
6217 {
6218 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
6219 struct ieee80211_link_sta *link_sta;
6220
6221 link_sta = rcu_dereference(sta->link[rtwsta_link->link_id]);
6222 if (unlikely(!link_sta)) {
6223 *nolink = true;
6224 return &sta->deflink;
6225 }
6226
6227 *nolink = false;
6228 return link_sta;
6229 }
6230
6231 #define rtw89_sta_rcu_dereference_link(rtwsta_link, assert) \
6232 ({ \
6233 typeof(rtwsta_link) p = rtwsta_link; \
6234 struct ieee80211_link_sta *link_sta; \
6235 bool nolink; \
6236 \
6237 link_sta = __rtw89_sta_rcu_dereference_link(p, &nolink); \
6238 if (unlikely(nolink) && (assert)) \
6239 rtw89_err(p->rtwsta->rtwdev, \
6240 "%s: cannot find exact link_sta for link_id %u\n",\
6241 __func__, p->link_id); \
6242 link_sta; \
6243 })
6244
rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)6245 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)
6246 {
6247 if (hw_bw == RTW89_CHANNEL_WIDTH_160)
6248 return RATE_INFO_BW_160;
6249 else if (hw_bw == RTW89_CHANNEL_WIDTH_80)
6250 return RATE_INFO_BW_80;
6251 else if (hw_bw == RTW89_CHANNEL_WIDTH_40)
6252 return RATE_INFO_BW_40;
6253 else
6254 return RATE_INFO_BW_20;
6255 }
6256
6257 static inline
rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)6258 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)
6259 {
6260 switch (hw_band) {
6261 default:
6262 case RTW89_BAND_2G:
6263 return NL80211_BAND_2GHZ;
6264 case RTW89_BAND_5G:
6265 return NL80211_BAND_5GHZ;
6266 case RTW89_BAND_6G:
6267 return NL80211_BAND_6GHZ;
6268 }
6269 }
6270
6271 static inline
rtw89_nl80211_to_hw_band(enum nl80211_band nl_band)6272 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band)
6273 {
6274 switch (nl_band) {
6275 default:
6276 case NL80211_BAND_2GHZ:
6277 return RTW89_BAND_2G;
6278 case NL80211_BAND_5GHZ:
6279 return RTW89_BAND_5G;
6280 case NL80211_BAND_6GHZ:
6281 return RTW89_BAND_6G;
6282 }
6283 }
6284
6285 static inline
nl_to_rtw89_bandwidth(enum nl80211_chan_width width)6286 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width)
6287 {
6288 switch (width) {
6289 default:
6290 WARN(1, "Not support bandwidth %d\n", width);
6291 fallthrough;
6292 case NL80211_CHAN_WIDTH_20_NOHT:
6293 case NL80211_CHAN_WIDTH_20:
6294 return RTW89_CHANNEL_WIDTH_20;
6295 case NL80211_CHAN_WIDTH_40:
6296 return RTW89_CHANNEL_WIDTH_40;
6297 case NL80211_CHAN_WIDTH_80:
6298 return RTW89_CHANNEL_WIDTH_80;
6299 case NL80211_CHAN_WIDTH_160:
6300 return RTW89_CHANNEL_WIDTH_160;
6301 }
6302 }
6303
6304 static inline
rtw89_he_rua_to_ru_alloc(u16 rua)6305 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua)
6306 {
6307 switch (rua) {
6308 default:
6309 WARN(1, "Invalid RU allocation: %d\n", rua);
6310 fallthrough;
6311 case 0 ... 36:
6312 return NL80211_RATE_INFO_HE_RU_ALLOC_26;
6313 case 37 ... 52:
6314 return NL80211_RATE_INFO_HE_RU_ALLOC_52;
6315 case 53 ... 60:
6316 return NL80211_RATE_INFO_HE_RU_ALLOC_106;
6317 case 61 ... 64:
6318 return NL80211_RATE_INFO_HE_RU_ALLOC_242;
6319 case 65 ... 66:
6320 return NL80211_RATE_INFO_HE_RU_ALLOC_484;
6321 case 67:
6322 return NL80211_RATE_INFO_HE_RU_ALLOC_996;
6323 case 68:
6324 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996;
6325 }
6326 }
6327
6328 static inline
rtw89_get_addr_cam_of(struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)6329 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif_link *rtwvif_link,
6330 struct rtw89_sta_link *rtwsta_link)
6331 {
6332 if (rtwsta_link) {
6333 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
6334
6335 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls)
6336 return &rtwsta_link->addr_cam;
6337 }
6338 return &rtwvif_link->addr_cam;
6339 }
6340
6341 static inline
rtw89_get_bssid_cam_of(struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)6342 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif_link *rtwvif_link,
6343 struct rtw89_sta_link *rtwsta_link)
6344 {
6345 if (rtwsta_link) {
6346 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
6347
6348 if (sta->tdls)
6349 return &rtwsta_link->bssid_cam;
6350 }
6351 return &rtwvif_link->bssid_cam;
6352 }
6353
6354 static inline
rtw89_chip_set_channel_prepare(struct rtw89_dev * rtwdev,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)6355 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev,
6356 struct rtw89_channel_help_params *p,
6357 const struct rtw89_chan *chan,
6358 enum rtw89_mac_idx mac_idx,
6359 enum rtw89_phy_idx phy_idx)
6360 {
6361 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan,
6362 mac_idx, phy_idx);
6363 }
6364
6365 static inline
rtw89_chip_set_channel_done(struct rtw89_dev * rtwdev,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)6366 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev,
6367 struct rtw89_channel_help_params *p,
6368 const struct rtw89_chan *chan,
6369 enum rtw89_mac_idx mac_idx,
6370 enum rtw89_phy_idx phy_idx)
6371 {
6372 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan,
6373 mac_idx, phy_idx);
6374 }
6375
6376 static inline
rtw89_chandef_get(struct rtw89_dev * rtwdev,enum rtw89_chanctx_idx idx)6377 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev,
6378 enum rtw89_chanctx_idx idx)
6379 {
6380 struct rtw89_hal *hal = &rtwdev->hal;
6381 enum rtw89_chanctx_idx roc_idx = atomic_read(&hal->roc_chanctx_idx);
6382
6383 if (roc_idx == idx)
6384 return &hal->roc_chandef;
6385
6386 return &hal->chanctx[idx].chandef;
6387 }
6388
6389 static inline
rtw89_chan_get(struct rtw89_dev * rtwdev,enum rtw89_chanctx_idx idx)6390 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev,
6391 enum rtw89_chanctx_idx idx)
6392 {
6393 struct rtw89_hal *hal = &rtwdev->hal;
6394
6395 return &hal->chanctx[idx].chan;
6396 }
6397
6398 static inline
rtw89_chan_rcd_get(struct rtw89_dev * rtwdev,enum rtw89_chanctx_idx idx)6399 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev,
6400 enum rtw89_chanctx_idx idx)
6401 {
6402 struct rtw89_hal *hal = &rtwdev->hal;
6403
6404 return &hal->chanctx[idx].rcd;
6405 }
6406
6407 static inline
rtw89_chan_rcd_get_by_chan(const struct rtw89_chan * chan)6408 const struct rtw89_chan_rcd *rtw89_chan_rcd_get_by_chan(const struct rtw89_chan *chan)
6409 {
6410 const struct rtw89_chanctx *chanctx =
6411 container_of_const(chan, struct rtw89_chanctx, chan);
6412
6413 return &chanctx->rcd;
6414 }
6415
6416 static inline
rtw89_scan_chan_get(struct rtw89_dev * rtwdev)6417 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev)
6418 {
6419 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif;
6420
6421 if (rtwvif_link)
6422 return rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx);
6423 else
6424 return rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
6425 }
6426
rtw89_chip_fem_setup(struct rtw89_dev * rtwdev)6427 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev)
6428 {
6429 const struct rtw89_chip_info *chip = rtwdev->chip;
6430
6431 if (chip->ops->fem_setup)
6432 chip->ops->fem_setup(rtwdev);
6433 }
6434
rtw89_chip_rfe_gpio(struct rtw89_dev * rtwdev)6435 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev)
6436 {
6437 const struct rtw89_chip_info *chip = rtwdev->chip;
6438
6439 if (chip->ops->rfe_gpio)
6440 chip->ops->rfe_gpio(rtwdev);
6441 }
6442
rtw89_chip_rfk_hw_init(struct rtw89_dev * rtwdev)6443 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev)
6444 {
6445 const struct rtw89_chip_info *chip = rtwdev->chip;
6446
6447 if (chip->ops->rfk_hw_init)
6448 chip->ops->rfk_hw_init(rtwdev);
6449 }
6450
6451 static inline
rtw89_chip_bb_preinit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)6452 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
6453 {
6454 const struct rtw89_chip_info *chip = rtwdev->chip;
6455
6456 if (chip->ops->bb_preinit)
6457 chip->ops->bb_preinit(rtwdev, phy_idx);
6458 }
6459
6460 static inline
rtw89_chip_bb_postinit(struct rtw89_dev * rtwdev)6461 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev)
6462 {
6463 const struct rtw89_chip_info *chip = rtwdev->chip;
6464
6465 if (!chip->ops->bb_postinit)
6466 return;
6467
6468 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0);
6469
6470 if (rtwdev->dbcc_en)
6471 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1);
6472 }
6473
rtw89_chip_bb_sethw(struct rtw89_dev * rtwdev)6474 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev)
6475 {
6476 const struct rtw89_chip_info *chip = rtwdev->chip;
6477
6478 if (chip->ops->bb_sethw)
6479 chip->ops->bb_sethw(rtwdev);
6480 }
6481
rtw89_chip_rfk_init(struct rtw89_dev * rtwdev)6482 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev)
6483 {
6484 const struct rtw89_chip_info *chip = rtwdev->chip;
6485
6486 if (chip->ops->rfk_init)
6487 chip->ops->rfk_init(rtwdev);
6488 }
6489
rtw89_chip_rfk_init_late(struct rtw89_dev * rtwdev)6490 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev)
6491 {
6492 const struct rtw89_chip_info *chip = rtwdev->chip;
6493
6494 if (chip->ops->rfk_init_late)
6495 chip->ops->rfk_init_late(rtwdev);
6496 }
6497
rtw89_chip_rfk_channel(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)6498 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev,
6499 struct rtw89_vif_link *rtwvif_link)
6500 {
6501 const struct rtw89_chip_info *chip = rtwdev->chip;
6502
6503 if (chip->ops->rfk_channel)
6504 chip->ops->rfk_channel(rtwdev, rtwvif_link);
6505 }
6506
rtw89_chip_rfk_band_changed(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan)6507 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev,
6508 enum rtw89_phy_idx phy_idx,
6509 const struct rtw89_chan *chan)
6510 {
6511 const struct rtw89_chip_info *chip = rtwdev->chip;
6512
6513 if (chip->ops->rfk_band_changed)
6514 chip->ops->rfk_band_changed(rtwdev, phy_idx, chan);
6515 }
6516
rtw89_chip_rfk_scan(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool start)6517 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev,
6518 struct rtw89_vif_link *rtwvif_link, bool start)
6519 {
6520 const struct rtw89_chip_info *chip = rtwdev->chip;
6521
6522 if (chip->ops->rfk_scan)
6523 chip->ops->rfk_scan(rtwdev, rtwvif_link, start);
6524 }
6525
rtw89_chip_rfk_track(struct rtw89_dev * rtwdev)6526 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev)
6527 {
6528 const struct rtw89_chip_info *chip = rtwdev->chip;
6529
6530 if (chip->ops->rfk_track)
6531 chip->ops->rfk_track(rtwdev);
6532 }
6533
rtw89_chip_set_txpwr_ctrl(struct rtw89_dev * rtwdev)6534 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev)
6535 {
6536 const struct rtw89_chip_info *chip = rtwdev->chip;
6537
6538 if (chip->ops->set_txpwr_ctrl)
6539 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0);
6540 }
6541
rtw89_chip_power_trim(struct rtw89_dev * rtwdev)6542 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev)
6543 {
6544 const struct rtw89_chip_info *chip = rtwdev->chip;
6545
6546 if (chip->ops->power_trim)
6547 chip->ops->power_trim(rtwdev);
6548 }
6549
rtw89_chip_init_txpwr_unit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)6550 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev,
6551 enum rtw89_phy_idx phy_idx)
6552 {
6553 const struct rtw89_chip_info *chip = rtwdev->chip;
6554
6555 if (chip->ops->init_txpwr_unit)
6556 chip->ops->init_txpwr_unit(rtwdev, phy_idx);
6557 }
6558
rtw89_chip_get_thermal(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path)6559 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev,
6560 enum rtw89_rf_path rf_path)
6561 {
6562 const struct rtw89_chip_info *chip = rtwdev->chip;
6563
6564 if (!chip->ops->get_thermal)
6565 return 0x10;
6566
6567 return chip->ops->get_thermal(rtwdev, rf_path);
6568 }
6569
rtw89_chip_query_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)6570 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev,
6571 struct rtw89_rx_phy_ppdu *phy_ppdu,
6572 struct ieee80211_rx_status *status)
6573 {
6574 const struct rtw89_chip_info *chip = rtwdev->chip;
6575
6576 if (chip->ops->query_ppdu)
6577 chip->ops->query_ppdu(rtwdev, phy_ppdu, status);
6578 }
6579
rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)6580 static inline void rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev *rtwdev,
6581 struct rtw89_rx_phy_ppdu *phy_ppdu)
6582 {
6583 const struct rtw89_chip_info *chip = rtwdev->chip;
6584
6585 if (chip->ops->convert_rpl_to_rssi)
6586 chip->ops->convert_rpl_to_rssi(rtwdev, phy_ppdu);
6587 }
6588
rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)6589 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
6590 enum rtw89_phy_idx phy_idx)
6591 {
6592 const struct rtw89_chip_info *chip = rtwdev->chip;
6593
6594 if (chip->ops->ctrl_nbtg_bt_tx)
6595 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx);
6596 }
6597
rtw89_chip_cfg_txrx_path(struct rtw89_dev * rtwdev)6598 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev)
6599 {
6600 const struct rtw89_chip_info *chip = rtwdev->chip;
6601
6602 if (chip->ops->cfg_txrx_path)
6603 chip->ops->cfg_txrx_path(rtwdev);
6604 }
6605
rtw89_chip_digital_pwr_comp(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)6606 static inline void rtw89_chip_digital_pwr_comp(struct rtw89_dev *rtwdev,
6607 enum rtw89_phy_idx phy_idx)
6608 {
6609 const struct rtw89_chip_info *chip = rtwdev->chip;
6610
6611 if (chip->ops->digital_pwr_comp)
6612 chip->ops->digital_pwr_comp(rtwdev, phy_idx);
6613 }
6614
rtw89_load_txpwr_table(struct rtw89_dev * rtwdev,const struct rtw89_txpwr_table * tbl)6615 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev,
6616 const struct rtw89_txpwr_table *tbl)
6617 {
6618 tbl->load(rtwdev, tbl);
6619 }
6620
rtw89_regd_get(struct rtw89_dev * rtwdev,u8 band)6621 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band)
6622 {
6623 const struct rtw89_regd *regd = rtwdev->regulatory.regd;
6624
6625 return regd->txpwr_regd[band];
6626 }
6627
rtw89_ctrl_btg_bt_rx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)6628 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
6629 enum rtw89_phy_idx phy_idx)
6630 {
6631 const struct rtw89_chip_info *chip = rtwdev->chip;
6632
6633 if (chip->ops->ctrl_btg_bt_rx)
6634 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx);
6635 }
6636
6637 static inline
rtw89_chip_query_rxdesc(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)6638 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev,
6639 struct rtw89_rx_desc_info *desc_info,
6640 u8 *data, u32 data_offset)
6641 {
6642 const struct rtw89_chip_info *chip = rtwdev->chip;
6643
6644 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset);
6645 }
6646
6647 static inline
rtw89_chip_fill_txdesc(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)6648 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev,
6649 struct rtw89_tx_desc_info *desc_info,
6650 void *txdesc)
6651 {
6652 const struct rtw89_chip_info *chip = rtwdev->chip;
6653
6654 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc);
6655 }
6656
6657 static inline
rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)6658 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev,
6659 struct rtw89_tx_desc_info *desc_info,
6660 void *txdesc)
6661 {
6662 const struct rtw89_chip_info *chip = rtwdev->chip;
6663
6664 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc);
6665 }
6666
6667 static inline
rtw89_chip_mac_cfg_gnt(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex_gnt * gnt_cfg)6668 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev,
6669 const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
6670 {
6671 const struct rtw89_chip_info *chip = rtwdev->chip;
6672
6673 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg);
6674 }
6675
rtw89_chip_cfg_ctrl_path(struct rtw89_dev * rtwdev,bool wl)6676 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)
6677 {
6678 const struct rtw89_chip_info *chip = rtwdev->chip;
6679
6680 chip->ops->cfg_ctrl_path(rtwdev, wl);
6681 }
6682
6683 static inline
rtw89_chip_stop_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 * tx_en,enum rtw89_sch_tx_sel sel)6684 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
6685 u32 *tx_en, enum rtw89_sch_tx_sel sel)
6686 {
6687 const struct rtw89_chip_info *chip = rtwdev->chip;
6688
6689 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel);
6690 }
6691
6692 static inline
rtw89_chip_resume_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 tx_en)6693 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
6694 {
6695 const struct rtw89_chip_info *chip = rtwdev->chip;
6696
6697 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en);
6698 }
6699
6700 static inline
rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)6701 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev,
6702 struct rtw89_vif_link *rtwvif_link,
6703 struct rtw89_sta_link *rtwsta_link)
6704 {
6705 const struct rtw89_chip_info *chip = rtwdev->chip;
6706
6707 if (!chip->ops->h2c_dctl_sec_cam)
6708 return 0;
6709 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif_link, rtwsta_link);
6710 }
6711
get_hdr_bssid(struct ieee80211_hdr * hdr)6712 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr)
6713 {
6714 __le16 fc = hdr->frame_control;
6715
6716 if (ieee80211_has_tods(fc))
6717 return hdr->addr1;
6718 else if (ieee80211_has_fromds(fc))
6719 return hdr->addr2;
6720 else
6721 return hdr->addr3;
6722 }
6723
6724 static inline
rtw89_sta_has_beamformer_cap(struct ieee80211_link_sta * link_sta)6725 bool rtw89_sta_has_beamformer_cap(struct ieee80211_link_sta *link_sta)
6726 {
6727 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||
6728 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) ||
6729 (link_sta->he_cap.he_cap_elem.phy_cap_info[3] &
6730 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) ||
6731 (link_sta->he_cap.he_cap_elem.phy_cap_info[4] &
6732 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER))
6733 return true;
6734 return false;
6735 }
6736
rtw89_fw_suit_get(struct rtw89_dev * rtwdev,enum rtw89_fw_type type)6737 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev,
6738 enum rtw89_fw_type type)
6739 {
6740 struct rtw89_fw_info *fw_info = &rtwdev->fw;
6741
6742 switch (type) {
6743 case RTW89_FW_WOWLAN:
6744 return &fw_info->wowlan;
6745 case RTW89_FW_LOGFMT:
6746 return &fw_info->log.suit;
6747 case RTW89_FW_BBMCU0:
6748 return &fw_info->bbmcu0;
6749 case RTW89_FW_BBMCU1:
6750 return &fw_info->bbmcu1;
6751 default:
6752 break;
6753 }
6754
6755 return &fw_info->normal;
6756 }
6757
rtw89_alloc_skb_for_rx(struct rtw89_dev * rtwdev,unsigned int length)6758 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev,
6759 unsigned int length)
6760 {
6761 struct sk_buff *skb;
6762
6763 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) {
6764 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM);
6765 if (!skb)
6766 return NULL;
6767
6768 skb_reserve(skb, RTW89_RADIOTAP_ROOM);
6769 return skb;
6770 }
6771
6772 return dev_alloc_skb(length);
6773 }
6774
rtw89_core_tx_wait_complete(struct rtw89_dev * rtwdev,struct rtw89_tx_skb_data * skb_data,bool tx_done)6775 static inline bool rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev,
6776 struct rtw89_tx_skb_data *skb_data,
6777 bool tx_done)
6778 {
6779 struct rtw89_tx_wait_info *wait;
6780 bool ret = false;
6781
6782 rcu_read_lock();
6783
6784 wait = rcu_dereference(skb_data->wait);
6785 if (!wait)
6786 goto out;
6787
6788 ret = true;
6789 wait->tx_done = tx_done;
6790 /* Don't access skb anymore after completion */
6791 complete_all(&wait->completion);
6792
6793 out:
6794 rcu_read_unlock();
6795 return ret;
6796 }
6797
rtw89_is_mlo_1_1(struct rtw89_dev * rtwdev)6798 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev)
6799 {
6800 switch (rtwdev->mlo_dbcc_mode) {
6801 case MLO_1_PLUS_1_1RF:
6802 case MLO_1_PLUS_1_2RF:
6803 case DBCC_LEGACY:
6804 return true;
6805 default:
6806 return false;
6807 }
6808 }
6809
rtw89_is_rtl885xb(struct rtw89_dev * rtwdev)6810 static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev)
6811 {
6812 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
6813
6814 if (chip_id == RTL8852B || chip_id == RTL8851B || chip_id == RTL8852BT)
6815 return true;
6816
6817 return false;
6818 }
6819
6820 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
6821 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel);
6822 int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
6823 struct sk_buff *skb, bool fwdl);
6824 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel);
6825 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
6826 int qsel, unsigned int timeout);
6827 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
6828 struct rtw89_tx_desc_info *desc_info,
6829 void *txdesc);
6830 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
6831 struct rtw89_tx_desc_info *desc_info,
6832 void *txdesc);
6833 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev,
6834 struct rtw89_tx_desc_info *desc_info,
6835 void *txdesc);
6836 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
6837 struct rtw89_tx_desc_info *desc_info,
6838 void *txdesc);
6839 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev,
6840 struct rtw89_tx_desc_info *desc_info,
6841 void *txdesc);
6842 void rtw89_core_rx(struct rtw89_dev *rtwdev,
6843 struct rtw89_rx_desc_info *desc_info,
6844 struct sk_buff *skb);
6845 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
6846 struct rtw89_rx_desc_info *desc_info,
6847 u8 *data, u32 data_offset);
6848 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev,
6849 struct rtw89_rx_desc_info *desc_info,
6850 u8 *data, u32 data_offset);
6851 void rtw89_core_napi_start(struct rtw89_dev *rtwdev);
6852 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev);
6853 int rtw89_core_napi_init(struct rtw89_dev *rtwdev);
6854 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev);
6855 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev,
6856 struct rtw89_vif_link *rtwvif_link,
6857 struct rtw89_sta_link *rtwsta_link);
6858 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev,
6859 struct rtw89_vif_link *rtwvif_link,
6860 struct rtw89_sta_link *rtwsta_link);
6861 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev,
6862 struct rtw89_vif_link *rtwvif_link,
6863 struct rtw89_sta_link *rtwsta_link);
6864 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev,
6865 struct rtw89_vif_link *rtwvif_link,
6866 struct rtw89_sta_link *rtwsta_link);
6867 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev,
6868 struct rtw89_vif_link *rtwvif_link,
6869 struct rtw89_sta_link *rtwsta_link);
6870 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
6871 struct ieee80211_sta *sta,
6872 struct cfg80211_tid_config *tid_config);
6873 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force);
6874 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks);
6875 int rtw89_core_init(struct rtw89_dev *rtwdev);
6876 void rtw89_core_deinit(struct rtw89_dev *rtwdev);
6877 int rtw89_core_register(struct rtw89_dev *rtwdev);
6878 void rtw89_core_unregister(struct rtw89_dev *rtwdev);
6879 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device,
6880 u32 bus_data_size,
6881 const struct rtw89_chip_info *chip);
6882 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev);
6883 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev);
6884 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id);
6885 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
6886 u8 mac_id, u8 port);
6887 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
6888 struct rtw89_sta *rtwsta, u8 mac_id);
6889 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif,
6890 unsigned int link_id);
6891 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id);
6892 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta,
6893 unsigned int link_id);
6894 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id);
6895 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev);
6896 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef);
6897 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef,
6898 struct rtw89_chan *chan);
6899 int rtw89_set_channel(struct rtw89_dev *rtwdev);
6900 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size);
6901 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit);
6902 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits);
6903 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev,
6904 struct rtw89_sta_link *rtwsta_link, u8 tid,
6905 u8 *cam_idx);
6906 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev,
6907 struct rtw89_sta_link *rtwsta_link, u8 tid,
6908 u8 *cam_idx);
6909 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev,
6910 struct ieee80211_sta *sta);
6911 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev,
6912 struct ieee80211_sta *sta);
6913 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev,
6914 struct ieee80211_sta *sta);
6915 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc);
6916 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev);
6917 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
6918 struct rtw89_vif_link *rtwvif_link);
6919 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate);
6920 int rtw89_regd_setup(struct rtw89_dev *rtwdev);
6921 int rtw89_regd_init(struct rtw89_dev *rtwdev,
6922 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request));
6923 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request);
6924 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
6925 struct rtw89_traffic_stats *stats);
6926 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond);
6927 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
6928 const struct rtw89_completion_data *data);
6929 int rtw89_core_start(struct rtw89_dev *rtwdev);
6930 void rtw89_core_stop(struct rtw89_dev *rtwdev);
6931 void rtw89_core_update_beacon_work(struct work_struct *work);
6932 void rtw89_roc_work(struct work_struct *work);
6933 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
6934 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
6935 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
6936 const u8 *mac_addr, bool hw_scan);
6937 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
6938 struct rtw89_vif_link *rtwvif_link, bool hw_scan);
6939 int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
6940 bool active);
6941 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev,
6942 struct rtw89_vif_link *rtwvif_link,
6943 struct ieee80211_bss_conf *bss_conf);
6944 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event);
6945
6946 #endif
6947