1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 - 2022 Beijing WangXun Technology Co., Ltd. */
3
4 #include <linux/etherdevice.h>
5 #include <net/ip6_checksum.h>
6 #include <net/page_pool/helpers.h>
7 #include <net/inet_ecn.h>
8 #include <linux/iopoll.h>
9 #include <linux/sctp.h>
10 #include <linux/pci.h>
11 #include <net/tcp.h>
12 #include <net/ip.h>
13
14 #include "wx_type.h"
15 #include "wx_lib.h"
16 #include "wx_hw.h"
17
18 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
19 static struct wx_dec_ptype wx_ptype_lookup[256] = {
20 /* L2: mac */
21 [0x11] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
22 [0x12] = WX_PTT(L2, NONE, NONE, NONE, TS, PAY2),
23 [0x13] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
24 [0x14] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
25 [0x15] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE),
26 [0x16] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
27 [0x17] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE),
28
29 /* L2: ethertype filter */
30 [0x18 ... 0x1F] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE),
31
32 /* L3: ip non-tunnel */
33 [0x21] = WX_PTT(IP, FGV4, NONE, NONE, NONE, PAY3),
34 [0x22] = WX_PTT(IP, IPV4, NONE, NONE, NONE, PAY3),
35 [0x23] = WX_PTT(IP, IPV4, NONE, NONE, UDP, PAY4),
36 [0x24] = WX_PTT(IP, IPV4, NONE, NONE, TCP, PAY4),
37 [0x25] = WX_PTT(IP, IPV4, NONE, NONE, SCTP, PAY4),
38 [0x29] = WX_PTT(IP, FGV6, NONE, NONE, NONE, PAY3),
39 [0x2A] = WX_PTT(IP, IPV6, NONE, NONE, NONE, PAY3),
40 [0x2B] = WX_PTT(IP, IPV6, NONE, NONE, UDP, PAY3),
41 [0x2C] = WX_PTT(IP, IPV6, NONE, NONE, TCP, PAY4),
42 [0x2D] = WX_PTT(IP, IPV6, NONE, NONE, SCTP, PAY4),
43
44 /* L2: fcoe */
45 [0x30 ... 0x34] = WX_PTT(FCOE, NONE, NONE, NONE, NONE, PAY3),
46 [0x38 ... 0x3C] = WX_PTT(FCOE, NONE, NONE, NONE, NONE, PAY3),
47
48 /* IPv4 --> IPv4/IPv6 */
49 [0x81] = WX_PTT(IP, IPV4, IPIP, FGV4, NONE, PAY3),
50 [0x82] = WX_PTT(IP, IPV4, IPIP, IPV4, NONE, PAY3),
51 [0x83] = WX_PTT(IP, IPV4, IPIP, IPV4, UDP, PAY4),
52 [0x84] = WX_PTT(IP, IPV4, IPIP, IPV4, TCP, PAY4),
53 [0x85] = WX_PTT(IP, IPV4, IPIP, IPV4, SCTP, PAY4),
54 [0x89] = WX_PTT(IP, IPV4, IPIP, FGV6, NONE, PAY3),
55 [0x8A] = WX_PTT(IP, IPV4, IPIP, IPV6, NONE, PAY3),
56 [0x8B] = WX_PTT(IP, IPV4, IPIP, IPV6, UDP, PAY4),
57 [0x8C] = WX_PTT(IP, IPV4, IPIP, IPV6, TCP, PAY4),
58 [0x8D] = WX_PTT(IP, IPV4, IPIP, IPV6, SCTP, PAY4),
59
60 /* IPv4 --> GRE/NAT --> NONE/IPv4/IPv6 */
61 [0x90] = WX_PTT(IP, IPV4, IG, NONE, NONE, PAY3),
62 [0x91] = WX_PTT(IP, IPV4, IG, FGV4, NONE, PAY3),
63 [0x92] = WX_PTT(IP, IPV4, IG, IPV4, NONE, PAY3),
64 [0x93] = WX_PTT(IP, IPV4, IG, IPV4, UDP, PAY4),
65 [0x94] = WX_PTT(IP, IPV4, IG, IPV4, TCP, PAY4),
66 [0x95] = WX_PTT(IP, IPV4, IG, IPV4, SCTP, PAY4),
67 [0x99] = WX_PTT(IP, IPV4, IG, FGV6, NONE, PAY3),
68 [0x9A] = WX_PTT(IP, IPV4, IG, IPV6, NONE, PAY3),
69 [0x9B] = WX_PTT(IP, IPV4, IG, IPV6, UDP, PAY4),
70 [0x9C] = WX_PTT(IP, IPV4, IG, IPV6, TCP, PAY4),
71 [0x9D] = WX_PTT(IP, IPV4, IG, IPV6, SCTP, PAY4),
72
73 /* IPv4 --> GRE/NAT --> MAC --> NONE/IPv4/IPv6 */
74 [0xA0] = WX_PTT(IP, IPV4, IGM, NONE, NONE, PAY3),
75 [0xA1] = WX_PTT(IP, IPV4, IGM, FGV4, NONE, PAY3),
76 [0xA2] = WX_PTT(IP, IPV4, IGM, IPV4, NONE, PAY3),
77 [0xA3] = WX_PTT(IP, IPV4, IGM, IPV4, UDP, PAY4),
78 [0xA4] = WX_PTT(IP, IPV4, IGM, IPV4, TCP, PAY4),
79 [0xA5] = WX_PTT(IP, IPV4, IGM, IPV4, SCTP, PAY4),
80 [0xA9] = WX_PTT(IP, IPV4, IGM, FGV6, NONE, PAY3),
81 [0xAA] = WX_PTT(IP, IPV4, IGM, IPV6, NONE, PAY3),
82 [0xAB] = WX_PTT(IP, IPV4, IGM, IPV6, UDP, PAY4),
83 [0xAC] = WX_PTT(IP, IPV4, IGM, IPV6, TCP, PAY4),
84 [0xAD] = WX_PTT(IP, IPV4, IGM, IPV6, SCTP, PAY4),
85
86 /* IPv4 --> GRE/NAT --> MAC+VLAN --> NONE/IPv4/IPv6 */
87 [0xB0] = WX_PTT(IP, IPV4, IGMV, NONE, NONE, PAY3),
88 [0xB1] = WX_PTT(IP, IPV4, IGMV, FGV4, NONE, PAY3),
89 [0xB2] = WX_PTT(IP, IPV4, IGMV, IPV4, NONE, PAY3),
90 [0xB3] = WX_PTT(IP, IPV4, IGMV, IPV4, UDP, PAY4),
91 [0xB4] = WX_PTT(IP, IPV4, IGMV, IPV4, TCP, PAY4),
92 [0xB5] = WX_PTT(IP, IPV4, IGMV, IPV4, SCTP, PAY4),
93 [0xB9] = WX_PTT(IP, IPV4, IGMV, FGV6, NONE, PAY3),
94 [0xBA] = WX_PTT(IP, IPV4, IGMV, IPV6, NONE, PAY3),
95 [0xBB] = WX_PTT(IP, IPV4, IGMV, IPV6, UDP, PAY4),
96 [0xBC] = WX_PTT(IP, IPV4, IGMV, IPV6, TCP, PAY4),
97 [0xBD] = WX_PTT(IP, IPV4, IGMV, IPV6, SCTP, PAY4),
98
99 /* IPv6 --> IPv4/IPv6 */
100 [0xC1] = WX_PTT(IP, IPV6, IPIP, FGV4, NONE, PAY3),
101 [0xC2] = WX_PTT(IP, IPV6, IPIP, IPV4, NONE, PAY3),
102 [0xC3] = WX_PTT(IP, IPV6, IPIP, IPV4, UDP, PAY4),
103 [0xC4] = WX_PTT(IP, IPV6, IPIP, IPV4, TCP, PAY4),
104 [0xC5] = WX_PTT(IP, IPV6, IPIP, IPV4, SCTP, PAY4),
105 [0xC9] = WX_PTT(IP, IPV6, IPIP, FGV6, NONE, PAY3),
106 [0xCA] = WX_PTT(IP, IPV6, IPIP, IPV6, NONE, PAY3),
107 [0xCB] = WX_PTT(IP, IPV6, IPIP, IPV6, UDP, PAY4),
108 [0xCC] = WX_PTT(IP, IPV6, IPIP, IPV6, TCP, PAY4),
109 [0xCD] = WX_PTT(IP, IPV6, IPIP, IPV6, SCTP, PAY4),
110
111 /* IPv6 --> GRE/NAT -> NONE/IPv4/IPv6 */
112 [0xD0] = WX_PTT(IP, IPV6, IG, NONE, NONE, PAY3),
113 [0xD1] = WX_PTT(IP, IPV6, IG, FGV4, NONE, PAY3),
114 [0xD2] = WX_PTT(IP, IPV6, IG, IPV4, NONE, PAY3),
115 [0xD3] = WX_PTT(IP, IPV6, IG, IPV4, UDP, PAY4),
116 [0xD4] = WX_PTT(IP, IPV6, IG, IPV4, TCP, PAY4),
117 [0xD5] = WX_PTT(IP, IPV6, IG, IPV4, SCTP, PAY4),
118 [0xD9] = WX_PTT(IP, IPV6, IG, FGV6, NONE, PAY3),
119 [0xDA] = WX_PTT(IP, IPV6, IG, IPV6, NONE, PAY3),
120 [0xDB] = WX_PTT(IP, IPV6, IG, IPV6, UDP, PAY4),
121 [0xDC] = WX_PTT(IP, IPV6, IG, IPV6, TCP, PAY4),
122 [0xDD] = WX_PTT(IP, IPV6, IG, IPV6, SCTP, PAY4),
123
124 /* IPv6 --> GRE/NAT -> MAC -> NONE/IPv4/IPv6 */
125 [0xE0] = WX_PTT(IP, IPV6, IGM, NONE, NONE, PAY3),
126 [0xE1] = WX_PTT(IP, IPV6, IGM, FGV4, NONE, PAY3),
127 [0xE2] = WX_PTT(IP, IPV6, IGM, IPV4, NONE, PAY3),
128 [0xE3] = WX_PTT(IP, IPV6, IGM, IPV4, UDP, PAY4),
129 [0xE4] = WX_PTT(IP, IPV6, IGM, IPV4, TCP, PAY4),
130 [0xE5] = WX_PTT(IP, IPV6, IGM, IPV4, SCTP, PAY4),
131 [0xE9] = WX_PTT(IP, IPV6, IGM, FGV6, NONE, PAY3),
132 [0xEA] = WX_PTT(IP, IPV6, IGM, IPV6, NONE, PAY3),
133 [0xEB] = WX_PTT(IP, IPV6, IGM, IPV6, UDP, PAY4),
134 [0xEC] = WX_PTT(IP, IPV6, IGM, IPV6, TCP, PAY4),
135 [0xED] = WX_PTT(IP, IPV6, IGM, IPV6, SCTP, PAY4),
136
137 /* IPv6 --> GRE/NAT -> MAC--> NONE/IPv */
138 [0xF0] = WX_PTT(IP, IPV6, IGMV, NONE, NONE, PAY3),
139 [0xF1] = WX_PTT(IP, IPV6, IGMV, FGV4, NONE, PAY3),
140 [0xF2] = WX_PTT(IP, IPV6, IGMV, IPV4, NONE, PAY3),
141 [0xF3] = WX_PTT(IP, IPV6, IGMV, IPV4, UDP, PAY4),
142 [0xF4] = WX_PTT(IP, IPV6, IGMV, IPV4, TCP, PAY4),
143 [0xF5] = WX_PTT(IP, IPV6, IGMV, IPV4, SCTP, PAY4),
144 [0xF9] = WX_PTT(IP, IPV6, IGMV, FGV6, NONE, PAY3),
145 [0xFA] = WX_PTT(IP, IPV6, IGMV, IPV6, NONE, PAY3),
146 [0xFB] = WX_PTT(IP, IPV6, IGMV, IPV6, UDP, PAY4),
147 [0xFC] = WX_PTT(IP, IPV6, IGMV, IPV6, TCP, PAY4),
148 [0xFD] = WX_PTT(IP, IPV6, IGMV, IPV6, SCTP, PAY4),
149 };
150
wx_decode_ptype(const u8 ptype)151 struct wx_dec_ptype wx_decode_ptype(const u8 ptype)
152 {
153 return wx_ptype_lookup[ptype];
154 }
155 EXPORT_SYMBOL(wx_decode_ptype);
156
157 /* wx_test_staterr - tests bits in Rx descriptor status and error fields */
wx_test_staterr(union wx_rx_desc * rx_desc,const u32 stat_err_bits)158 static __le32 wx_test_staterr(union wx_rx_desc *rx_desc,
159 const u32 stat_err_bits)
160 {
161 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
162 }
163
wx_dma_sync_frag(struct wx_ring * rx_ring,struct wx_rx_buffer * rx_buffer)164 static void wx_dma_sync_frag(struct wx_ring *rx_ring,
165 struct wx_rx_buffer *rx_buffer)
166 {
167 struct sk_buff *skb = rx_buffer->skb;
168 skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
169
170 dma_sync_single_range_for_cpu(rx_ring->dev,
171 WX_CB(skb)->dma,
172 skb_frag_off(frag),
173 skb_frag_size(frag),
174 DMA_FROM_DEVICE);
175 }
176
wx_get_rx_buffer(struct wx_ring * rx_ring,union wx_rx_desc * rx_desc,struct sk_buff ** skb,int * rx_buffer_pgcnt)177 static struct wx_rx_buffer *wx_get_rx_buffer(struct wx_ring *rx_ring,
178 union wx_rx_desc *rx_desc,
179 struct sk_buff **skb,
180 int *rx_buffer_pgcnt)
181 {
182 struct wx_rx_buffer *rx_buffer;
183 unsigned int size;
184
185 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
186 size = le16_to_cpu(rx_desc->wb.upper.length);
187
188 #if (PAGE_SIZE < 8192)
189 *rx_buffer_pgcnt = page_count(rx_buffer->page);
190 #else
191 *rx_buffer_pgcnt = 0;
192 #endif
193
194 prefetchw(rx_buffer->page);
195 *skb = rx_buffer->skb;
196
197 /* Delay unmapping of the first packet. It carries the header
198 * information, HW may still access the header after the writeback.
199 * Only unmap it when EOP is reached
200 */
201 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_EOP)) {
202 if (!*skb)
203 goto skip_sync;
204 } else {
205 if (*skb)
206 wx_dma_sync_frag(rx_ring, rx_buffer);
207 }
208
209 /* we are reusing so sync this buffer for CPU use */
210 dma_sync_single_range_for_cpu(rx_ring->dev,
211 rx_buffer->dma,
212 rx_buffer->page_offset,
213 size,
214 DMA_FROM_DEVICE);
215 skip_sync:
216 return rx_buffer;
217 }
218
wx_put_rx_buffer(struct wx_ring * rx_ring,struct wx_rx_buffer * rx_buffer,struct sk_buff * skb,int rx_buffer_pgcnt)219 static void wx_put_rx_buffer(struct wx_ring *rx_ring,
220 struct wx_rx_buffer *rx_buffer,
221 struct sk_buff *skb,
222 int rx_buffer_pgcnt)
223 {
224 /* clear contents of rx_buffer */
225 rx_buffer->page = NULL;
226 rx_buffer->skb = NULL;
227 }
228
wx_build_skb(struct wx_ring * rx_ring,struct wx_rx_buffer * rx_buffer,union wx_rx_desc * rx_desc)229 static struct sk_buff *wx_build_skb(struct wx_ring *rx_ring,
230 struct wx_rx_buffer *rx_buffer,
231 union wx_rx_desc *rx_desc)
232 {
233 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
234 #if (PAGE_SIZE < 8192)
235 unsigned int truesize = WX_RX_BUFSZ;
236 #else
237 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
238 #endif
239 struct sk_buff *skb = rx_buffer->skb;
240
241 if (!skb) {
242 void *page_addr = page_address(rx_buffer->page) +
243 rx_buffer->page_offset;
244
245 /* prefetch first cache line of first page */
246 net_prefetch(page_addr);
247
248 /* allocate a skb to store the frags */
249 skb = napi_alloc_skb(&rx_ring->q_vector->napi, WX_RXBUFFER_256);
250 if (unlikely(!skb))
251 return NULL;
252
253 /* we will be copying header into skb->data in
254 * pskb_may_pull so it is in our interest to prefetch
255 * it now to avoid a possible cache miss
256 */
257 prefetchw(skb->data);
258
259 if (size <= WX_RXBUFFER_256) {
260 memcpy(__skb_put(skb, size), page_addr,
261 ALIGN(size, sizeof(long)));
262 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, true);
263 return skb;
264 }
265
266 skb_mark_for_recycle(skb);
267
268 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_EOP))
269 WX_CB(skb)->dma = rx_buffer->dma;
270
271 skb_add_rx_frag(skb, 0, rx_buffer->page,
272 rx_buffer->page_offset,
273 size, truesize);
274 goto out;
275
276 } else {
277 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
278 rx_buffer->page_offset, size, truesize);
279 }
280
281 out:
282 #if (PAGE_SIZE < 8192)
283 /* flip page offset to other buffer */
284 rx_buffer->page_offset ^= truesize;
285 #else
286 /* move offset up to the next cache line */
287 rx_buffer->page_offset += truesize;
288 #endif
289
290 return skb;
291 }
292
wx_alloc_mapped_page(struct wx_ring * rx_ring,struct wx_rx_buffer * bi)293 static bool wx_alloc_mapped_page(struct wx_ring *rx_ring,
294 struct wx_rx_buffer *bi)
295 {
296 struct page *page = bi->page;
297 dma_addr_t dma;
298
299 /* since we are recycling buffers we should seldom need to alloc */
300 if (likely(page))
301 return true;
302
303 page = page_pool_dev_alloc_pages(rx_ring->page_pool);
304 if (unlikely(!page))
305 return false;
306 dma = page_pool_get_dma_addr(page);
307
308 bi->dma = dma;
309 bi->page = page;
310 bi->page_offset = 0;
311
312 return true;
313 }
314
315 /**
316 * wx_alloc_rx_buffers - Replace used receive buffers
317 * @rx_ring: ring to place buffers on
318 * @cleaned_count: number of buffers to replace
319 **/
wx_alloc_rx_buffers(struct wx_ring * rx_ring,u16 cleaned_count)320 void wx_alloc_rx_buffers(struct wx_ring *rx_ring, u16 cleaned_count)
321 {
322 u16 i = rx_ring->next_to_use;
323 union wx_rx_desc *rx_desc;
324 struct wx_rx_buffer *bi;
325
326 /* nothing to do */
327 if (!cleaned_count)
328 return;
329
330 rx_desc = WX_RX_DESC(rx_ring, i);
331 bi = &rx_ring->rx_buffer_info[i];
332 i -= rx_ring->count;
333
334 do {
335 if (!wx_alloc_mapped_page(rx_ring, bi))
336 break;
337
338 /* sync the buffer for use by the device */
339 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
340 bi->page_offset,
341 WX_RX_BUFSZ,
342 DMA_FROM_DEVICE);
343
344 rx_desc->read.pkt_addr =
345 cpu_to_le64(bi->dma + bi->page_offset);
346
347 rx_desc++;
348 bi++;
349 i++;
350 if (unlikely(!i)) {
351 rx_desc = WX_RX_DESC(rx_ring, 0);
352 bi = rx_ring->rx_buffer_info;
353 i -= rx_ring->count;
354 }
355
356 /* clear the status bits for the next_to_use descriptor */
357 rx_desc->wb.upper.status_error = 0;
358 /* clear the length for the next_to_use descriptor */
359 rx_desc->wb.upper.length = 0;
360
361 cleaned_count--;
362 } while (cleaned_count);
363
364 i += rx_ring->count;
365
366 if (rx_ring->next_to_use != i) {
367 rx_ring->next_to_use = i;
368 /* update next to alloc since we have filled the ring */
369 rx_ring->next_to_alloc = i;
370
371 /* Force memory writes to complete before letting h/w
372 * know there are new descriptors to fetch. (Only
373 * applicable for weak-ordered memory model archs,
374 * such as IA-64).
375 */
376 wmb();
377 writel(i, rx_ring->tail);
378 }
379 }
380
wx_desc_unused(struct wx_ring * ring)381 u16 wx_desc_unused(struct wx_ring *ring)
382 {
383 u16 ntc = ring->next_to_clean;
384 u16 ntu = ring->next_to_use;
385
386 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
387 }
388
389 /**
390 * wx_is_non_eop - process handling of non-EOP buffers
391 * @rx_ring: Rx ring being processed
392 * @rx_desc: Rx descriptor for current buffer
393 * @skb: Current socket buffer containing buffer in progress
394 *
395 * This function updates next to clean. If the buffer is an EOP buffer
396 * this function exits returning false, otherwise it will place the
397 * sk_buff in the next buffer to be chained and return true indicating
398 * that this is in fact a non-EOP buffer.
399 **/
wx_is_non_eop(struct wx_ring * rx_ring,union wx_rx_desc * rx_desc,struct sk_buff * skb)400 static bool wx_is_non_eop(struct wx_ring *rx_ring,
401 union wx_rx_desc *rx_desc,
402 struct sk_buff *skb)
403 {
404 u32 ntc = rx_ring->next_to_clean + 1;
405
406 /* fetch, update, and store next to clean */
407 ntc = (ntc < rx_ring->count) ? ntc : 0;
408 rx_ring->next_to_clean = ntc;
409
410 prefetch(WX_RX_DESC(rx_ring, ntc));
411
412 /* if we are the last buffer then there is nothing else to do */
413 if (likely(wx_test_staterr(rx_desc, WX_RXD_STAT_EOP)))
414 return false;
415
416 rx_ring->rx_buffer_info[ntc].skb = skb;
417 rx_ring->rx_stats.non_eop_descs++;
418
419 return true;
420 }
421
wx_pull_tail(struct sk_buff * skb)422 static void wx_pull_tail(struct sk_buff *skb)
423 {
424 skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
425 unsigned int pull_len;
426 unsigned char *va;
427
428 /* it is valid to use page_address instead of kmap since we are
429 * working with pages allocated out of the lomem pool per
430 * alloc_page(GFP_ATOMIC)
431 */
432 va = skb_frag_address(frag);
433
434 /* we need the header to contain the greater of either ETH_HLEN or
435 * 60 bytes if the skb->len is less than 60 for skb_pad.
436 */
437 pull_len = eth_get_headlen(skb->dev, va, WX_RXBUFFER_256);
438
439 /* align pull length to size of long to optimize memcpy performance */
440 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
441
442 /* update all of the pointers */
443 skb_frag_size_sub(frag, pull_len);
444 skb_frag_off_add(frag, pull_len);
445 skb->data_len -= pull_len;
446 skb->tail += pull_len;
447 }
448
449 /**
450 * wx_cleanup_headers - Correct corrupted or empty headers
451 * @rx_ring: rx descriptor ring packet is being transacted on
452 * @rx_desc: pointer to the EOP Rx descriptor
453 * @skb: pointer to current skb being fixed
454 *
455 * Check for corrupted packet headers caused by senders on the local L2
456 * embedded NIC switch not setting up their Tx Descriptors right. These
457 * should be very rare.
458 *
459 * Also address the case where we are pulling data in on pages only
460 * and as such no data is present in the skb header.
461 *
462 * In addition if skb is not at least 60 bytes we need to pad it so that
463 * it is large enough to qualify as a valid Ethernet frame.
464 *
465 * Returns true if an error was encountered and skb was freed.
466 **/
wx_cleanup_headers(struct wx_ring * rx_ring,union wx_rx_desc * rx_desc,struct sk_buff * skb)467 static bool wx_cleanup_headers(struct wx_ring *rx_ring,
468 union wx_rx_desc *rx_desc,
469 struct sk_buff *skb)
470 {
471 struct net_device *netdev = rx_ring->netdev;
472
473 /* verify that the packet does not have any known errors */
474 if (!netdev ||
475 unlikely(wx_test_staterr(rx_desc, WX_RXD_ERR_RXE) &&
476 !(netdev->features & NETIF_F_RXALL))) {
477 dev_kfree_skb_any(skb);
478 return true;
479 }
480
481 /* place header in linear portion of buffer */
482 if (!skb_headlen(skb))
483 wx_pull_tail(skb);
484
485 /* if eth_skb_pad returns an error the skb was freed */
486 if (eth_skb_pad(skb))
487 return true;
488
489 return false;
490 }
491
wx_rx_hash(struct wx_ring * ring,union wx_rx_desc * rx_desc,struct sk_buff * skb)492 static void wx_rx_hash(struct wx_ring *ring,
493 union wx_rx_desc *rx_desc,
494 struct sk_buff *skb)
495 {
496 u16 rss_type;
497
498 if (!(ring->netdev->features & NETIF_F_RXHASH))
499 return;
500
501 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
502 WX_RXD_RSSTYPE_MASK;
503
504 if (!rss_type)
505 return;
506
507 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
508 (WX_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
509 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
510 }
511
512 /**
513 * wx_rx_checksum - indicate in skb if hw indicated a good cksum
514 * @ring: structure containing ring specific data
515 * @rx_desc: current Rx descriptor being processed
516 * @skb: skb currently being received and modified
517 **/
wx_rx_checksum(struct wx_ring * ring,union wx_rx_desc * rx_desc,struct sk_buff * skb)518 static void wx_rx_checksum(struct wx_ring *ring,
519 union wx_rx_desc *rx_desc,
520 struct sk_buff *skb)
521 {
522 struct wx_dec_ptype dptype = wx_decode_ptype(WX_RXD_PKTTYPE(rx_desc));
523
524 skb_checksum_none_assert(skb);
525 /* Rx csum disabled */
526 if (!(ring->netdev->features & NETIF_F_RXCSUM))
527 return;
528
529 /* if IPv4 header checksum error */
530 if ((wx_test_staterr(rx_desc, WX_RXD_STAT_IPCS) &&
531 wx_test_staterr(rx_desc, WX_RXD_ERR_IPE)) ||
532 (wx_test_staterr(rx_desc, WX_RXD_STAT_OUTERIPCS) &&
533 wx_test_staterr(rx_desc, WX_RXD_ERR_OUTERIPER))) {
534 ring->rx_stats.csum_err++;
535 return;
536 }
537
538 /* L4 checksum offload flag must set for the below code to work */
539 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_L4CS))
540 return;
541
542 /* Hardware can't guarantee csum if IPv6 Dest Header found */
543 if (dptype.prot != WX_DEC_PTYPE_PROT_SCTP && WX_RXD_IPV6EX(rx_desc))
544 return;
545
546 /* if L4 checksum error */
547 if (wx_test_staterr(rx_desc, WX_RXD_ERR_TCPE)) {
548 ring->rx_stats.csum_err++;
549 return;
550 }
551
552 /* It must be a TCP or UDP or SCTP packet with a valid checksum */
553 skb->ip_summed = CHECKSUM_UNNECESSARY;
554
555 /* If there is an outer header present that might contain a checksum
556 * we need to bump the checksum level by 1 to reflect the fact that
557 * we are indicating we validated the inner checksum.
558 */
559 if (dptype.etype >= WX_DEC_PTYPE_ETYPE_IG)
560 __skb_incr_checksum_unnecessary(skb);
561 ring->rx_stats.csum_good_cnt++;
562 }
563
wx_rx_vlan(struct wx_ring * ring,union wx_rx_desc * rx_desc,struct sk_buff * skb)564 static void wx_rx_vlan(struct wx_ring *ring, union wx_rx_desc *rx_desc,
565 struct sk_buff *skb)
566 {
567 u16 ethertype;
568 u8 idx = 0;
569
570 if ((ring->netdev->features &
571 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) &&
572 wx_test_staterr(rx_desc, WX_RXD_STAT_VP)) {
573 idx = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
574 0x1c0) >> 6;
575 ethertype = ring->q_vector->wx->tpid[idx];
576 __vlan_hwaccel_put_tag(skb, htons(ethertype),
577 le16_to_cpu(rx_desc->wb.upper.vlan));
578 }
579 }
580
581 /**
582 * wx_process_skb_fields - Populate skb header fields from Rx descriptor
583 * @rx_ring: rx descriptor ring packet is being transacted on
584 * @rx_desc: pointer to the EOP Rx descriptor
585 * @skb: pointer to current skb being populated
586 *
587 * This function checks the ring, descriptor, and packet information in
588 * order to populate the hash, checksum, protocol, and
589 * other fields within the skb.
590 **/
wx_process_skb_fields(struct wx_ring * rx_ring,union wx_rx_desc * rx_desc,struct sk_buff * skb)591 static void wx_process_skb_fields(struct wx_ring *rx_ring,
592 union wx_rx_desc *rx_desc,
593 struct sk_buff *skb)
594 {
595 wx_rx_hash(rx_ring, rx_desc, skb);
596 wx_rx_checksum(rx_ring, rx_desc, skb);
597 wx_rx_vlan(rx_ring, rx_desc, skb);
598 skb_record_rx_queue(skb, rx_ring->queue_index);
599 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
600 }
601
602 /**
603 * wx_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
604 * @q_vector: structure containing interrupt and ring information
605 * @rx_ring: rx descriptor ring to transact packets on
606 * @budget: Total limit on number of packets to process
607 *
608 * This function provides a "bounce buffer" approach to Rx interrupt
609 * processing. The advantage to this is that on systems that have
610 * expensive overhead for IOMMU access this provides a means of avoiding
611 * it by maintaining the mapping of the page to the system.
612 *
613 * Returns amount of work completed.
614 **/
wx_clean_rx_irq(struct wx_q_vector * q_vector,struct wx_ring * rx_ring,int budget)615 static int wx_clean_rx_irq(struct wx_q_vector *q_vector,
616 struct wx_ring *rx_ring,
617 int budget)
618 {
619 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
620 u16 cleaned_count = wx_desc_unused(rx_ring);
621
622 do {
623 struct wx_rx_buffer *rx_buffer;
624 union wx_rx_desc *rx_desc;
625 struct sk_buff *skb;
626 int rx_buffer_pgcnt;
627
628 /* return some buffers to hardware, one at a time is too slow */
629 if (cleaned_count >= WX_RX_BUFFER_WRITE) {
630 wx_alloc_rx_buffers(rx_ring, cleaned_count);
631 cleaned_count = 0;
632 }
633
634 rx_desc = WX_RX_DESC(rx_ring, rx_ring->next_to_clean);
635 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_DD))
636 break;
637
638 /* This memory barrier is needed to keep us from reading
639 * any other fields out of the rx_desc until we know the
640 * descriptor has been written back
641 */
642 dma_rmb();
643
644 rx_buffer = wx_get_rx_buffer(rx_ring, rx_desc, &skb, &rx_buffer_pgcnt);
645
646 /* retrieve a buffer from the ring */
647 skb = wx_build_skb(rx_ring, rx_buffer, rx_desc);
648
649 /* exit if we failed to retrieve a buffer */
650 if (!skb) {
651 rx_ring->rx_stats.alloc_rx_buff_failed++;
652 break;
653 }
654
655 wx_put_rx_buffer(rx_ring, rx_buffer, skb, rx_buffer_pgcnt);
656 cleaned_count++;
657
658 /* place incomplete frames back on ring for completion */
659 if (wx_is_non_eop(rx_ring, rx_desc, skb))
660 continue;
661
662 /* verify the packet layout is correct */
663 if (wx_cleanup_headers(rx_ring, rx_desc, skb))
664 continue;
665
666 /* probably a little skewed due to removing CRC */
667 total_rx_bytes += skb->len;
668
669 /* populate checksum, timestamp, VLAN, and protocol */
670 wx_process_skb_fields(rx_ring, rx_desc, skb);
671 napi_gro_receive(&q_vector->napi, skb);
672
673 /* update budget accounting */
674 total_rx_packets++;
675 } while (likely(total_rx_packets < budget));
676
677 u64_stats_update_begin(&rx_ring->syncp);
678 rx_ring->stats.packets += total_rx_packets;
679 rx_ring->stats.bytes += total_rx_bytes;
680 u64_stats_update_end(&rx_ring->syncp);
681 q_vector->rx.total_packets += total_rx_packets;
682 q_vector->rx.total_bytes += total_rx_bytes;
683
684 return total_rx_packets;
685 }
686
wx_txring_txq(const struct wx_ring * ring)687 static struct netdev_queue *wx_txring_txq(const struct wx_ring *ring)
688 {
689 return netdev_get_tx_queue(ring->netdev, ring->queue_index);
690 }
691
692 /**
693 * wx_clean_tx_irq - Reclaim resources after transmit completes
694 * @q_vector: structure containing interrupt and ring information
695 * @tx_ring: tx ring to clean
696 * @napi_budget: Used to determine if we are in netpoll
697 **/
wx_clean_tx_irq(struct wx_q_vector * q_vector,struct wx_ring * tx_ring,int napi_budget)698 static bool wx_clean_tx_irq(struct wx_q_vector *q_vector,
699 struct wx_ring *tx_ring, int napi_budget)
700 {
701 unsigned int budget = q_vector->wx->tx_work_limit;
702 unsigned int total_bytes = 0, total_packets = 0;
703 unsigned int i = tx_ring->next_to_clean;
704 struct wx_tx_buffer *tx_buffer;
705 union wx_tx_desc *tx_desc;
706
707 if (!netif_carrier_ok(tx_ring->netdev))
708 return true;
709
710 tx_buffer = &tx_ring->tx_buffer_info[i];
711 tx_desc = WX_TX_DESC(tx_ring, i);
712 i -= tx_ring->count;
713
714 do {
715 union wx_tx_desc *eop_desc = tx_buffer->next_to_watch;
716
717 /* if next_to_watch is not set then there is no work pending */
718 if (!eop_desc)
719 break;
720
721 /* prevent any other reads prior to eop_desc */
722 smp_rmb();
723
724 /* if DD is not set pending work has not been completed */
725 if (!(eop_desc->wb.status & cpu_to_le32(WX_TXD_STAT_DD)))
726 break;
727
728 /* clear next_to_watch to prevent false hangs */
729 tx_buffer->next_to_watch = NULL;
730
731 /* update the statistics for this packet */
732 total_bytes += tx_buffer->bytecount;
733 total_packets += tx_buffer->gso_segs;
734
735 /* free the skb */
736 napi_consume_skb(tx_buffer->skb, napi_budget);
737
738 /* unmap skb header data */
739 dma_unmap_single(tx_ring->dev,
740 dma_unmap_addr(tx_buffer, dma),
741 dma_unmap_len(tx_buffer, len),
742 DMA_TO_DEVICE);
743
744 /* clear tx_buffer data */
745 dma_unmap_len_set(tx_buffer, len, 0);
746
747 /* unmap remaining buffers */
748 while (tx_desc != eop_desc) {
749 tx_buffer++;
750 tx_desc++;
751 i++;
752 if (unlikely(!i)) {
753 i -= tx_ring->count;
754 tx_buffer = tx_ring->tx_buffer_info;
755 tx_desc = WX_TX_DESC(tx_ring, 0);
756 }
757
758 /* unmap any remaining paged data */
759 if (dma_unmap_len(tx_buffer, len)) {
760 dma_unmap_page(tx_ring->dev,
761 dma_unmap_addr(tx_buffer, dma),
762 dma_unmap_len(tx_buffer, len),
763 DMA_TO_DEVICE);
764 dma_unmap_len_set(tx_buffer, len, 0);
765 }
766 }
767
768 /* move us one more past the eop_desc for start of next pkt */
769 tx_buffer++;
770 tx_desc++;
771 i++;
772 if (unlikely(!i)) {
773 i -= tx_ring->count;
774 tx_buffer = tx_ring->tx_buffer_info;
775 tx_desc = WX_TX_DESC(tx_ring, 0);
776 }
777
778 /* issue prefetch for next Tx descriptor */
779 prefetch(tx_desc);
780
781 /* update budget accounting */
782 budget--;
783 } while (likely(budget));
784
785 i += tx_ring->count;
786 tx_ring->next_to_clean = i;
787 u64_stats_update_begin(&tx_ring->syncp);
788 tx_ring->stats.bytes += total_bytes;
789 tx_ring->stats.packets += total_packets;
790 u64_stats_update_end(&tx_ring->syncp);
791 q_vector->tx.total_bytes += total_bytes;
792 q_vector->tx.total_packets += total_packets;
793
794 netdev_tx_completed_queue(wx_txring_txq(tx_ring),
795 total_packets, total_bytes);
796
797 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
798 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
799 (wx_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
800 /* Make sure that anybody stopping the queue after this
801 * sees the new next_to_clean.
802 */
803 smp_mb();
804
805 if (__netif_subqueue_stopped(tx_ring->netdev,
806 tx_ring->queue_index) &&
807 netif_running(tx_ring->netdev)) {
808 netif_wake_subqueue(tx_ring->netdev,
809 tx_ring->queue_index);
810 ++tx_ring->tx_stats.restart_queue;
811 }
812 }
813
814 return !!budget;
815 }
816
817 /**
818 * wx_poll - NAPI polling RX/TX cleanup routine
819 * @napi: napi struct with our devices info in it
820 * @budget: amount of work driver is allowed to do this pass, in packets
821 *
822 * This function will clean all queues associated with a q_vector.
823 **/
wx_poll(struct napi_struct * napi,int budget)824 static int wx_poll(struct napi_struct *napi, int budget)
825 {
826 struct wx_q_vector *q_vector = container_of(napi, struct wx_q_vector, napi);
827 int per_ring_budget, work_done = 0;
828 struct wx *wx = q_vector->wx;
829 bool clean_complete = true;
830 struct wx_ring *ring;
831
832 wx_for_each_ring(ring, q_vector->tx) {
833 if (!wx_clean_tx_irq(q_vector, ring, budget))
834 clean_complete = false;
835 }
836
837 /* Exit if we are called by netpoll */
838 if (budget <= 0)
839 return budget;
840
841 /* attempt to distribute budget to each queue fairly, but don't allow
842 * the budget to go below 1 because we'll exit polling
843 */
844 if (q_vector->rx.count > 1)
845 per_ring_budget = max(budget / q_vector->rx.count, 1);
846 else
847 per_ring_budget = budget;
848
849 wx_for_each_ring(ring, q_vector->rx) {
850 int cleaned = wx_clean_rx_irq(q_vector, ring, per_ring_budget);
851
852 work_done += cleaned;
853 if (cleaned >= per_ring_budget)
854 clean_complete = false;
855 }
856
857 /* If all work not completed, return budget and keep polling */
858 if (!clean_complete)
859 return budget;
860
861 /* all work done, exit the polling mode */
862 if (likely(napi_complete_done(napi, work_done))) {
863 if (netif_running(wx->netdev))
864 wx_intr_enable(wx, WX_INTR_Q(q_vector->v_idx));
865 }
866
867 return min(work_done, budget - 1);
868 }
869
wx_maybe_stop_tx(struct wx_ring * tx_ring,u16 size)870 static int wx_maybe_stop_tx(struct wx_ring *tx_ring, u16 size)
871 {
872 if (likely(wx_desc_unused(tx_ring) >= size))
873 return 0;
874
875 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
876
877 /* For the next check */
878 smp_mb();
879
880 /* We need to check again in a case another CPU has just
881 * made room available.
882 */
883 if (likely(wx_desc_unused(tx_ring) < size))
884 return -EBUSY;
885
886 /* A reprieve! - use start_queue because it doesn't call schedule */
887 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
888 ++tx_ring->tx_stats.restart_queue;
889
890 return 0;
891 }
892
wx_tx_cmd_type(u32 tx_flags)893 static u32 wx_tx_cmd_type(u32 tx_flags)
894 {
895 /* set type for advanced descriptor with frame checksum insertion */
896 u32 cmd_type = WX_TXD_DTYP_DATA | WX_TXD_IFCS;
897
898 /* set HW vlan bit if vlan is present */
899 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_HW_VLAN, WX_TXD_VLE);
900 /* set segmentation enable bits for TSO/FSO */
901 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_TSO, WX_TXD_TSE);
902 /* set timestamp bit if present */
903 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_TSTAMP, WX_TXD_MAC_TSTAMP);
904 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_LINKSEC, WX_TXD_LINKSEC);
905
906 return cmd_type;
907 }
908
wx_tx_olinfo_status(union wx_tx_desc * tx_desc,u32 tx_flags,unsigned int paylen)909 static void wx_tx_olinfo_status(union wx_tx_desc *tx_desc,
910 u32 tx_flags, unsigned int paylen)
911 {
912 u32 olinfo_status = paylen << WX_TXD_PAYLEN_SHIFT;
913
914 /* enable L4 checksum for TSO and TX checksum offload */
915 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_CSUM, WX_TXD_L4CS);
916 /* enable IPv4 checksum for TSO */
917 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_IPV4, WX_TXD_IIPCS);
918 /* enable outer IPv4 checksum for TSO */
919 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_OUTER_IPV4,
920 WX_TXD_EIPCS);
921 /* Check Context must be set if Tx switch is enabled, which it
922 * always is for case where virtual functions are running
923 */
924 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_CC, WX_TXD_CC);
925 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_IPSEC,
926 WX_TXD_IPSEC);
927 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
928 }
929
wx_tx_map(struct wx_ring * tx_ring,struct wx_tx_buffer * first,const u8 hdr_len)930 static void wx_tx_map(struct wx_ring *tx_ring,
931 struct wx_tx_buffer *first,
932 const u8 hdr_len)
933 {
934 struct sk_buff *skb = first->skb;
935 struct wx_tx_buffer *tx_buffer;
936 u32 tx_flags = first->tx_flags;
937 u16 i = tx_ring->next_to_use;
938 unsigned int data_len, size;
939 union wx_tx_desc *tx_desc;
940 skb_frag_t *frag;
941 dma_addr_t dma;
942 u32 cmd_type;
943
944 cmd_type = wx_tx_cmd_type(tx_flags);
945 tx_desc = WX_TX_DESC(tx_ring, i);
946 wx_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
947
948 size = skb_headlen(skb);
949 data_len = skb->data_len;
950 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
951
952 tx_buffer = first;
953
954 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
955 if (dma_mapping_error(tx_ring->dev, dma))
956 goto dma_error;
957
958 /* record length, and DMA address */
959 dma_unmap_len_set(tx_buffer, len, size);
960 dma_unmap_addr_set(tx_buffer, dma, dma);
961
962 tx_desc->read.buffer_addr = cpu_to_le64(dma);
963
964 while (unlikely(size > WX_MAX_DATA_PER_TXD)) {
965 tx_desc->read.cmd_type_len =
966 cpu_to_le32(cmd_type ^ WX_MAX_DATA_PER_TXD);
967
968 i++;
969 tx_desc++;
970 if (i == tx_ring->count) {
971 tx_desc = WX_TX_DESC(tx_ring, 0);
972 i = 0;
973 }
974 tx_desc->read.olinfo_status = 0;
975
976 dma += WX_MAX_DATA_PER_TXD;
977 size -= WX_MAX_DATA_PER_TXD;
978
979 tx_desc->read.buffer_addr = cpu_to_le64(dma);
980 }
981
982 if (likely(!data_len))
983 break;
984
985 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
986
987 i++;
988 tx_desc++;
989 if (i == tx_ring->count) {
990 tx_desc = WX_TX_DESC(tx_ring, 0);
991 i = 0;
992 }
993 tx_desc->read.olinfo_status = 0;
994
995 size = skb_frag_size(frag);
996
997 data_len -= size;
998
999 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1000 DMA_TO_DEVICE);
1001
1002 tx_buffer = &tx_ring->tx_buffer_info[i];
1003 }
1004
1005 /* write last descriptor with RS and EOP bits */
1006 cmd_type |= size | WX_TXD_EOP | WX_TXD_RS;
1007 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
1008
1009 netdev_tx_sent_queue(wx_txring_txq(tx_ring), first->bytecount);
1010
1011 skb_tx_timestamp(skb);
1012
1013 /* Force memory writes to complete before letting h/w know there
1014 * are new descriptors to fetch. (Only applicable for weak-ordered
1015 * memory model archs, such as IA-64).
1016 *
1017 * We also need this memory barrier to make certain all of the
1018 * status bits have been updated before next_to_watch is written.
1019 */
1020 wmb();
1021
1022 /* set next_to_watch value indicating a packet is present */
1023 first->next_to_watch = tx_desc;
1024
1025 i++;
1026 if (i == tx_ring->count)
1027 i = 0;
1028
1029 tx_ring->next_to_use = i;
1030
1031 wx_maybe_stop_tx(tx_ring, DESC_NEEDED);
1032
1033 if (netif_xmit_stopped(wx_txring_txq(tx_ring)) || !netdev_xmit_more())
1034 writel(i, tx_ring->tail);
1035
1036 return;
1037 dma_error:
1038 dev_err(tx_ring->dev, "TX DMA map failed\n");
1039
1040 /* clear dma mappings for failed tx_buffer_info map */
1041 for (;;) {
1042 tx_buffer = &tx_ring->tx_buffer_info[i];
1043 if (dma_unmap_len(tx_buffer, len))
1044 dma_unmap_page(tx_ring->dev,
1045 dma_unmap_addr(tx_buffer, dma),
1046 dma_unmap_len(tx_buffer, len),
1047 DMA_TO_DEVICE);
1048 dma_unmap_len_set(tx_buffer, len, 0);
1049 if (tx_buffer == first)
1050 break;
1051 if (i == 0)
1052 i += tx_ring->count;
1053 i--;
1054 }
1055
1056 dev_kfree_skb_any(first->skb);
1057 first->skb = NULL;
1058
1059 tx_ring->next_to_use = i;
1060 }
1061
wx_tx_ctxtdesc(struct wx_ring * tx_ring,u32 vlan_macip_lens,u32 fcoe_sof_eof,u32 type_tucmd,u32 mss_l4len_idx)1062 static void wx_tx_ctxtdesc(struct wx_ring *tx_ring, u32 vlan_macip_lens,
1063 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
1064 {
1065 struct wx_tx_context_desc *context_desc;
1066 u16 i = tx_ring->next_to_use;
1067
1068 context_desc = WX_TX_CTXTDESC(tx_ring, i);
1069 i++;
1070 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1071
1072 /* set bits to identify this as an advanced context descriptor */
1073 type_tucmd |= WX_TXD_DTYP_CTXT;
1074 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
1075 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
1076 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
1077 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
1078 }
1079
wx_get_ipv6_proto(struct sk_buff * skb,int offset,u8 * nexthdr)1080 static void wx_get_ipv6_proto(struct sk_buff *skb, int offset, u8 *nexthdr)
1081 {
1082 struct ipv6hdr *hdr = (struct ipv6hdr *)(skb->data + offset);
1083
1084 *nexthdr = hdr->nexthdr;
1085 offset += sizeof(struct ipv6hdr);
1086 while (ipv6_ext_hdr(*nexthdr)) {
1087 struct ipv6_opt_hdr _hdr, *hp;
1088
1089 if (*nexthdr == NEXTHDR_NONE)
1090 return;
1091 hp = skb_header_pointer(skb, offset, sizeof(_hdr), &_hdr);
1092 if (!hp)
1093 return;
1094 if (*nexthdr == NEXTHDR_FRAGMENT)
1095 break;
1096 *nexthdr = hp->nexthdr;
1097 }
1098 }
1099
1100 union network_header {
1101 struct iphdr *ipv4;
1102 struct ipv6hdr *ipv6;
1103 void *raw;
1104 };
1105
wx_encode_tx_desc_ptype(const struct wx_tx_buffer * first)1106 static u8 wx_encode_tx_desc_ptype(const struct wx_tx_buffer *first)
1107 {
1108 u8 tun_prot = 0, l4_prot = 0, ptype = 0;
1109 struct sk_buff *skb = first->skb;
1110
1111 if (skb->encapsulation) {
1112 union network_header hdr;
1113
1114 switch (first->protocol) {
1115 case htons(ETH_P_IP):
1116 tun_prot = ip_hdr(skb)->protocol;
1117 ptype = WX_PTYPE_TUN_IPV4;
1118 break;
1119 case htons(ETH_P_IPV6):
1120 wx_get_ipv6_proto(skb, skb_network_offset(skb), &tun_prot);
1121 ptype = WX_PTYPE_TUN_IPV6;
1122 break;
1123 default:
1124 return ptype;
1125 }
1126
1127 if (tun_prot == IPPROTO_IPIP) {
1128 hdr.raw = (void *)inner_ip_hdr(skb);
1129 ptype |= WX_PTYPE_PKT_IPIP;
1130 } else if (tun_prot == IPPROTO_UDP) {
1131 hdr.raw = (void *)inner_ip_hdr(skb);
1132 if (skb->inner_protocol_type != ENCAP_TYPE_ETHER ||
1133 skb->inner_protocol != htons(ETH_P_TEB)) {
1134 ptype |= WX_PTYPE_PKT_IG;
1135 } else {
1136 if (((struct ethhdr *)skb_inner_mac_header(skb))->h_proto
1137 == htons(ETH_P_8021Q))
1138 ptype |= WX_PTYPE_PKT_IGMV;
1139 else
1140 ptype |= WX_PTYPE_PKT_IGM;
1141 }
1142
1143 } else if (tun_prot == IPPROTO_GRE) {
1144 hdr.raw = (void *)inner_ip_hdr(skb);
1145 if (skb->inner_protocol == htons(ETH_P_IP) ||
1146 skb->inner_protocol == htons(ETH_P_IPV6)) {
1147 ptype |= WX_PTYPE_PKT_IG;
1148 } else {
1149 if (((struct ethhdr *)skb_inner_mac_header(skb))->h_proto
1150 == htons(ETH_P_8021Q))
1151 ptype |= WX_PTYPE_PKT_IGMV;
1152 else
1153 ptype |= WX_PTYPE_PKT_IGM;
1154 }
1155 } else {
1156 return ptype;
1157 }
1158
1159 switch (hdr.ipv4->version) {
1160 case IPVERSION:
1161 l4_prot = hdr.ipv4->protocol;
1162 break;
1163 case 6:
1164 wx_get_ipv6_proto(skb, skb_inner_network_offset(skb), &l4_prot);
1165 ptype |= WX_PTYPE_PKT_IPV6;
1166 break;
1167 default:
1168 return ptype;
1169 }
1170 } else {
1171 switch (first->protocol) {
1172 case htons(ETH_P_IP):
1173 l4_prot = ip_hdr(skb)->protocol;
1174 ptype = WX_PTYPE_PKT_IP;
1175 break;
1176 case htons(ETH_P_IPV6):
1177 wx_get_ipv6_proto(skb, skb_network_offset(skb), &l4_prot);
1178 ptype = WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6;
1179 break;
1180 default:
1181 return WX_PTYPE_PKT_MAC | WX_PTYPE_TYP_MAC;
1182 }
1183 }
1184 switch (l4_prot) {
1185 case IPPROTO_TCP:
1186 ptype |= WX_PTYPE_TYP_TCP;
1187 break;
1188 case IPPROTO_UDP:
1189 ptype |= WX_PTYPE_TYP_UDP;
1190 break;
1191 case IPPROTO_SCTP:
1192 ptype |= WX_PTYPE_TYP_SCTP;
1193 break;
1194 default:
1195 ptype |= WX_PTYPE_TYP_IP;
1196 break;
1197 }
1198
1199 return ptype;
1200 }
1201
wx_tso(struct wx_ring * tx_ring,struct wx_tx_buffer * first,u8 * hdr_len,u8 ptype)1202 static int wx_tso(struct wx_ring *tx_ring, struct wx_tx_buffer *first,
1203 u8 *hdr_len, u8 ptype)
1204 {
1205 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
1206 struct net_device *netdev = tx_ring->netdev;
1207 u32 l4len, tunhdr_eiplen_tunlen = 0;
1208 struct sk_buff *skb = first->skb;
1209 bool enc = skb->encapsulation;
1210 struct ipv6hdr *ipv6h;
1211 struct tcphdr *tcph;
1212 struct iphdr *iph;
1213 u8 tun_prot = 0;
1214 int err;
1215
1216 if (skb->ip_summed != CHECKSUM_PARTIAL)
1217 return 0;
1218
1219 if (!skb_is_gso(skb))
1220 return 0;
1221
1222 err = skb_cow_head(skb, 0);
1223 if (err < 0)
1224 return err;
1225
1226 /* indicates the inner headers in the skbuff are valid. */
1227 iph = enc ? inner_ip_hdr(skb) : ip_hdr(skb);
1228 if (iph->version == 4) {
1229 tcph = enc ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1230 iph->tot_len = 0;
1231 iph->check = 0;
1232 tcph->check = ~csum_tcpudp_magic(iph->saddr,
1233 iph->daddr, 0,
1234 IPPROTO_TCP, 0);
1235 first->tx_flags |= WX_TX_FLAGS_TSO |
1236 WX_TX_FLAGS_CSUM |
1237 WX_TX_FLAGS_IPV4 |
1238 WX_TX_FLAGS_CC;
1239 } else if (iph->version == 6 && skb_is_gso_v6(skb)) {
1240 ipv6h = enc ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
1241 tcph = enc ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1242 ipv6h->payload_len = 0;
1243 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr,
1244 &ipv6h->daddr, 0,
1245 IPPROTO_TCP, 0);
1246 first->tx_flags |= WX_TX_FLAGS_TSO |
1247 WX_TX_FLAGS_CSUM |
1248 WX_TX_FLAGS_CC;
1249 }
1250
1251 /* compute header lengths */
1252 l4len = enc ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1253 *hdr_len = enc ? skb_inner_transport_offset(skb) :
1254 skb_transport_offset(skb);
1255 *hdr_len += l4len;
1256
1257 /* update gso size and bytecount with header size */
1258 first->gso_segs = skb_shinfo(skb)->gso_segs;
1259 first->bytecount += (first->gso_segs - 1) * *hdr_len;
1260
1261 /* mss_l4len_id: use 0 as index for TSO */
1262 mss_l4len_idx = l4len << WX_TXD_L4LEN_SHIFT;
1263 mss_l4len_idx |= skb_shinfo(skb)->gso_size << WX_TXD_MSS_SHIFT;
1264
1265 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
1266 if (enc) {
1267 switch (first->protocol) {
1268 case htons(ETH_P_IP):
1269 tun_prot = ip_hdr(skb)->protocol;
1270 first->tx_flags |= WX_TX_FLAGS_OUTER_IPV4;
1271 break;
1272 case htons(ETH_P_IPV6):
1273 tun_prot = ipv6_hdr(skb)->nexthdr;
1274 break;
1275 default:
1276 break;
1277 }
1278 switch (tun_prot) {
1279 case IPPROTO_UDP:
1280 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_UDP;
1281 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) <<
1282 WX_TXD_OUTER_IPLEN_SHIFT) |
1283 (((skb_inner_mac_header(skb) -
1284 skb_transport_header(skb)) >> 1) <<
1285 WX_TXD_TUNNEL_LEN_SHIFT);
1286 break;
1287 case IPPROTO_GRE:
1288 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_GRE;
1289 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) <<
1290 WX_TXD_OUTER_IPLEN_SHIFT) |
1291 (((skb_inner_mac_header(skb) -
1292 skb_transport_header(skb)) >> 1) <<
1293 WX_TXD_TUNNEL_LEN_SHIFT);
1294 break;
1295 case IPPROTO_IPIP:
1296 tunhdr_eiplen_tunlen = (((char *)inner_ip_hdr(skb) -
1297 (char *)ip_hdr(skb)) >> 2) <<
1298 WX_TXD_OUTER_IPLEN_SHIFT;
1299 break;
1300 default:
1301 break;
1302 }
1303 vlan_macip_lens = skb_inner_network_header_len(skb) >> 1;
1304 } else {
1305 vlan_macip_lens = skb_network_header_len(skb) >> 1;
1306 }
1307
1308 vlan_macip_lens |= skb_network_offset(skb) << WX_TXD_MACLEN_SHIFT;
1309 vlan_macip_lens |= first->tx_flags & WX_TX_FLAGS_VLAN_MASK;
1310
1311 type_tucmd = ptype << 24;
1312 if (skb->vlan_proto == htons(ETH_P_8021AD) &&
1313 netdev->features & NETIF_F_HW_VLAN_STAG_TX)
1314 type_tucmd |= WX_SET_FLAG(first->tx_flags,
1315 WX_TX_FLAGS_HW_VLAN,
1316 0x1 << WX_TXD_TAG_TPID_SEL_SHIFT);
1317 wx_tx_ctxtdesc(tx_ring, vlan_macip_lens, tunhdr_eiplen_tunlen,
1318 type_tucmd, mss_l4len_idx);
1319
1320 return 1;
1321 }
1322
wx_tx_csum(struct wx_ring * tx_ring,struct wx_tx_buffer * first,u8 ptype)1323 static void wx_tx_csum(struct wx_ring *tx_ring, struct wx_tx_buffer *first,
1324 u8 ptype)
1325 {
1326 u32 tunhdr_eiplen_tunlen = 0, vlan_macip_lens = 0;
1327 struct net_device *netdev = tx_ring->netdev;
1328 u32 mss_l4len_idx = 0, type_tucmd;
1329 struct sk_buff *skb = first->skb;
1330 u8 tun_prot = 0;
1331
1332 if (skb->ip_summed != CHECKSUM_PARTIAL) {
1333 csum_failed:
1334 if (!(first->tx_flags & WX_TX_FLAGS_HW_VLAN) &&
1335 !(first->tx_flags & WX_TX_FLAGS_CC))
1336 return;
1337 vlan_macip_lens = skb_network_offset(skb) <<
1338 WX_TXD_MACLEN_SHIFT;
1339 } else {
1340 u8 l4_prot = 0;
1341 union {
1342 struct iphdr *ipv4;
1343 struct ipv6hdr *ipv6;
1344 u8 *raw;
1345 } network_hdr;
1346 union {
1347 struct tcphdr *tcphdr;
1348 u8 *raw;
1349 } transport_hdr;
1350
1351 if (skb->encapsulation) {
1352 network_hdr.raw = skb_inner_network_header(skb);
1353 transport_hdr.raw = skb_inner_transport_header(skb);
1354 vlan_macip_lens = skb_network_offset(skb) <<
1355 WX_TXD_MACLEN_SHIFT;
1356 switch (first->protocol) {
1357 case htons(ETH_P_IP):
1358 tun_prot = ip_hdr(skb)->protocol;
1359 break;
1360 case htons(ETH_P_IPV6):
1361 tun_prot = ipv6_hdr(skb)->nexthdr;
1362 break;
1363 default:
1364 return;
1365 }
1366 switch (tun_prot) {
1367 case IPPROTO_UDP:
1368 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_UDP;
1369 tunhdr_eiplen_tunlen |=
1370 ((skb_network_header_len(skb) >> 2) <<
1371 WX_TXD_OUTER_IPLEN_SHIFT) |
1372 (((skb_inner_mac_header(skb) -
1373 skb_transport_header(skb)) >> 1) <<
1374 WX_TXD_TUNNEL_LEN_SHIFT);
1375 break;
1376 case IPPROTO_GRE:
1377 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_GRE;
1378 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) <<
1379 WX_TXD_OUTER_IPLEN_SHIFT) |
1380 (((skb_inner_mac_header(skb) -
1381 skb_transport_header(skb)) >> 1) <<
1382 WX_TXD_TUNNEL_LEN_SHIFT);
1383 break;
1384 case IPPROTO_IPIP:
1385 tunhdr_eiplen_tunlen = (((char *)inner_ip_hdr(skb) -
1386 (char *)ip_hdr(skb)) >> 2) <<
1387 WX_TXD_OUTER_IPLEN_SHIFT;
1388 break;
1389 default:
1390 break;
1391 }
1392
1393 } else {
1394 network_hdr.raw = skb_network_header(skb);
1395 transport_hdr.raw = skb_transport_header(skb);
1396 vlan_macip_lens = skb_network_offset(skb) <<
1397 WX_TXD_MACLEN_SHIFT;
1398 }
1399
1400 switch (network_hdr.ipv4->version) {
1401 case IPVERSION:
1402 vlan_macip_lens |= (transport_hdr.raw - network_hdr.raw) >> 1;
1403 l4_prot = network_hdr.ipv4->protocol;
1404 break;
1405 case 6:
1406 vlan_macip_lens |= (transport_hdr.raw - network_hdr.raw) >> 1;
1407 l4_prot = network_hdr.ipv6->nexthdr;
1408 break;
1409 default:
1410 break;
1411 }
1412
1413 switch (l4_prot) {
1414 case IPPROTO_TCP:
1415 mss_l4len_idx = (transport_hdr.tcphdr->doff * 4) <<
1416 WX_TXD_L4LEN_SHIFT;
1417 break;
1418 case IPPROTO_SCTP:
1419 mss_l4len_idx = sizeof(struct sctphdr) <<
1420 WX_TXD_L4LEN_SHIFT;
1421 break;
1422 case IPPROTO_UDP:
1423 mss_l4len_idx = sizeof(struct udphdr) <<
1424 WX_TXD_L4LEN_SHIFT;
1425 break;
1426 default:
1427 skb_checksum_help(skb);
1428 goto csum_failed;
1429 }
1430
1431 /* update TX checksum flag */
1432 first->tx_flags |= WX_TX_FLAGS_CSUM;
1433 }
1434 first->tx_flags |= WX_TX_FLAGS_CC;
1435 /* vlan_macip_lens: MACLEN, VLAN tag */
1436 vlan_macip_lens |= first->tx_flags & WX_TX_FLAGS_VLAN_MASK;
1437
1438 type_tucmd = ptype << 24;
1439 if (skb->vlan_proto == htons(ETH_P_8021AD) &&
1440 netdev->features & NETIF_F_HW_VLAN_STAG_TX)
1441 type_tucmd |= WX_SET_FLAG(first->tx_flags,
1442 WX_TX_FLAGS_HW_VLAN,
1443 0x1 << WX_TXD_TAG_TPID_SEL_SHIFT);
1444 wx_tx_ctxtdesc(tx_ring, vlan_macip_lens, tunhdr_eiplen_tunlen,
1445 type_tucmd, mss_l4len_idx);
1446 }
1447
wx_xmit_frame_ring(struct sk_buff * skb,struct wx_ring * tx_ring)1448 static netdev_tx_t wx_xmit_frame_ring(struct sk_buff *skb,
1449 struct wx_ring *tx_ring)
1450 {
1451 struct wx *wx = netdev_priv(tx_ring->netdev);
1452 u16 count = TXD_USE_COUNT(skb_headlen(skb));
1453 struct wx_tx_buffer *first;
1454 u8 hdr_len = 0, ptype;
1455 unsigned short f;
1456 u32 tx_flags = 0;
1457 int tso;
1458
1459 /* need: 1 descriptor per page * PAGE_SIZE/WX_MAX_DATA_PER_TXD,
1460 * + 1 desc for skb_headlen/WX_MAX_DATA_PER_TXD,
1461 * + 2 desc gap to keep tail from touching head,
1462 * + 1 desc for context descriptor,
1463 * otherwise try next time
1464 */
1465 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1466 count += TXD_USE_COUNT(skb_frag_size(&skb_shinfo(skb)->
1467 frags[f]));
1468
1469 if (wx_maybe_stop_tx(tx_ring, count + 3)) {
1470 tx_ring->tx_stats.tx_busy++;
1471 return NETDEV_TX_BUSY;
1472 }
1473
1474 /* record the location of the first descriptor for this packet */
1475 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
1476 first->skb = skb;
1477 first->bytecount = skb->len;
1478 first->gso_segs = 1;
1479
1480 /* if we have a HW VLAN tag being added default to the HW one */
1481 if (skb_vlan_tag_present(skb)) {
1482 tx_flags |= skb_vlan_tag_get(skb) << WX_TX_FLAGS_VLAN_SHIFT;
1483 tx_flags |= WX_TX_FLAGS_HW_VLAN;
1484 }
1485
1486 /* record initial flags and protocol */
1487 first->tx_flags = tx_flags;
1488 first->protocol = vlan_get_protocol(skb);
1489
1490 ptype = wx_encode_tx_desc_ptype(first);
1491
1492 tso = wx_tso(tx_ring, first, &hdr_len, ptype);
1493 if (tso < 0)
1494 goto out_drop;
1495 else if (!tso)
1496 wx_tx_csum(tx_ring, first, ptype);
1497
1498 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags) && tx_ring->atr_sample_rate)
1499 wx->atr(tx_ring, first, ptype);
1500
1501 wx_tx_map(tx_ring, first, hdr_len);
1502
1503 return NETDEV_TX_OK;
1504 out_drop:
1505 dev_kfree_skb_any(first->skb);
1506 first->skb = NULL;
1507
1508 return NETDEV_TX_OK;
1509 }
1510
wx_xmit_frame(struct sk_buff * skb,struct net_device * netdev)1511 netdev_tx_t wx_xmit_frame(struct sk_buff *skb,
1512 struct net_device *netdev)
1513 {
1514 unsigned int r_idx = skb->queue_mapping;
1515 struct wx *wx = netdev_priv(netdev);
1516 struct wx_ring *tx_ring;
1517
1518 if (!netif_carrier_ok(netdev)) {
1519 dev_kfree_skb_any(skb);
1520 return NETDEV_TX_OK;
1521 }
1522
1523 /* The minimum packet size for olinfo paylen is 17 so pad the skb
1524 * in order to meet this minimum size requirement.
1525 */
1526 if (skb_put_padto(skb, 17))
1527 return NETDEV_TX_OK;
1528
1529 if (r_idx >= wx->num_tx_queues)
1530 r_idx = r_idx % wx->num_tx_queues;
1531 tx_ring = wx->tx_ring[r_idx];
1532
1533 return wx_xmit_frame_ring(skb, tx_ring);
1534 }
1535 EXPORT_SYMBOL(wx_xmit_frame);
1536
wx_napi_enable_all(struct wx * wx)1537 void wx_napi_enable_all(struct wx *wx)
1538 {
1539 struct wx_q_vector *q_vector;
1540 int q_idx;
1541
1542 for (q_idx = 0; q_idx < wx->num_q_vectors; q_idx++) {
1543 q_vector = wx->q_vector[q_idx];
1544 napi_enable(&q_vector->napi);
1545 }
1546 }
1547 EXPORT_SYMBOL(wx_napi_enable_all);
1548
wx_napi_disable_all(struct wx * wx)1549 void wx_napi_disable_all(struct wx *wx)
1550 {
1551 struct wx_q_vector *q_vector;
1552 int q_idx;
1553
1554 for (q_idx = 0; q_idx < wx->num_q_vectors; q_idx++) {
1555 q_vector = wx->q_vector[q_idx];
1556 napi_disable(&q_vector->napi);
1557 }
1558 }
1559 EXPORT_SYMBOL(wx_napi_disable_all);
1560
1561 /**
1562 * wx_set_rss_queues: Allocate queues for RSS
1563 * @wx: board private structure to initialize
1564 *
1565 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
1566 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
1567 *
1568 **/
wx_set_rss_queues(struct wx * wx)1569 static void wx_set_rss_queues(struct wx *wx)
1570 {
1571 struct wx_ring_feature *f;
1572
1573 /* set mask for 16 queue limit of RSS */
1574 f = &wx->ring_feature[RING_F_RSS];
1575 f->indices = f->limit;
1576
1577 if (!(test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags)))
1578 goto out;
1579
1580 clear_bit(WX_FLAG_FDIR_HASH, wx->flags);
1581
1582 wx->ring_feature[RING_F_FDIR].indices = 1;
1583 /* Use Flow Director in addition to RSS to ensure the best
1584 * distribution of flows across cores, even when an FDIR flow
1585 * isn't matched.
1586 */
1587 if (f->indices > 1) {
1588 f = &wx->ring_feature[RING_F_FDIR];
1589
1590 f->indices = f->limit;
1591
1592 if (!(test_bit(WX_FLAG_FDIR_PERFECT, wx->flags)))
1593 set_bit(WX_FLAG_FDIR_HASH, wx->flags);
1594 }
1595
1596 out:
1597 wx->num_rx_queues = f->indices;
1598 wx->num_tx_queues = f->indices;
1599 }
1600
wx_set_num_queues(struct wx * wx)1601 static void wx_set_num_queues(struct wx *wx)
1602 {
1603 /* Start with base case */
1604 wx->num_rx_queues = 1;
1605 wx->num_tx_queues = 1;
1606 wx->queues_per_pool = 1;
1607
1608 wx_set_rss_queues(wx);
1609 }
1610
1611 /**
1612 * wx_acquire_msix_vectors - acquire MSI-X vectors
1613 * @wx: board private structure
1614 *
1615 * Attempts to acquire a suitable range of MSI-X vector interrupts. Will
1616 * return a negative error code if unable to acquire MSI-X vectors for any
1617 * reason.
1618 */
wx_acquire_msix_vectors(struct wx * wx)1619 static int wx_acquire_msix_vectors(struct wx *wx)
1620 {
1621 struct irq_affinity affd = { .post_vectors = 1 };
1622 int nvecs, i;
1623
1624 /* We start by asking for one vector per queue pair */
1625 nvecs = max(wx->num_rx_queues, wx->num_tx_queues);
1626 nvecs = min_t(int, nvecs, num_online_cpus());
1627 nvecs = min_t(int, nvecs, wx->mac.max_msix_vectors);
1628
1629 wx->msix_q_entries = kcalloc(nvecs, sizeof(struct msix_entry),
1630 GFP_KERNEL);
1631 if (!wx->msix_q_entries)
1632 return -ENOMEM;
1633
1634 /* One for non-queue interrupts */
1635 nvecs += 1;
1636
1637 wx->msix_entry = kcalloc(1, sizeof(struct msix_entry),
1638 GFP_KERNEL);
1639 if (!wx->msix_entry) {
1640 kfree(wx->msix_q_entries);
1641 wx->msix_q_entries = NULL;
1642 return -ENOMEM;
1643 }
1644
1645 nvecs = pci_alloc_irq_vectors_affinity(wx->pdev, nvecs,
1646 nvecs,
1647 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY,
1648 &affd);
1649 if (nvecs < 0) {
1650 wx_err(wx, "Failed to allocate MSI-X interrupts. Err: %d\n", nvecs);
1651 kfree(wx->msix_q_entries);
1652 wx->msix_q_entries = NULL;
1653 kfree(wx->msix_entry);
1654 wx->msix_entry = NULL;
1655 return nvecs;
1656 }
1657
1658 nvecs -= 1;
1659 for (i = 0; i < nvecs; i++) {
1660 wx->msix_q_entries[i].entry = i;
1661 wx->msix_q_entries[i].vector = pci_irq_vector(wx->pdev, i);
1662 }
1663
1664 wx->num_q_vectors = nvecs;
1665
1666 wx->msix_entry->entry = nvecs;
1667 wx->msix_entry->vector = pci_irq_vector(wx->pdev, nvecs);
1668
1669 return 0;
1670 }
1671
1672 /**
1673 * wx_set_interrupt_capability - set MSI-X or MSI if supported
1674 * @wx: board private structure to initialize
1675 *
1676 * Attempt to configure the interrupts using the best available
1677 * capabilities of the hardware and the kernel.
1678 **/
wx_set_interrupt_capability(struct wx * wx)1679 static int wx_set_interrupt_capability(struct wx *wx)
1680 {
1681 struct pci_dev *pdev = wx->pdev;
1682 int nvecs, ret;
1683
1684 /* We will try to get MSI-X interrupts first */
1685 ret = wx_acquire_msix_vectors(wx);
1686 if (ret == 0 || (ret == -ENOMEM))
1687 return ret;
1688
1689 /* Disable RSS */
1690 dev_warn(&wx->pdev->dev, "Disabling RSS support\n");
1691 wx->ring_feature[RING_F_RSS].limit = 1;
1692
1693 wx_set_num_queues(wx);
1694
1695 /* minmum one for queue, one for misc*/
1696 nvecs = 1;
1697 nvecs = pci_alloc_irq_vectors(pdev, nvecs,
1698 nvecs, PCI_IRQ_MSI | PCI_IRQ_INTX);
1699 if (nvecs == 1) {
1700 if (pdev->msi_enabled)
1701 wx_err(wx, "Fallback to MSI.\n");
1702 else
1703 wx_err(wx, "Fallback to INTx.\n");
1704 } else {
1705 wx_err(wx, "Failed to allocate MSI/INTx interrupts. Error: %d\n", nvecs);
1706 return nvecs;
1707 }
1708
1709 pdev->irq = pci_irq_vector(pdev, 0);
1710 wx->num_q_vectors = 1;
1711
1712 return 0;
1713 }
1714
1715 /**
1716 * wx_cache_ring_rss - Descriptor ring to register mapping for RSS
1717 * @wx: board private structure to initialize
1718 *
1719 * Cache the descriptor ring offsets for RSS, ATR, FCoE, and SR-IOV.
1720 *
1721 **/
wx_cache_ring_rss(struct wx * wx)1722 static void wx_cache_ring_rss(struct wx *wx)
1723 {
1724 u16 i;
1725
1726 for (i = 0; i < wx->num_rx_queues; i++)
1727 wx->rx_ring[i]->reg_idx = i;
1728
1729 for (i = 0; i < wx->num_tx_queues; i++)
1730 wx->tx_ring[i]->reg_idx = i;
1731 }
1732
wx_add_ring(struct wx_ring * ring,struct wx_ring_container * head)1733 static void wx_add_ring(struct wx_ring *ring, struct wx_ring_container *head)
1734 {
1735 ring->next = head->ring;
1736 head->ring = ring;
1737 head->count++;
1738 }
1739
1740 /**
1741 * wx_alloc_q_vector - Allocate memory for a single interrupt vector
1742 * @wx: board private structure to initialize
1743 * @v_count: q_vectors allocated on wx, used for ring interleaving
1744 * @v_idx: index of vector in wx struct
1745 * @txr_count: total number of Tx rings to allocate
1746 * @txr_idx: index of first Tx ring to allocate
1747 * @rxr_count: total number of Rx rings to allocate
1748 * @rxr_idx: index of first Rx ring to allocate
1749 *
1750 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1751 **/
wx_alloc_q_vector(struct wx * wx,unsigned int v_count,unsigned int v_idx,unsigned int txr_count,unsigned int txr_idx,unsigned int rxr_count,unsigned int rxr_idx)1752 static int wx_alloc_q_vector(struct wx *wx,
1753 unsigned int v_count, unsigned int v_idx,
1754 unsigned int txr_count, unsigned int txr_idx,
1755 unsigned int rxr_count, unsigned int rxr_idx)
1756 {
1757 struct wx_q_vector *q_vector;
1758 int ring_count, default_itr;
1759 struct wx_ring *ring;
1760
1761 /* note this will allocate space for the ring structure as well! */
1762 ring_count = txr_count + rxr_count;
1763
1764 q_vector = kzalloc(struct_size(q_vector, ring, ring_count),
1765 GFP_KERNEL);
1766 if (!q_vector)
1767 return -ENOMEM;
1768
1769 /* initialize NAPI */
1770 netif_napi_add(wx->netdev, &q_vector->napi,
1771 wx_poll);
1772
1773 /* tie q_vector and wx together */
1774 wx->q_vector[v_idx] = q_vector;
1775 q_vector->wx = wx;
1776 q_vector->v_idx = v_idx;
1777 if (cpu_online(v_idx))
1778 q_vector->numa_node = cpu_to_node(v_idx);
1779
1780 /* initialize pointer to rings */
1781 ring = q_vector->ring;
1782
1783 if (wx->mac.type == wx_mac_sp)
1784 default_itr = WX_12K_ITR;
1785 else
1786 default_itr = WX_7K_ITR;
1787 /* initialize ITR */
1788 if (txr_count && !rxr_count)
1789 /* tx only vector */
1790 q_vector->itr = wx->tx_itr_setting ?
1791 default_itr : wx->tx_itr_setting;
1792 else
1793 /* rx or rx/tx vector */
1794 q_vector->itr = wx->rx_itr_setting ?
1795 default_itr : wx->rx_itr_setting;
1796
1797 while (txr_count) {
1798 /* assign generic ring traits */
1799 ring->dev = &wx->pdev->dev;
1800 ring->netdev = wx->netdev;
1801
1802 /* configure backlink on ring */
1803 ring->q_vector = q_vector;
1804
1805 /* update q_vector Tx values */
1806 wx_add_ring(ring, &q_vector->tx);
1807
1808 /* apply Tx specific ring traits */
1809 ring->count = wx->tx_ring_count;
1810
1811 ring->queue_index = txr_idx;
1812
1813 /* assign ring to wx */
1814 wx->tx_ring[txr_idx] = ring;
1815
1816 /* update count and index */
1817 txr_count--;
1818 txr_idx += v_count;
1819
1820 /* push pointer to next ring */
1821 ring++;
1822 }
1823
1824 while (rxr_count) {
1825 /* assign generic ring traits */
1826 ring->dev = &wx->pdev->dev;
1827 ring->netdev = wx->netdev;
1828
1829 /* configure backlink on ring */
1830 ring->q_vector = q_vector;
1831
1832 /* update q_vector Rx values */
1833 wx_add_ring(ring, &q_vector->rx);
1834
1835 /* apply Rx specific ring traits */
1836 ring->count = wx->rx_ring_count;
1837 ring->queue_index = rxr_idx;
1838
1839 /* assign ring to wx */
1840 wx->rx_ring[rxr_idx] = ring;
1841
1842 /* update count and index */
1843 rxr_count--;
1844 rxr_idx += v_count;
1845
1846 /* push pointer to next ring */
1847 ring++;
1848 }
1849
1850 return 0;
1851 }
1852
1853 /**
1854 * wx_free_q_vector - Free memory allocated for specific interrupt vector
1855 * @wx: board private structure to initialize
1856 * @v_idx: Index of vector to be freed
1857 *
1858 * This function frees the memory allocated to the q_vector. In addition if
1859 * NAPI is enabled it will delete any references to the NAPI struct prior
1860 * to freeing the q_vector.
1861 **/
wx_free_q_vector(struct wx * wx,int v_idx)1862 static void wx_free_q_vector(struct wx *wx, int v_idx)
1863 {
1864 struct wx_q_vector *q_vector = wx->q_vector[v_idx];
1865 struct wx_ring *ring;
1866
1867 wx_for_each_ring(ring, q_vector->tx)
1868 wx->tx_ring[ring->queue_index] = NULL;
1869
1870 wx_for_each_ring(ring, q_vector->rx)
1871 wx->rx_ring[ring->queue_index] = NULL;
1872
1873 wx->q_vector[v_idx] = NULL;
1874 netif_napi_del(&q_vector->napi);
1875 kfree_rcu(q_vector, rcu);
1876 }
1877
1878 /**
1879 * wx_alloc_q_vectors - Allocate memory for interrupt vectors
1880 * @wx: board private structure to initialize
1881 *
1882 * We allocate one q_vector per queue interrupt. If allocation fails we
1883 * return -ENOMEM.
1884 **/
wx_alloc_q_vectors(struct wx * wx)1885 static int wx_alloc_q_vectors(struct wx *wx)
1886 {
1887 unsigned int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1888 unsigned int rxr_remaining = wx->num_rx_queues;
1889 unsigned int txr_remaining = wx->num_tx_queues;
1890 unsigned int q_vectors = wx->num_q_vectors;
1891 int rqpv, tqpv;
1892 int err;
1893
1894 for (; v_idx < q_vectors; v_idx++) {
1895 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1896 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1897 err = wx_alloc_q_vector(wx, q_vectors, v_idx,
1898 tqpv, txr_idx,
1899 rqpv, rxr_idx);
1900
1901 if (err)
1902 goto err_out;
1903
1904 /* update counts and index */
1905 rxr_remaining -= rqpv;
1906 txr_remaining -= tqpv;
1907 rxr_idx++;
1908 txr_idx++;
1909 }
1910
1911 return 0;
1912
1913 err_out:
1914 wx->num_tx_queues = 0;
1915 wx->num_rx_queues = 0;
1916 wx->num_q_vectors = 0;
1917
1918 while (v_idx--)
1919 wx_free_q_vector(wx, v_idx);
1920
1921 return -ENOMEM;
1922 }
1923
1924 /**
1925 * wx_free_q_vectors - Free memory allocated for interrupt vectors
1926 * @wx: board private structure to initialize
1927 *
1928 * This function frees the memory allocated to the q_vectors. In addition if
1929 * NAPI is enabled it will delete any references to the NAPI struct prior
1930 * to freeing the q_vector.
1931 **/
wx_free_q_vectors(struct wx * wx)1932 static void wx_free_q_vectors(struct wx *wx)
1933 {
1934 int v_idx = wx->num_q_vectors;
1935
1936 wx->num_tx_queues = 0;
1937 wx->num_rx_queues = 0;
1938 wx->num_q_vectors = 0;
1939
1940 while (v_idx--)
1941 wx_free_q_vector(wx, v_idx);
1942 }
1943
wx_reset_interrupt_capability(struct wx * wx)1944 void wx_reset_interrupt_capability(struct wx *wx)
1945 {
1946 struct pci_dev *pdev = wx->pdev;
1947
1948 if (!pdev->msi_enabled && !pdev->msix_enabled)
1949 return;
1950
1951 if (pdev->msix_enabled) {
1952 kfree(wx->msix_q_entries);
1953 wx->msix_q_entries = NULL;
1954 kfree(wx->msix_entry);
1955 wx->msix_entry = NULL;
1956 }
1957 pci_free_irq_vectors(wx->pdev);
1958 }
1959 EXPORT_SYMBOL(wx_reset_interrupt_capability);
1960
1961 /**
1962 * wx_clear_interrupt_scheme - Clear the current interrupt scheme settings
1963 * @wx: board private structure to clear interrupt scheme on
1964 *
1965 * We go through and clear interrupt specific resources and reset the structure
1966 * to pre-load conditions
1967 **/
wx_clear_interrupt_scheme(struct wx * wx)1968 void wx_clear_interrupt_scheme(struct wx *wx)
1969 {
1970 wx_free_q_vectors(wx);
1971 wx_reset_interrupt_capability(wx);
1972 }
1973 EXPORT_SYMBOL(wx_clear_interrupt_scheme);
1974
wx_init_interrupt_scheme(struct wx * wx)1975 int wx_init_interrupt_scheme(struct wx *wx)
1976 {
1977 int ret;
1978
1979 /* Number of supported queues */
1980 wx_set_num_queues(wx);
1981
1982 /* Set interrupt mode */
1983 ret = wx_set_interrupt_capability(wx);
1984 if (ret) {
1985 wx_err(wx, "Allocate irq vectors for failed.\n");
1986 return ret;
1987 }
1988
1989 /* Allocate memory for queues */
1990 ret = wx_alloc_q_vectors(wx);
1991 if (ret) {
1992 wx_err(wx, "Unable to allocate memory for queue vectors.\n");
1993 wx_reset_interrupt_capability(wx);
1994 return ret;
1995 }
1996
1997 wx_cache_ring_rss(wx);
1998
1999 return 0;
2000 }
2001 EXPORT_SYMBOL(wx_init_interrupt_scheme);
2002
wx_msix_clean_rings(int __always_unused irq,void * data)2003 irqreturn_t wx_msix_clean_rings(int __always_unused irq, void *data)
2004 {
2005 struct wx_q_vector *q_vector = data;
2006
2007 /* EIAM disabled interrupts (on this vector) for us */
2008 if (q_vector->rx.ring || q_vector->tx.ring)
2009 napi_schedule_irqoff(&q_vector->napi);
2010
2011 return IRQ_HANDLED;
2012 }
2013 EXPORT_SYMBOL(wx_msix_clean_rings);
2014
wx_free_irq(struct wx * wx)2015 void wx_free_irq(struct wx *wx)
2016 {
2017 struct pci_dev *pdev = wx->pdev;
2018 int vector;
2019
2020 if (!(pdev->msix_enabled)) {
2021 if (!wx->misc_irq_domain)
2022 free_irq(pdev->irq, wx);
2023 return;
2024 }
2025
2026 for (vector = 0; vector < wx->num_q_vectors; vector++) {
2027 struct wx_q_vector *q_vector = wx->q_vector[vector];
2028 struct msix_entry *entry = &wx->msix_q_entries[vector];
2029
2030 /* free only the irqs that were actually requested */
2031 if (!q_vector->rx.ring && !q_vector->tx.ring)
2032 continue;
2033
2034 free_irq(entry->vector, q_vector);
2035 }
2036
2037 if (!wx->misc_irq_domain)
2038 free_irq(wx->msix_entry->vector, wx);
2039 }
2040 EXPORT_SYMBOL(wx_free_irq);
2041
2042 /**
2043 * wx_setup_isb_resources - allocate interrupt status resources
2044 * @wx: board private structure
2045 *
2046 * Return 0 on success, negative on failure
2047 **/
wx_setup_isb_resources(struct wx * wx)2048 int wx_setup_isb_resources(struct wx *wx)
2049 {
2050 struct pci_dev *pdev = wx->pdev;
2051
2052 if (wx->isb_mem)
2053 return 0;
2054
2055 wx->isb_mem = dma_alloc_coherent(&pdev->dev,
2056 sizeof(u32) * 4,
2057 &wx->isb_dma,
2058 GFP_KERNEL);
2059 if (!wx->isb_mem) {
2060 wx_err(wx, "Alloc isb_mem failed\n");
2061 return -ENOMEM;
2062 }
2063
2064 return 0;
2065 }
2066 EXPORT_SYMBOL(wx_setup_isb_resources);
2067
2068 /**
2069 * wx_free_isb_resources - allocate all queues Rx resources
2070 * @wx: board private structure
2071 *
2072 * Return 0 on success, negative on failure
2073 **/
wx_free_isb_resources(struct wx * wx)2074 void wx_free_isb_resources(struct wx *wx)
2075 {
2076 struct pci_dev *pdev = wx->pdev;
2077
2078 dma_free_coherent(&pdev->dev, sizeof(u32) * 4,
2079 wx->isb_mem, wx->isb_dma);
2080 wx->isb_mem = NULL;
2081 }
2082 EXPORT_SYMBOL(wx_free_isb_resources);
2083
wx_misc_isb(struct wx * wx,enum wx_isb_idx idx)2084 u32 wx_misc_isb(struct wx *wx, enum wx_isb_idx idx)
2085 {
2086 u32 cur_tag = 0;
2087
2088 cur_tag = wx->isb_mem[WX_ISB_HEADER];
2089 wx->isb_tag[idx] = cur_tag;
2090
2091 return (__force u32)cpu_to_le32(wx->isb_mem[idx]);
2092 }
2093 EXPORT_SYMBOL(wx_misc_isb);
2094
2095 /**
2096 * wx_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
2097 * @wx: pointer to wx struct
2098 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
2099 * @queue: queue to map the corresponding interrupt to
2100 * @msix_vector: the vector to map to the corresponding queue
2101 *
2102 **/
wx_set_ivar(struct wx * wx,s8 direction,u16 queue,u16 msix_vector)2103 static void wx_set_ivar(struct wx *wx, s8 direction,
2104 u16 queue, u16 msix_vector)
2105 {
2106 u32 ivar, index;
2107
2108 if (direction == -1) {
2109 /* other causes */
2110 msix_vector |= WX_PX_IVAR_ALLOC_VAL;
2111 index = 0;
2112 ivar = rd32(wx, WX_PX_MISC_IVAR);
2113 ivar &= ~(0xFF << index);
2114 ivar |= (msix_vector << index);
2115 wr32(wx, WX_PX_MISC_IVAR, ivar);
2116 } else {
2117 /* tx or rx causes */
2118 msix_vector |= WX_PX_IVAR_ALLOC_VAL;
2119 index = ((16 * (queue & 1)) + (8 * direction));
2120 ivar = rd32(wx, WX_PX_IVAR(queue >> 1));
2121 ivar &= ~(0xFF << index);
2122 ivar |= (msix_vector << index);
2123 wr32(wx, WX_PX_IVAR(queue >> 1), ivar);
2124 }
2125 }
2126
2127 /**
2128 * wx_write_eitr - write EITR register in hardware specific way
2129 * @q_vector: structure containing interrupt and ring information
2130 *
2131 * This function is made to be called by ethtool and by the driver
2132 * when it needs to update EITR registers at runtime. Hardware
2133 * specific quirks/differences are taken care of here.
2134 */
wx_write_eitr(struct wx_q_vector * q_vector)2135 void wx_write_eitr(struct wx_q_vector *q_vector)
2136 {
2137 struct wx *wx = q_vector->wx;
2138 int v_idx = q_vector->v_idx;
2139 u32 itr_reg;
2140
2141 if (wx->mac.type == wx_mac_sp)
2142 itr_reg = q_vector->itr & WX_SP_MAX_EITR;
2143 else
2144 itr_reg = q_vector->itr & WX_EM_MAX_EITR;
2145
2146 itr_reg |= WX_PX_ITR_CNT_WDIS;
2147
2148 wr32(wx, WX_PX_ITR(v_idx), itr_reg);
2149 }
2150
2151 /**
2152 * wx_configure_vectors - Configure vectors for hardware
2153 * @wx: board private structure
2154 *
2155 * wx_configure_vectors sets up the hardware to properly generate MSI-X/MSI/INTx
2156 * interrupts.
2157 **/
wx_configure_vectors(struct wx * wx)2158 void wx_configure_vectors(struct wx *wx)
2159 {
2160 struct pci_dev *pdev = wx->pdev;
2161 u32 eitrsel = 0;
2162 u16 v_idx;
2163
2164 if (pdev->msix_enabled) {
2165 /* Populate MSIX to EITR Select */
2166 wr32(wx, WX_PX_ITRSEL, eitrsel);
2167 /* use EIAM to auto-mask when MSI-X interrupt is asserted
2168 * this saves a register write for every interrupt
2169 */
2170 wr32(wx, WX_PX_GPIE, WX_PX_GPIE_MODEL);
2171 } else {
2172 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2173 * specifically only auto mask tx and rx interrupts.
2174 */
2175 wr32(wx, WX_PX_GPIE, 0);
2176 }
2177
2178 /* Populate the IVAR table and set the ITR values to the
2179 * corresponding register.
2180 */
2181 for (v_idx = 0; v_idx < wx->num_q_vectors; v_idx++) {
2182 struct wx_q_vector *q_vector = wx->q_vector[v_idx];
2183 struct wx_ring *ring;
2184
2185 wx_for_each_ring(ring, q_vector->rx)
2186 wx_set_ivar(wx, 0, ring->reg_idx, v_idx);
2187
2188 wx_for_each_ring(ring, q_vector->tx)
2189 wx_set_ivar(wx, 1, ring->reg_idx, v_idx);
2190
2191 wx_write_eitr(q_vector);
2192 }
2193
2194 wx_set_ivar(wx, -1, 0, v_idx);
2195 if (pdev->msix_enabled)
2196 wr32(wx, WX_PX_ITR(v_idx), 1950);
2197 }
2198 EXPORT_SYMBOL(wx_configure_vectors);
2199
2200 /**
2201 * wx_clean_rx_ring - Free Rx Buffers per Queue
2202 * @rx_ring: ring to free buffers from
2203 **/
wx_clean_rx_ring(struct wx_ring * rx_ring)2204 static void wx_clean_rx_ring(struct wx_ring *rx_ring)
2205 {
2206 struct wx_rx_buffer *rx_buffer;
2207 u16 i = rx_ring->next_to_clean;
2208
2209 rx_buffer = &rx_ring->rx_buffer_info[i];
2210
2211 /* Free all the Rx ring sk_buffs */
2212 while (i != rx_ring->next_to_alloc) {
2213 if (rx_buffer->skb) {
2214 struct sk_buff *skb = rx_buffer->skb;
2215
2216 dev_kfree_skb(skb);
2217 }
2218
2219 /* Invalidate cache lines that may have been written to by
2220 * device so that we avoid corrupting memory.
2221 */
2222 dma_sync_single_range_for_cpu(rx_ring->dev,
2223 rx_buffer->dma,
2224 rx_buffer->page_offset,
2225 WX_RX_BUFSZ,
2226 DMA_FROM_DEVICE);
2227
2228 /* free resources associated with mapping */
2229 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false);
2230
2231 i++;
2232 rx_buffer++;
2233 if (i == rx_ring->count) {
2234 i = 0;
2235 rx_buffer = rx_ring->rx_buffer_info;
2236 }
2237 }
2238
2239 /* Zero out the descriptor ring */
2240 memset(rx_ring->desc, 0, rx_ring->size);
2241
2242 rx_ring->next_to_alloc = 0;
2243 rx_ring->next_to_clean = 0;
2244 rx_ring->next_to_use = 0;
2245 }
2246
2247 /**
2248 * wx_clean_all_rx_rings - Free Rx Buffers for all queues
2249 * @wx: board private structure
2250 **/
wx_clean_all_rx_rings(struct wx * wx)2251 void wx_clean_all_rx_rings(struct wx *wx)
2252 {
2253 int i;
2254
2255 for (i = 0; i < wx->num_rx_queues; i++)
2256 wx_clean_rx_ring(wx->rx_ring[i]);
2257 }
2258 EXPORT_SYMBOL(wx_clean_all_rx_rings);
2259
2260 /**
2261 * wx_free_rx_resources - Free Rx Resources
2262 * @rx_ring: ring to clean the resources from
2263 *
2264 * Free all receive software resources
2265 **/
wx_free_rx_resources(struct wx_ring * rx_ring)2266 static void wx_free_rx_resources(struct wx_ring *rx_ring)
2267 {
2268 wx_clean_rx_ring(rx_ring);
2269 kvfree(rx_ring->rx_buffer_info);
2270 rx_ring->rx_buffer_info = NULL;
2271
2272 /* if not set, then don't free */
2273 if (!rx_ring->desc)
2274 return;
2275
2276 dma_free_coherent(rx_ring->dev, rx_ring->size,
2277 rx_ring->desc, rx_ring->dma);
2278
2279 rx_ring->desc = NULL;
2280
2281 if (rx_ring->page_pool) {
2282 page_pool_destroy(rx_ring->page_pool);
2283 rx_ring->page_pool = NULL;
2284 }
2285 }
2286
2287 /**
2288 * wx_free_all_rx_resources - Free Rx Resources for All Queues
2289 * @wx: pointer to hardware structure
2290 *
2291 * Free all receive software resources
2292 **/
wx_free_all_rx_resources(struct wx * wx)2293 static void wx_free_all_rx_resources(struct wx *wx)
2294 {
2295 int i;
2296
2297 for (i = 0; i < wx->num_rx_queues; i++)
2298 wx_free_rx_resources(wx->rx_ring[i]);
2299 }
2300
2301 /**
2302 * wx_clean_tx_ring - Free Tx Buffers
2303 * @tx_ring: ring to be cleaned
2304 **/
wx_clean_tx_ring(struct wx_ring * tx_ring)2305 static void wx_clean_tx_ring(struct wx_ring *tx_ring)
2306 {
2307 struct wx_tx_buffer *tx_buffer;
2308 u16 i = tx_ring->next_to_clean;
2309
2310 tx_buffer = &tx_ring->tx_buffer_info[i];
2311
2312 while (i != tx_ring->next_to_use) {
2313 union wx_tx_desc *eop_desc, *tx_desc;
2314
2315 /* Free all the Tx ring sk_buffs */
2316 dev_kfree_skb_any(tx_buffer->skb);
2317
2318 /* unmap skb header data */
2319 dma_unmap_single(tx_ring->dev,
2320 dma_unmap_addr(tx_buffer, dma),
2321 dma_unmap_len(tx_buffer, len),
2322 DMA_TO_DEVICE);
2323
2324 /* check for eop_desc to determine the end of the packet */
2325 eop_desc = tx_buffer->next_to_watch;
2326 tx_desc = WX_TX_DESC(tx_ring, i);
2327
2328 /* unmap remaining buffers */
2329 while (tx_desc != eop_desc) {
2330 tx_buffer++;
2331 tx_desc++;
2332 i++;
2333 if (unlikely(i == tx_ring->count)) {
2334 i = 0;
2335 tx_buffer = tx_ring->tx_buffer_info;
2336 tx_desc = WX_TX_DESC(tx_ring, 0);
2337 }
2338
2339 /* unmap any remaining paged data */
2340 if (dma_unmap_len(tx_buffer, len))
2341 dma_unmap_page(tx_ring->dev,
2342 dma_unmap_addr(tx_buffer, dma),
2343 dma_unmap_len(tx_buffer, len),
2344 DMA_TO_DEVICE);
2345 }
2346
2347 /* move us one more past the eop_desc for start of next pkt */
2348 tx_buffer++;
2349 i++;
2350 if (unlikely(i == tx_ring->count)) {
2351 i = 0;
2352 tx_buffer = tx_ring->tx_buffer_info;
2353 }
2354 }
2355
2356 netdev_tx_reset_queue(wx_txring_txq(tx_ring));
2357
2358 /* reset next_to_use and next_to_clean */
2359 tx_ring->next_to_use = 0;
2360 tx_ring->next_to_clean = 0;
2361 }
2362
2363 /**
2364 * wx_clean_all_tx_rings - Free Tx Buffers for all queues
2365 * @wx: board private structure
2366 **/
wx_clean_all_tx_rings(struct wx * wx)2367 void wx_clean_all_tx_rings(struct wx *wx)
2368 {
2369 int i;
2370
2371 for (i = 0; i < wx->num_tx_queues; i++)
2372 wx_clean_tx_ring(wx->tx_ring[i]);
2373 }
2374 EXPORT_SYMBOL(wx_clean_all_tx_rings);
2375
2376 /**
2377 * wx_free_tx_resources - Free Tx Resources per Queue
2378 * @tx_ring: Tx descriptor ring for a specific queue
2379 *
2380 * Free all transmit software resources
2381 **/
wx_free_tx_resources(struct wx_ring * tx_ring)2382 static void wx_free_tx_resources(struct wx_ring *tx_ring)
2383 {
2384 wx_clean_tx_ring(tx_ring);
2385 kvfree(tx_ring->tx_buffer_info);
2386 tx_ring->tx_buffer_info = NULL;
2387
2388 /* if not set, then don't free */
2389 if (!tx_ring->desc)
2390 return;
2391
2392 dma_free_coherent(tx_ring->dev, tx_ring->size,
2393 tx_ring->desc, tx_ring->dma);
2394 tx_ring->desc = NULL;
2395 }
2396
2397 /**
2398 * wx_free_all_tx_resources - Free Tx Resources for All Queues
2399 * @wx: pointer to hardware structure
2400 *
2401 * Free all transmit software resources
2402 **/
wx_free_all_tx_resources(struct wx * wx)2403 static void wx_free_all_tx_resources(struct wx *wx)
2404 {
2405 int i;
2406
2407 for (i = 0; i < wx->num_tx_queues; i++)
2408 wx_free_tx_resources(wx->tx_ring[i]);
2409 }
2410
wx_free_resources(struct wx * wx)2411 void wx_free_resources(struct wx *wx)
2412 {
2413 wx_free_all_rx_resources(wx);
2414 wx_free_all_tx_resources(wx);
2415 }
2416 EXPORT_SYMBOL(wx_free_resources);
2417
wx_alloc_page_pool(struct wx_ring * rx_ring)2418 static int wx_alloc_page_pool(struct wx_ring *rx_ring)
2419 {
2420 int ret = 0;
2421
2422 struct page_pool_params pp_params = {
2423 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
2424 .order = 0,
2425 .pool_size = rx_ring->count,
2426 .nid = dev_to_node(rx_ring->dev),
2427 .dev = rx_ring->dev,
2428 .dma_dir = DMA_FROM_DEVICE,
2429 .offset = 0,
2430 .max_len = PAGE_SIZE,
2431 };
2432
2433 rx_ring->page_pool = page_pool_create(&pp_params);
2434 if (IS_ERR(rx_ring->page_pool)) {
2435 ret = PTR_ERR(rx_ring->page_pool);
2436 rx_ring->page_pool = NULL;
2437 }
2438
2439 return ret;
2440 }
2441
2442 /**
2443 * wx_setup_rx_resources - allocate Rx resources (Descriptors)
2444 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2445 *
2446 * Returns 0 on success, negative on failure
2447 **/
wx_setup_rx_resources(struct wx_ring * rx_ring)2448 static int wx_setup_rx_resources(struct wx_ring *rx_ring)
2449 {
2450 struct device *dev = rx_ring->dev;
2451 int orig_node = dev_to_node(dev);
2452 int numa_node = NUMA_NO_NODE;
2453 int size, ret;
2454
2455 size = sizeof(struct wx_rx_buffer) * rx_ring->count;
2456
2457 if (rx_ring->q_vector)
2458 numa_node = rx_ring->q_vector->numa_node;
2459
2460 rx_ring->rx_buffer_info = kvmalloc_node(size, GFP_KERNEL, numa_node);
2461 if (!rx_ring->rx_buffer_info)
2462 rx_ring->rx_buffer_info = kvmalloc(size, GFP_KERNEL);
2463 if (!rx_ring->rx_buffer_info)
2464 goto err;
2465
2466 /* Round up to nearest 4K */
2467 rx_ring->size = rx_ring->count * sizeof(union wx_rx_desc);
2468 rx_ring->size = ALIGN(rx_ring->size, 4096);
2469
2470 set_dev_node(dev, numa_node);
2471 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
2472 &rx_ring->dma, GFP_KERNEL);
2473 if (!rx_ring->desc) {
2474 set_dev_node(dev, orig_node);
2475 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
2476 &rx_ring->dma, GFP_KERNEL);
2477 }
2478
2479 if (!rx_ring->desc)
2480 goto err;
2481
2482 rx_ring->next_to_clean = 0;
2483 rx_ring->next_to_use = 0;
2484
2485 ret = wx_alloc_page_pool(rx_ring);
2486 if (ret < 0) {
2487 dev_err(rx_ring->dev, "Page pool creation failed: %d\n", ret);
2488 goto err_desc;
2489 }
2490
2491 return 0;
2492
2493 err_desc:
2494 dma_free_coherent(dev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2495 err:
2496 kvfree(rx_ring->rx_buffer_info);
2497 rx_ring->rx_buffer_info = NULL;
2498 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
2499 return -ENOMEM;
2500 }
2501
2502 /**
2503 * wx_setup_all_rx_resources - allocate all queues Rx resources
2504 * @wx: pointer to hardware structure
2505 *
2506 * If this function returns with an error, then it's possible one or
2507 * more of the rings is populated (while the rest are not). It is the
2508 * callers duty to clean those orphaned rings.
2509 *
2510 * Return 0 on success, negative on failure
2511 **/
wx_setup_all_rx_resources(struct wx * wx)2512 static int wx_setup_all_rx_resources(struct wx *wx)
2513 {
2514 int i, err = 0;
2515
2516 for (i = 0; i < wx->num_rx_queues; i++) {
2517 err = wx_setup_rx_resources(wx->rx_ring[i]);
2518 if (!err)
2519 continue;
2520
2521 wx_err(wx, "Allocation for Rx Queue %u failed\n", i);
2522 goto err_setup_rx;
2523 }
2524
2525 return 0;
2526 err_setup_rx:
2527 /* rewind the index freeing the rings as we go */
2528 while (i--)
2529 wx_free_rx_resources(wx->rx_ring[i]);
2530 return err;
2531 }
2532
2533 /**
2534 * wx_setup_tx_resources - allocate Tx resources (Descriptors)
2535 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2536 *
2537 * Return 0 on success, negative on failure
2538 **/
wx_setup_tx_resources(struct wx_ring * tx_ring)2539 static int wx_setup_tx_resources(struct wx_ring *tx_ring)
2540 {
2541 struct device *dev = tx_ring->dev;
2542 int orig_node = dev_to_node(dev);
2543 int numa_node = NUMA_NO_NODE;
2544 int size;
2545
2546 size = sizeof(struct wx_tx_buffer) * tx_ring->count;
2547
2548 if (tx_ring->q_vector)
2549 numa_node = tx_ring->q_vector->numa_node;
2550
2551 tx_ring->tx_buffer_info = kvmalloc_node(size, GFP_KERNEL, numa_node);
2552 if (!tx_ring->tx_buffer_info)
2553 tx_ring->tx_buffer_info = kvmalloc(size, GFP_KERNEL);
2554 if (!tx_ring->tx_buffer_info)
2555 goto err;
2556
2557 /* round up to nearest 4K */
2558 tx_ring->size = tx_ring->count * sizeof(union wx_tx_desc);
2559 tx_ring->size = ALIGN(tx_ring->size, 4096);
2560
2561 set_dev_node(dev, numa_node);
2562 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2563 &tx_ring->dma, GFP_KERNEL);
2564 if (!tx_ring->desc) {
2565 set_dev_node(dev, orig_node);
2566 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2567 &tx_ring->dma, GFP_KERNEL);
2568 }
2569
2570 if (!tx_ring->desc)
2571 goto err;
2572
2573 tx_ring->next_to_use = 0;
2574 tx_ring->next_to_clean = 0;
2575
2576 return 0;
2577
2578 err:
2579 kvfree(tx_ring->tx_buffer_info);
2580 tx_ring->tx_buffer_info = NULL;
2581 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
2582 return -ENOMEM;
2583 }
2584
2585 /**
2586 * wx_setup_all_tx_resources - allocate all queues Tx resources
2587 * @wx: pointer to private structure
2588 *
2589 * If this function returns with an error, then it's possible one or
2590 * more of the rings is populated (while the rest are not). It is the
2591 * callers duty to clean those orphaned rings.
2592 *
2593 * Return 0 on success, negative on failure
2594 **/
wx_setup_all_tx_resources(struct wx * wx)2595 static int wx_setup_all_tx_resources(struct wx *wx)
2596 {
2597 int i, err = 0;
2598
2599 for (i = 0; i < wx->num_tx_queues; i++) {
2600 err = wx_setup_tx_resources(wx->tx_ring[i]);
2601 if (!err)
2602 continue;
2603
2604 wx_err(wx, "Allocation for Tx Queue %u failed\n", i);
2605 goto err_setup_tx;
2606 }
2607
2608 return 0;
2609 err_setup_tx:
2610 /* rewind the index freeing the rings as we go */
2611 while (i--)
2612 wx_free_tx_resources(wx->tx_ring[i]);
2613 return err;
2614 }
2615
wx_setup_resources(struct wx * wx)2616 int wx_setup_resources(struct wx *wx)
2617 {
2618 int err;
2619
2620 /* allocate transmit descriptors */
2621 err = wx_setup_all_tx_resources(wx);
2622 if (err)
2623 return err;
2624
2625 /* allocate receive descriptors */
2626 err = wx_setup_all_rx_resources(wx);
2627 if (err)
2628 goto err_free_tx;
2629
2630 err = wx_setup_isb_resources(wx);
2631 if (err)
2632 goto err_free_rx;
2633
2634 return 0;
2635
2636 err_free_rx:
2637 wx_free_all_rx_resources(wx);
2638 err_free_tx:
2639 wx_free_all_tx_resources(wx);
2640
2641 return err;
2642 }
2643 EXPORT_SYMBOL(wx_setup_resources);
2644
2645 /**
2646 * wx_get_stats64 - Get System Network Statistics
2647 * @netdev: network interface device structure
2648 * @stats: storage space for 64bit statistics
2649 */
wx_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * stats)2650 void wx_get_stats64(struct net_device *netdev,
2651 struct rtnl_link_stats64 *stats)
2652 {
2653 struct wx *wx = netdev_priv(netdev);
2654 struct wx_hw_stats *hwstats;
2655 int i;
2656
2657 wx_update_stats(wx);
2658
2659 rcu_read_lock();
2660 for (i = 0; i < wx->num_rx_queues; i++) {
2661 struct wx_ring *ring = READ_ONCE(wx->rx_ring[i]);
2662 u64 bytes, packets;
2663 unsigned int start;
2664
2665 if (ring) {
2666 do {
2667 start = u64_stats_fetch_begin(&ring->syncp);
2668 packets = ring->stats.packets;
2669 bytes = ring->stats.bytes;
2670 } while (u64_stats_fetch_retry(&ring->syncp, start));
2671 stats->rx_packets += packets;
2672 stats->rx_bytes += bytes;
2673 }
2674 }
2675
2676 for (i = 0; i < wx->num_tx_queues; i++) {
2677 struct wx_ring *ring = READ_ONCE(wx->tx_ring[i]);
2678 u64 bytes, packets;
2679 unsigned int start;
2680
2681 if (ring) {
2682 do {
2683 start = u64_stats_fetch_begin(&ring->syncp);
2684 packets = ring->stats.packets;
2685 bytes = ring->stats.bytes;
2686 } while (u64_stats_fetch_retry(&ring->syncp,
2687 start));
2688 stats->tx_packets += packets;
2689 stats->tx_bytes += bytes;
2690 }
2691 }
2692
2693 rcu_read_unlock();
2694
2695 hwstats = &wx->stats;
2696 stats->rx_errors = hwstats->crcerrs + hwstats->rlec;
2697 stats->multicast = hwstats->qmprc;
2698 stats->rx_length_errors = hwstats->rlec;
2699 stats->rx_crc_errors = hwstats->crcerrs;
2700 }
2701 EXPORT_SYMBOL(wx_get_stats64);
2702
wx_set_features(struct net_device * netdev,netdev_features_t features)2703 int wx_set_features(struct net_device *netdev, netdev_features_t features)
2704 {
2705 netdev_features_t changed = netdev->features ^ features;
2706 struct wx *wx = netdev_priv(netdev);
2707 bool need_reset = false;
2708
2709 if (features & NETIF_F_RXHASH) {
2710 wr32m(wx, WX_RDB_RA_CTL, WX_RDB_RA_CTL_RSS_EN,
2711 WX_RDB_RA_CTL_RSS_EN);
2712 wx->rss_enabled = true;
2713 } else {
2714 wr32m(wx, WX_RDB_RA_CTL, WX_RDB_RA_CTL_RSS_EN, 0);
2715 wx->rss_enabled = false;
2716 }
2717
2718 netdev->features = features;
2719
2720 if (wx->mac.type == wx_mac_sp && changed & NETIF_F_HW_VLAN_CTAG_RX)
2721 wx->do_reset(netdev);
2722 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_FILTER))
2723 wx_set_rx_mode(netdev);
2724
2725 if (!(test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags)))
2726 return 0;
2727
2728 /* Check if Flow Director n-tuple support was enabled or disabled. If
2729 * the state changed, we need to reset.
2730 */
2731 switch (features & NETIF_F_NTUPLE) {
2732 case NETIF_F_NTUPLE:
2733 /* turn off ATR, enable perfect filters and reset */
2734 if (!(test_and_set_bit(WX_FLAG_FDIR_PERFECT, wx->flags)))
2735 need_reset = true;
2736
2737 clear_bit(WX_FLAG_FDIR_HASH, wx->flags);
2738 break;
2739 default:
2740 /* turn off perfect filters, enable ATR and reset */
2741 if (test_and_clear_bit(WX_FLAG_FDIR_PERFECT, wx->flags))
2742 need_reset = true;
2743
2744 /* We cannot enable ATR if RSS is disabled */
2745 if (wx->ring_feature[RING_F_RSS].limit <= 1)
2746 break;
2747
2748 set_bit(WX_FLAG_FDIR_HASH, wx->flags);
2749 break;
2750 }
2751
2752 if (need_reset)
2753 wx->do_reset(netdev);
2754
2755 return 0;
2756 }
2757 EXPORT_SYMBOL(wx_set_features);
2758
2759 #define NETIF_VLAN_STRIPPING_FEATURES (NETIF_F_HW_VLAN_CTAG_RX | \
2760 NETIF_F_HW_VLAN_STAG_RX)
2761
2762 #define NETIF_VLAN_INSERTION_FEATURES (NETIF_F_HW_VLAN_CTAG_TX | \
2763 NETIF_F_HW_VLAN_STAG_TX)
2764
2765 #define NETIF_VLAN_FILTERING_FEATURES (NETIF_F_HW_VLAN_CTAG_FILTER | \
2766 NETIF_F_HW_VLAN_STAG_FILTER)
2767
wx_fix_features(struct net_device * netdev,netdev_features_t features)2768 netdev_features_t wx_fix_features(struct net_device *netdev,
2769 netdev_features_t features)
2770 {
2771 netdev_features_t changed = netdev->features ^ features;
2772 struct wx *wx = netdev_priv(netdev);
2773
2774 if (changed & NETIF_VLAN_STRIPPING_FEATURES) {
2775 if ((features & NETIF_VLAN_STRIPPING_FEATURES) != NETIF_VLAN_STRIPPING_FEATURES &&
2776 (features & NETIF_VLAN_STRIPPING_FEATURES) != 0) {
2777 features &= ~NETIF_VLAN_STRIPPING_FEATURES;
2778 features |= netdev->features & NETIF_VLAN_STRIPPING_FEATURES;
2779 wx_err(wx, "802.1Q and 802.1ad VLAN stripping must be either both on or both off.");
2780 }
2781 }
2782
2783 if (changed & NETIF_VLAN_INSERTION_FEATURES) {
2784 if ((features & NETIF_VLAN_INSERTION_FEATURES) != NETIF_VLAN_INSERTION_FEATURES &&
2785 (features & NETIF_VLAN_INSERTION_FEATURES) != 0) {
2786 features &= ~NETIF_VLAN_INSERTION_FEATURES;
2787 features |= netdev->features & NETIF_VLAN_INSERTION_FEATURES;
2788 wx_err(wx, "802.1Q and 802.1ad VLAN insertion must be either both on or both off.");
2789 }
2790 }
2791
2792 if (changed & NETIF_VLAN_FILTERING_FEATURES) {
2793 if ((features & NETIF_VLAN_FILTERING_FEATURES) != NETIF_VLAN_FILTERING_FEATURES &&
2794 (features & NETIF_VLAN_FILTERING_FEATURES) != 0) {
2795 features &= ~NETIF_VLAN_FILTERING_FEATURES;
2796 features |= netdev->features & NETIF_VLAN_FILTERING_FEATURES;
2797 wx_err(wx, "802.1Q and 802.1ad VLAN filtering must be either both on or both off.");
2798 }
2799 }
2800
2801 return features;
2802 }
2803 EXPORT_SYMBOL(wx_fix_features);
2804
wx_set_ring(struct wx * wx,u32 new_tx_count,u32 new_rx_count,struct wx_ring * temp_ring)2805 void wx_set_ring(struct wx *wx, u32 new_tx_count,
2806 u32 new_rx_count, struct wx_ring *temp_ring)
2807 {
2808 int i, err = 0;
2809
2810 /* Setup new Tx resources and free the old Tx resources in that order.
2811 * We can then assign the new resources to the rings via a memcpy.
2812 * The advantage to this approach is that we are guaranteed to still
2813 * have resources even in the case of an allocation failure.
2814 */
2815 if (new_tx_count != wx->tx_ring_count) {
2816 for (i = 0; i < wx->num_tx_queues; i++) {
2817 memcpy(&temp_ring[i], wx->tx_ring[i],
2818 sizeof(struct wx_ring));
2819
2820 temp_ring[i].count = new_tx_count;
2821 err = wx_setup_tx_resources(&temp_ring[i]);
2822 if (err) {
2823 wx_err(wx, "setup new tx resources failed, keep using the old config\n");
2824 while (i) {
2825 i--;
2826 wx_free_tx_resources(&temp_ring[i]);
2827 }
2828 return;
2829 }
2830 }
2831
2832 for (i = 0; i < wx->num_tx_queues; i++) {
2833 wx_free_tx_resources(wx->tx_ring[i]);
2834
2835 memcpy(wx->tx_ring[i], &temp_ring[i],
2836 sizeof(struct wx_ring));
2837 }
2838
2839 wx->tx_ring_count = new_tx_count;
2840 }
2841
2842 /* Repeat the process for the Rx rings if needed */
2843 if (new_rx_count != wx->rx_ring_count) {
2844 for (i = 0; i < wx->num_rx_queues; i++) {
2845 memcpy(&temp_ring[i], wx->rx_ring[i],
2846 sizeof(struct wx_ring));
2847
2848 temp_ring[i].count = new_rx_count;
2849 err = wx_setup_rx_resources(&temp_ring[i]);
2850 if (err) {
2851 wx_err(wx, "setup new rx resources failed, keep using the old config\n");
2852 while (i) {
2853 i--;
2854 wx_free_rx_resources(&temp_ring[i]);
2855 }
2856 return;
2857 }
2858 }
2859
2860 for (i = 0; i < wx->num_rx_queues; i++) {
2861 wx_free_rx_resources(wx->rx_ring[i]);
2862 memcpy(wx->rx_ring[i], &temp_ring[i],
2863 sizeof(struct wx_ring));
2864 }
2865
2866 wx->rx_ring_count = new_rx_count;
2867 }
2868 }
2869 EXPORT_SYMBOL(wx_set_ring);
2870
2871 MODULE_DESCRIPTION("Common library for Wangxun(R) Ethernet drivers.");
2872 MODULE_LICENSE("GPL");
2873