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/Documentation/devicetree/bindings/serial/
Dmediatek,uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/mediatek,uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Universal Asynchronous Receiver/Transmitter (UART)
10 - Matthias Brugger <matthias.bgg@gmail.com>
13 - $ref: serial.yaml#
16 The MediaTek UART is based on the basic 8250 UART and compatible
23 - const: mediatek,mt6577-uart
24 - items:
[all …]
Dmvebu-uart.txt1 * Marvell UART : Non standard UART used in some of Marvell EBU SoCs
2 e.g., Armada-3700.
5 - compatible:
6 - "marvell,armada-3700-uart" for the standard variant of the UART
7 (32 bytes FIFO, no DMA, level interrupts, 8-bit access to the
9 - "marvell,armada-3700-uart-ext" for the extended variant of the
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
12 - reg: offset and length of the register set for the device.
13 - clocks: UART reference clock used to derive the baudrate. If no clock
14 is provided (possible only with the "marvell,armada-3700-uart"
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Damlogic,meson-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/serial/amlogic,meson-uart.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic Meson SoC UART Serial Interface
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Amlogic Meson SoC UART Serial Interface is present on a large range
15 of SoCs, and can be present either in the "Always-On" power domain or the
16 "Everything-Else" power domain.
18 The particularity of the "Always-On" Serial Interface is that the hardware
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Dsamsung_uart.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
14 Each Samsung UART should have an alias correctly numbered in the "aliases"
15 node, according to serialN format, where N is the port number (non-negative
21 - enum:
22 - apple,s5l-uart
[all …]
Dfsl-imx-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
10 - Fabio Estevam <festevam@gmail.com>
15 - const: fsl,imx1-uart
16 - const: fsl,imx21-uart
17 - items:
18 - enum:
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Dsnps-dw-apb-uart.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare ABP UART
10 - Rob Herring <robh@kernel.org>
13 - $ref: serial.yaml#
14 - $ref: rs485.yaml#
16 - if:
20 const: starfive,jh7110-uart
[all …]
Dsprd-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/serial/sprd-uart.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Spreadtrum serial UART
11 - Orson Zhai <orsonzhai@gmail.com>
12 - Baolin Wang <baolin.wang7@gmail.com>
13 - Chunyan Zhang <zhang.lyra@gmail.com>
18 - items:
19 - enum:
[all …]
Dbrcm,bcm7271-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/brcm,bcm7271-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Al Cooper <alcooperx@gmail.com>
13 - $ref: serial.yaml#
16 The Broadcom UART is based on the basic 8250 UART but with
23 - enum:
24 - brcm,bcm7271-uart
25 - brcm,bcm7278-uart
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D8250.yaml3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UART (Universal Asynchronous Receiver/Transmitter)
10 - devicetree@vger.kernel.org
13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if:
17 - required:
18 - aspeed,lpc-io-reg
19 - required:
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Dingenic,uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/ingenic,uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs UART controller
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: serial.yaml#
17 pattern: "^serial@[0-9a-f]+$"
21 - enum:
22 - ingenic,jz4740-uart
[all …]
D8250_omap.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vignesh Raghavendra <vigneshr@ti.com>
13 - $ref: /schemas/serial/serial.yaml#
14 - $ref: /schemas/serial/rs485.yaml#
19 - enum:
20 - ti,am3352-uart
21 - ti,am4372-uart
22 - ti,am654-uart
[all …]
Dcirrus,clps711x-uart.txt1 * Cirrus Logic CLPS711X Universal Asynchronous Receiver/Transmitter (UART)
4 - compatible: Should be "cirrus,ep7209-uart".
5 - reg: Address and length of the register set for the device.
6 - interrupts: Should contain UART TX and RX interrupt.
7 - clocks: Should contain UART core clock number.
8 - syscon: Phandle to SYSCON node, which contain UART control bits.
11 - {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD
14 Note: Each UART port should have an alias correctly numbered
22 uart1: uart@80000480 {
23 compatible = "cirrus,ep7312-uart","cirrus,ep7209-uart";
[all …]
Drenesas,em-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/renesas,em-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas EMMA Mobile UART Interface
10 - Magnus Damm <magnus.damm@gmail.com>
15 - items:
16 - enum:
17 - renesas,r9a09g011-uart # RZ/V2M
18 - const: renesas,em-uart # generic EMMA Mobile compatible UART
[all …]
Dsifive-serial.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive asynchronous serial interface (UART)
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
15 - $ref: serial.yaml#
20 - enum:
[all …]
Dcdns,uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/cdns,uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence UART Controller
10 - Michal Simek <michal.simek@amd.com>
15 - description: UART controller for Zynq-7xxx SoC
17 - const: xlnx,xuartps
18 - const: cdns,uart-r1p8
19 - description: UART controller for Zynq Ultrascale+ MPSoC
[all …]
Desp,esp32-uart.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/serial/esp,esp32-uart.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: ESP32xx UART controllers
11 - Max Filippov <jcmvbkbc@gmail.com>
14 ESP32 UART controller is a part of the ESP32 SoC.
15 ESP32S3 UART controller is a part of the ESP32S3 SoC.
19 - $ref: serial.yaml#
24 - esp,esp32-uart
[all …]
Darc-uart.txt1 * Synopsys ARC UART : Non standard UART used in some of the ARC FPGA boards
4 - compatible : "snps,arc-uart"
5 - reg : offset and length of the register set for the device.
6 - interrupts : device interrupt
7 - clock-frequency : the input clock frequency for the UART
8 - current-speed : baud rate for UART
13 compatible = "snps,arc-uart";
16 clock-frequency = <80000000>;
17 current-speed = <115200>;
Dserial.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
18 Each enabled UART may have an optional "serialN" alias in the "aliases" node,
19 where N is the port number (non-negative decimal integer) as printed on the
28 cts-gpios:
32 the UART's CTS line.
34 dcd-gpios:
[all …]
Dactions,owl-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/actions,owl-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Actions Semi Owl UART
10 - Kanak Shilledar <kanakshilledar111@protonmail.com>
13 - $ref: serial.yaml
18 - enum:
19 - actions,s500-uart
20 - actions,s900-uart
[all …]
Dst,stm32-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/st,stm32-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Erwan Le Ray <erwan.leray@foss.st.com>
15 - st,stm32-uart
16 - st,stm32f7-uart
17 - st,stm32h7-uart
32 description: label associated with this uart
34 st,hw-flow-ctrl:
[all …]
/Documentation/devicetree/bindings/dma/
Dmediatek,uart-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/mediatek,uart-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek UART APDMA controller
10 - Long Cheng <long.cheng@mediatek.com>
13 The MediaTek UART APDMA controller provides DMA capabilities
14 for the UART peripheral bus.
17 - $ref: dma-controller.yaml#
22 - items:
[all …]
/Documentation/devicetree/bindings/soc/aspeed/
Duart-routing.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 ---
6 $id: http://devicetree.org/schemas/soc/aspeed/uart-routing.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 title: Aspeed UART Routing Controller
12 - Oskar Senft <osk@google.com>
13 - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
16 The Aspeed UART routing control allow to dynamically route the inputs for
17 the built-in UARTS and physical serial I/O ports.
19 This allows, for example, to connect the output of UART to another UART.
[all …]
/Documentation/devicetree/bindings/clock/
Dmarvell,armada-3700-uart-clock.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/marvell,armada-3700-uart-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 title: Marvell Armada 3720 UART clocks
9 - Pali Rohár <pali@kernel.org>
13 const: marvell,armada-3700-uart-clock
17 - description: UART Clock Control Register
18 - description: UART 2 Baud Rate Divisor Register
22 List of parent clocks suitable for UART from following set:
[all …]
/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dserial.txt4 - fsl,cpm1-smc-uart
5 - fsl,cpm2-smc-uart
6 - fsl,cpm1-scc-uart
7 - fsl,cpm2-scc-uart
8 - fsl,qe-uart
11 property as described in booting-without-of.txt, section IX.1 in the following
23 compatible = "fsl,mpc8272-scc-uart",
24 "fsl,cpm2-scc-uart";
27 interrupt-parent = <&PIC>;
28 fsl,cpm-brg = <1>;
[all …]
/Documentation/w1/masters/
Dw1-uart.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
4 Kernel driver w1-uart
11 -----------
13 UART 1-Wire bus driver. The driver utilizes the UART interface via the
14 Serial Device Bus to create the 1-Wire timing patterns as described in
15 the document `"Using a UART to Implement a 1-Wire Bus Master"`_.
17 .. _"Using a UART to Implement a 1-Wire Bus Master": https://www.analog.com/en/technical-articles/u…
19 In short, the UART peripheral must support full-duplex and operate in
20 open-drain mode. The timing patterns are generated by a specific
21 combination of baud-rate and transmitted byte, which corresponds to a
[all …]

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