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| /Documentation/devicetree/bindings/net/ |
| D | mdio-mux-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
17 - $ref: /schemas/net/mdio-mux.yaml#
21 const: mdio-mux-gpio
30 - compatible
31 - gpios
36 - |
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| /Documentation/devicetree/bindings/pci/ |
| D | intel,ixp4xx-pci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/intel,ixp4xx-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
15 - $ref: /schemas/pci/pci-host-bridge.yaml#
20 - enum:
21 - intel,ixp42x-pci
22 - intel,ixp43x-pci
28 - description: IXP4xx-specific registers
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| D | faraday,ftpci100.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
18 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
19 Technology) and product ID 0x4321.
21 The plain variant has 128MiB of non-prefetchable memory space, whereas the
27 and should point to respective interrupt in that controller in its interrupt-map.
29 The code which is the only documentation of how the Faraday PCI (the non-dual
34 interrupt-map-mask = <0xf800 0 0 7>;
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| /Documentation/input/devices/ |
| D | elantech.rst | 4 Copyright (C) 2007-2008 Arjan Opmeer <arjan@opmeer.net>
17 3. Differentiating hardware versions
25 5.2.1 Parity checking and packet re-synchronization
27 5.2.3 Two finger touch
28 6. Hardware version 3
38 7.2.3 Motion packet
39 8. Trackpoint (for Hardware version 3 and 4)
50 hardware versions unimaginatively called version 1,version 2, version 3
54 and width of the touch. Hardware version 3 uses 6 bytes per packet (and
56 of up to 3 fingers. Hardware version 4 uses 6 bytes per packet, and can
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| /Documentation/devicetree/bindings/phy/ |
| D | apm-xgene-phy.txt | 1 * APM X-Gene 15Gbps Multi-purpose PHY nodes
3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
7 - compatible : Shall be "apm,xgene-phy".
8 - reg : PHY memory resource is the SDS PHY access resource.
9 - #phy-cells : Shall be 1 as it expects one argument for setting
10 the mode of the PHY. Possible values are 0 (SATA),
11 1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI).
14 - status : Shall be "ok" if enabled or "disabled" if disabled.
16 - clocks : Reference to the clock entry.
17 - apm,tx-eye-tuning : Manual control to fine tune the capture of the serial
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| /Documentation/userspace-api/media/v4l/ |
| D | pixfmt-rgb.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _pixfmt-rgb:
22 (including capture queues of mem-to-mem devices) fill the alpha component in
25 but can set the alpha bit to a user-configurable value, the
26 :ref:`V4L2_CID_ALPHA_COMPONENT <v4l2-alpha-component>` control is used to
31 :ref:`Output <output>` devices (including output queues of mem-to-mem devices
44 - In all the tables that follow, bit 7 is the most significant bit in a byte.
45 - 'r', 'g' and 'b' denote bits of the red, green and blue components
54 based on the order of the RGB components as seen in a 8-, 16- or 32-bit word,
57 for each component. For instance, the RGB565 format stores a pixel in a 16-bit
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| D | subdev-formats.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-mbus-format:
14 .. flat-table:: struct v4l2_mbus_framefmt
15 :header-rows: 0
16 :stub-columns: 0
19 * - __u32
20 - ``width``
21 - Image width in pixels.
22 * - __u32
23 - ``height``
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| /Documentation/driver-api/media/drivers/ccs/ |
| D | ccs-regs.asc | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2 # Copyright (C) 2019--2020 Intel Corporation
5 # - f field LSB MSB rflags
6 # - e enum value # after a field
7 # - e enum value [LSB MSB]
8 # - b bool bit
9 # - l arg name min max elsize [discontig...]
19 module_model_id 0x0000 16
20 module_revision_number_major 0x0002 8
21 frame_count 0x0005 8
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| /Documentation/devicetree/bindings/iio/proximity/ |
| D | semtech,sx9324.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gwendal Grignou <gwendal@chromium.org>
11 - Daniel Campello <campello@chromium.org>
17 - $ref: /schemas/iio/iio.yaml#
32 vdd-supply:
35 svdd-supply:
38 "#io-channel-cells":
41 semtech,ph0-pin:
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,imx6sx-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx6sx-iomuxc"
8 - fsl,pins: each entry consists of 6 integers and represents the mux and config
11 imx6sx-pinfunc.h under device tree source folder. The last integer CONFIG is
12 the pad setting value like pull-up on this pin. Please refer to i.MX6 SoloX
17 PAD_CTL_PUS_100K_DOWN (0 << 14)
20 PAD_CTL_PUS_22K_UP (3 << 14)
24 PAD_CTL_SPEED_LOW (0 << 6)
26 PAD_CTL_SPEED_HIGH (3 << 6)
27 PAD_CTL_DSE_DISABLE (0 << 3)
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| D | fsl,imx6sll-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx6sll-iomuxc"
8 - fsl,pins: each entry consists of 6 integers and represents the mux and config
11 imx6sll-pinfunc.h under device tree source folder. The last integer CONFIG is
12 the pad setting value like pull-up on this pin. Please refer to i.MX6SLL
18 PAD_CTL_PUS_100K_DOWN (0 << 14)
21 PAD_CTL_PUS_22K_UP (3 << 14)
25 PAD_CTL_SPEED_LOW (0 << 6)
27 PAD_CTL_SPEED_HIGH (3 << 6)
28 PAD_CTL_DSE_DISABLE (0 << 3)
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| D | fsl,imx6ul-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/fsl,imx6ul-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
17 - $ref: pinctrl.yaml#
22 - fsl,imx6ul-iomuxc
23 - fsl,imx6ull-iomuxc-snvs
42 be found in <arch/arm/boot/dts/imx6ul-pinfunc.h>. The last integer
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| D | fsl,imx6q-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx6q-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
11 pull-up for this pin. Please refer to imx6q datasheet for the valid pad
16 PAD_CTL_PUS_100K_DOWN (0 << 14)
19 PAD_CTL_PUS_22K_UP (3 << 14)
25 PAD_CTL_SPEED_HIGH (3 << 6)
26 PAD_CTL_DSE_DISABLE (0 << 3)
27 PAD_CTL_DSE_240ohm (1 << 3)
28 PAD_CTL_DSE_120ohm (2 << 3)
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| D | fsl,imx6dl-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx6dl-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
11 pull-up for this pin. Please refer to imx6dl datasheet for the valid pad
16 PAD_CTL_PUS_100K_DOWN (0 << 14)
19 PAD_CTL_PUS_22K_UP (3 << 14)
25 PAD_CTL_SPEED_HIGH (3 << 6)
26 PAD_CTL_DSE_DISABLE (0 << 3)
27 PAD_CTL_DSE_240ohm (1 << 3)
28 PAD_CTL_DSE_120ohm (2 << 3)
[all …]
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| D | fsl,imx6sl-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx6sl-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
11 pull-up for this pin. Please refer to imx6sl datasheet for the valid pad
17 PAD_CTL_PUS_100K_DOWN (0 << 14)
20 PAD_CTL_PUS_22K_UP (3 << 14)
26 PAD_CTL_SPEED_HIGH (3 << 6)
27 PAD_CTL_DSE_DISABLE (0 << 3)
28 PAD_CTL_DSE_240ohm (1 << 3)
29 PAD_CTL_DSE_120ohm (2 << 3)
[all …]
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| /Documentation/leds/ |
| D | leds-mlxcpld.rst | 10 -----------
14 - mlxcpld:fan1:green
15 - mlxcpld:fan1:red
16 - mlxcpld:fan2:green
17 - mlxcpld:fan2:red
18 - mlxcpld:fan3:green
19 - mlxcpld:fan3:red
20 - mlxcpld:fan4:green
21 - mlxcpld:fan4:red
22 - mlxcpld:psu:green
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| /Documentation/hwmon/ |
| D | dme1737.rst | 10 Addresses scanned: I2C 0x2c, 0x2d, 0x2e
18 Addresses scanned: none, address read from Super-I/O config space
26 Addresses scanned: I2C 0x2c, 0x2d, 0x2e
34 Addresses scanned: none, address read from Super-I/O config space
43 -----------------
52 Include non-standard LPC addresses 0x162e and 0x164e
55 - VIA EPIA SN18000
59 -----------
63 and SCH5127 Super-I/O chips. These chips feature monitoring of 3 temp sensors
64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
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| /Documentation/gpu/amdgpu/ |
| D | dgpu-asic-info-table.csv | 2 AMD Radeon (TM) HD 8500M/ 8600M /M200 /M320 /M330 /M335 Series, HAINAN, --, 6, --, --
3 AMD Radeon HD 7800 /7900 /FireGL Series, TAHITI, DCE 6, 6, VCE 1 / UVD 3, --
4 AMD Radeon R7 (TM|HD) M265 /M370 /8500M /8600 /8700 /8700M, OLAND, DCE 6, 6, VCE 1 / UVD 3, --
5 AMD Radeon (TM) (HD|R7) 7800 /7970 /8800 /8970 /370/ Series, PITCAIRN, DCE 6, 6, VCE 1 / UVD 3, --
6 …|R7|R9|HD) E8860 /M360 /7700 /7800 /8800 /9000(M) /W4100 Series, VERDE, DCE 6, 6, VCE 1 / UVD 3, --
9 AMD Radeon (TM) R(5|7) M315 /M340 /M360, TOPAZ, *, 8, --, 2
10 AMD Radeon (TM) R9 200 /380 /W7100 /S7150 /M390 /M395 Series, TONGA, DCE 10, 8, VCE 3 / UVD 5, 3
11 AMD Radeon (FirePro) (TM) R9 Fury Series, FIJI, DCE 10, 8, VCE 3 / UVD 6, 3
12 …/580 /590 Series - AMD Radeon (TM) (Pro WX) 5100 /E9390 /E9560 /E9565 /V7350 /7100 /P30PH, POLARIS…
13 …M) (RX|Pro WX) E9260 /460 /V5300X /550 /560(X) Series, POLARIS11, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3
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| /Documentation/translations/zh_CN/core-api/ |
| D | packing.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/core-api/packing.rst
22 --------
42 --------
46 - 将一个CPU可使用的数字打包到内存缓冲区中（具有硬件约束/特殊性）。
47 - 将内存缓冲区（具有硬件约束/特殊性）解压缩为一个CPU可使用的数字。
63 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
64 3 2 1 0
66 也就是说，CPU可使用的u64的MSByte(7)位于内存偏移量0处，而u64的LSByte(0)位于内存偏移量7处。
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| /Documentation/devicetree/bindings/iio/imu/ |
| D | adi,adis16475.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nuno Sá <nuno.sa@analog.com>
14 https://www.analog.com/media/en/technical-documentation/data-sheets/ADIS16475.pdf
19 - adi,adis16475-1
20 - adi,adis16475-2
21 - adi,adis16475-3
22 - adi,adis16477-1
23 - adi,adis16477-2
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpic-timer.txt | 4 - compatible: "fsl,mpic-global-timer"
6 - reg : Contains two regions. The first is the main timer register bank
10 - fsl,available-ranges: use <start count> style section to define which
14 - interrupts: one interrupt per timer in the group, in order, starting
15 with timer zero. If timer-available-ranges is present, only the
19 /* Note that this requires #interrupt-cells to be 4 */
21 compatible = "fsl,mpic-global-timer";
22 reg = <0x41100 0x100 0x41300 4>;
24 /* Another AMP partition is using timers 0 and 1 */
25 fsl,available-ranges = <2 2>;
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| /Documentation/tools/rtla/ |
| D | rtla-timerlat-top.rst | 2 rtla-timerlat-top
4 -------------------------------------------
6 -------------------------------------------
22 seem with the option **-T**.
35 **--aa-only** *us*
38 Print the auto-analysis if the system hits the stop tracing condition. This option
45 In the example below, the timerlat tracer is dispatched in cpus *1-23* in the
49 # timerlat -a 40 -c 1-23 -q
51 0 00:00:12 | IRQ Timer Latency (us) | Thread Timer Latency (us)
53 1 #12322 | 0 0 1 15 | 10 3 9 31
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| /Documentation/admin-guide/thermal/ |
| D | intel_powerclamp.rst | 6 - Arjan van de Ven <arjan@linux.intel.com>
7 - Jacob Pan <jacob.jun.pan@linux.intel.com>
12 - Goals and Objectives
15 - Idle Injection
16 - Calibration
19 - Effectiveness and Limitations
20 - Power vs Performance
21 - Scalability
22 - Calibration
23 - Comparison with Alternative Techniques
[all …]
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| /Documentation/networking/device_drivers/ethernet/3com/ |
| D | 3c509.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Linux and the 3Com EtherLink III Series Ethercards (driver v1.18c and higher)
8 of the 3c509 driver. You should not use the driver without reading this file.
20 The following are notes and information on using the 3Com EtherLink III series
21 ethercards in Linux. These cards are commonly known by the most widely-used
22 card's 3Com model number, 3c509. They are all 10mb/s ISA-bus cards and shouldn't
23 be (but sometimes are) confused with the similarly-numbered PCI-bus "3c905"
24 (aka "Vortex" or "Boomerang") series. Kernel support for the 3c509 family is
25 provided by the module 3c509.c, which has code to support all of the following
28 - 3c509 (original ISA card)
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| D | vortex.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 3Com Vortex device driver
12 This document describes the usage and errata of the 3Com "Vortex" device
13 driver for Linux, 3c59x.c.
20 - Andrew Morton
21 - Netdev mailing list <netdev@vger.kernel.org>
22 - Linux kernel mailing list <linux-kernel@vger.kernel.org>
28 Since kernel 2.3.99-pre6, this driver incorporates the support for the
29 3c575-series Cardbus cards which used to be handled by 3c575_cb.c.
33 - 3c590 Vortex 10Mbps
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