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| /Documentation/devicetree/bindings/net/ |
| D | samsung-sxgbe.txt | 4 - compatible: Should be "samsung,sxgbe-v2.0a"
5 - reg: Address and length of the register set for the device
6 - interrupts: Should contain the SXGBE interrupts
9 index 0 - this is fixed common interrupt of SXGBE and it is always
11 index 1 to 25 - 8 variable transmit interrupts, variable 16 receive interrupts
13 - phy-mode: String, operation mode of the PHY interface.
15 - samsung,pbl: Integer, Programmable Burst Length.
16 Supported values are 1, 2, 4, 8, 16, or 32.
17 - samsung,burst-map: Integer, Program the possible bursts supported by sxgbe
19 Allowable range is 0x01-0x3F. When this field is set fixed burst is enabled.
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| D | hisilicon-hns-dsaf.txt | 4 - compatible: should be "hisilicon,hns-dsaf-v1" or "hisilicon,hns-dsaf-v2".
5 "hisilicon,hns-dsaf-v1" is for hip05.
6 "hisilicon,hns-dsaf-v2" is for Hi1610 and Hi1612.
7 - mode: dsa fabric mode string. only support one of dsaf modes like these:
8 "2port-64vf",
9 "6port-16rss",
10 "6port-16vf",
11 "single-port".
12 - interrupts: should contain the DSA Fabric and rcb interrupt.
13 - reg: specifies base physical address(es) and size of the device registers.
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| /Documentation/devicetree/bindings/crypto/ |
| D | hisilicon,hip07-sec.txt | 4 - compatible: Must contain one of
5 - "hisilicon,hip06-sec"
6 - "hisilicon,hip07-sec"
7 - reg: Memory addresses and lengths of the memory regions through which
9 Region 0 has registers to control the backend processing engines.
11 Regions 2-18 have registers for the 16 individual queues which are isolated
13 - interrupts: Interrupt specifiers.
14 Refer to interrupt-controller/interrupts.txt for generic interrupt client node
16 Interrupt 0 is for the SEC unit error queue.
19 - dma-coherent: The driver assumes coherent dma is possible.
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| /Documentation/userspace-api/media/v4l/ |
| D | metafmt-vsp1-hgo.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgo:
9 Renesas R-Car VSP1 1-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1 1-D
20 computes the minimum, maximum and sum of all pixels as well as per-channel
28 - In *64 bins normal mode*, the HGO operates on the three channels independently
29 to compute three 64-bins histograms. RGB, YCbCr and HSV image formats are
31 - In *64 bins maximum mode*, the HGO operates on the maximum of the (R, G, B)
32 channels to compute a single 64-bins histogram. Only the RGB image format is
34 - In *256 bins normal mode*, the HGO operates on the Y channel to compute a
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| D | metafmt-vsp1-hgt.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgt:
9 Renesas R-Car VSP1 2-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1
16 2-D Histogram (HGT) engine.
28 The Saturation position **n** (0 - 31) of the bucket in the matrix is
33 The Hue position **m** (0 - 5) of the bucket in the matrix depends on
43 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5
50 5U 0L 0U 1L 1U 2L 2U 3L 3U 4L 4U 5L 5U 0L
51 <0..............................Hue Value............................255>
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| D | pixfmt-packed-yuv.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _packed-yuv:
15 - In all the tables that follow, bit 7 is the most significant bit in a byte.
16 - 'Y', 'Cb' and 'Cr' denote bits of the luma, blue chroma (also known as
22 4:4:4 Subsampling
28 The next table lists the packed YUV 4:4:4 formats with less than 8 bits per
30 seen in a 16-bit word, which is then stored in memory in little endian byte
32 format stores a pixel in a 16-bit word [15:0] laid out at as [Y'\ :sub:`4-0`
33 Cb\ :sub:`5-0` Cr\ :sub:`4-0`], and stored in memory in two bytes,
34 [Cb\ :sub:`2-0` Cr\ :sub:`4-0`] followed by [Y'\ :sub:`4-0` Cb\ :sub:`5-3`].
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| D | pixfmt-rgb.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _pixfmt-rgb:
22 (including capture queues of mem-to-mem devices) fill the alpha component in
25 but can set the alpha bit to a user-configurable value, the
26 :ref:`V4L2_CID_ALPHA_COMPONENT <v4l2-alpha-component>` control is used to
31 :ref:`Output <output>` devices (including output queues of mem-to-mem devices
44 - In all the tables that follow, bit 7 is the most significant bit in a byte.
45 - 'r', 'g' and 'b' denote bits of the red, green and blue components
54 based on the order of the RGB components as seen in a 8-, 16- or 32-bit word,
56 noted by the presence of bit 31 in the 4CC value), and on the number of bits
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| D | pixfmt-yuv-planar.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. planar-yuv:
12 - Semi-planar formats use two planes. The first plane is the luma plane and
16 - Fully planar formats use three planes to store the Y, Cb and Cr components
26 and applications that support the multi-planar API, described in
27 :ref:`planar-apis`. Unless explicitly documented as supporting non-contiguous
31 Semi-Planar YUV Formats
46 For non-contiguous formats, no constraints are enforced by the format on the
57 .. flat-table:: Overview of Semi-Planar YUV Formats
58 :header-rows: 1
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| D | subdev-formats.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-mbus-format:
14 .. flat-table:: struct v4l2_mbus_framefmt
15 :header-rows: 0
16 :stub-columns: 0
19 * - __u32
20 - ``width``
21 - Image width in pixels.
22 * - __u32
23 - ``height``
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| D | yuv-formats.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _yuv-formats:
29 direction are possible, common factors are 1 (no subsampling), 2 and 4, with
33 - `4:4:4`: No subsampling
34 - `4:2:2`: Horizontal subsampling by 2, no vertical subsampling
35 - `4:2:0`: Horizontal subsampling by 2, vertical subsampling by 2
36 - `4:1:1`: Horizontal subsampling by 4, no vertical subsampling
37 - `4:1:0`: Horizontal subsampling by 4, vertical subsampling by 4
42 - .. _yuv-chroma-centered:
49 - .. _yuv-chroma-cosited:
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| /Documentation/devicetree/bindings/nvmem/ |
| D | socionext,uniphier-efuse.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/socionext,uniphier-efuse.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Keiji Hayashibara <hayashibara.keiji@socionext.com>
11 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
14 - $ref: nvmem.yaml#
15 - $ref: nvmem-deprecated-cells.yaml#
19 const: socionext,uniphier-efuse
25 - compatible
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| /Documentation/input/devices/ |
| D | elantech.rst | 4 Copyright (C) 2007-2008 Arjan Opmeer <arjan@opmeer.net>
18 4. Hardware version 1
20 4.2 Native relative mode 4 byte packet format
21 4.3 Native absolute mode 4 byte packet format
25 5.2.1 Parity checking and packet re-synchronization
33 7. Hardware version 4
39 8. Trackpoint (for Hardware version 3 and 4)
51 and version 4. Version 1 is found in "older" laptops and uses 4 bytes per
56 of up to 3 fingers. Hardware version 4 uses 6 bytes per packet, and can
58 4 allows tracking up to 5 fingers.
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| D | sentelic.rst | 8 :Copyright: |copy| 2002-2011 Sentelic Corporation.
10 :Last update: Dec-07-2011
12 Finger Sensing Pad Intellimouse Mode (scrolling wheel, 4th and 5th buttons)
15 A) MSID 4: Scrolling wheel mode plus Forward page(4th button) and Backward
21 4. Issuing the "Get device ID" command (0xF2) and waits for the response;
22 5. FSP will respond 0x04.
27 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
28 BYTE |---------------|BYTE |---------------|BYTE|---------------|BYTE|---------------|
29 1 |Y|X|y|x|1|M|R|L| 2 |X|X|X|X|X|X|X|X| 3 |Y|Y|Y|Y|Y|Y|Y|Y| 4 | | |B|F|W|W|W|W|
30 |---------------| |---------------| |---------------| |---------------|
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| D | alps.rst | 1 ----------------------
3 ----------------------
6 ------------
8 ALPS touchpads, called versions 1, 2, 3, 4, 5, 6, 7 and 8.
10 Since roughly mid-2010 several new ALPS touchpads have been released and
14 adequate. The design choices were to re-define the alps_model_data
29 ---------
32 E8-E6-E6-E6-E9. An ALPS touchpad should respond with either 00-00-0A or
33 00-00-64 if no buttons are pressed. The bits 0-2 of the first byte will be 1s
37 report" sequence: E8-E7-E7-E7-E9. The response is the model signature and is
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| /Documentation/devicetree/bindings/dma/ |
| D | milbeaut-m10v-hdmac.txt | 4 - device to memory transfer
5 - memory to device transfer
8 - compatible: Should be "socionext,milbeaut-m10v-hdmac"
9 - reg: Should contain DMA registers location and length.
10 - interrupts: Should contain all of the per-channel DMA interrupts.
11 Number of channels is configurable - 2, 4 or 8, so
12 the number of interrupts specified should be {2,4,8}.
13 - #dma-cells: Should be 1. Specify the ID of the slave.
14 - clocks: Phandle to the clock used by the HDMAC module.
19 hdmac1: dma-controller@1e110000 {
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| D | socionext,uniphier-mio-dmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/dma/socionext,uniphier-mio-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Masahiro Yamada <yamada.masahiro@socionext.com>
17 - $ref: dma-controller.yaml#
21 const: socionext,uniphier-mio-dmac
29 The number of interrupt lines is SoC-dependent.
37 '#dma-cells':
42 - compatible
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| /Documentation/devicetree/bindings/mips/lantiq/ |
| D | rcu.txt | 5 where each sub-device has its own set of registers.
14 -------------------------------------------------------------------------------
16 - compatible : The first and second values must be:
17 "lantiq,xrx200-rcu", "simple-mfd", "syscon"
18 - reg : The address and length of the system control registers
21 -------------------------------------------------------------------------------
24 compatible = "lantiq,xrx200-rcu", "simple-mfd", "syscon";
25 reg = <0x203000 0x100>;
26 ranges = <0x0 0x203000 0x100>;
27 big-endian;
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| /Documentation/translations/zh_CN/core-api/ |
| D | packing.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/core-api/packing.rst
22 --------
42 --------
46 - 将一个CPU可使用的数字打包到内存缓冲区中（具有硬件约束/特殊性）。
47 - 将内存缓冲区（具有硬件约束/特殊性）解压缩为一个CPU可使用的数字。
62 7 6 5 4
63 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
64 3 2 1 0
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| /Documentation/driver-api/media/drivers/ccs/ |
| D | ccs-regs.asc | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2 # Copyright (C) 2019--2020 Intel Corporation
5 # - f field LSB MSB rflags
6 # - e enum value # after a field
7 # - e enum value [LSB MSB]
8 # - b bool bit
9 # - l arg name min max elsize [discontig...]
19 module_model_id 0x0000 16
20 module_revision_number_major 0x0002 8
21 frame_count 0x0005 8
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| /Documentation/devicetree/bindings/scsi/ |
| D | hisilicon-sas.txt | 6 - compatible : value should be as follows:
7 (a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset
8 (b) "hisilicon,hip06-sas-v2" for v2 hw in hip06 chipset
9 (c) "hisilicon,hip07-sas-v2" for v2 hw in hip07 chipset
10 - sas-addr : array of 8 bytes for host SAS address
11 - reg : Contains two regions. The first is the address and length of the SAS
15 - hisilicon,sas-syscon: phandle of syscon used for sas control
16 - ctrl-reset-reg : offset to controller reset register in ctrl reg
17 - ctrl-reset-sts-reg : offset to controller reset status register in ctrl reg
18 - ctrl-clock-ena-reg : offset to controller clock enable register in ctrl reg
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| /Documentation/devicetree/bindings/sound/ |
| D | qcom,wcd937x-sdw.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,wcd937x-sdw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9370/WCD9375 Codec is a standalone Hi-Fi audio codec IC.
24 qcom,tx-port-mapping:
29 Supports maximum 4 tx soundwire ports.
34 WCD9370 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4
36 $ref: /schemas/types.yaml#/definitions/uint32-array
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | fsl,intmux.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,intmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - NXP Linux Team <linux-imx@nxp.com>
15 const: fsl,imx-intmux
27 interrupt-controller: true
29 '#interrupt-cells':
37 clock-names:
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| /Documentation/hwmon/ |
| D | xdpe12284.rst | 1 .. SPDX-License-Identifier: GPL-2.0
25 -----------
27 This driver implements support for Infineon Multi-phase XDPE112 and XDPE122
32 - Intel VR13 and VR13HC rev 1.3, IMVP8 rev 1.2 and IMPVP9 rev 1.3 DC-DC
34 - Intel SVID rev 1.9. protocol.
35 - PMBus rev 1.3 interface.
41 - VR12.0 mode, 5-mV DAC - 0x01.
42 - VR12.5 mode, 10-mV DAC - 0x02.
43 - IMVP9 mode, 5-mV DAC - 0x03.
44 - AMD mode 6.25mV - 0x10.
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | tda1997x.txt | 1 Device-Tree bindings for the NXP TDA1997x HDMI receiver
6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
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| /Documentation/core-api/ |
| D | packing.rst | 6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
37 into a CPU-usable number.
48 The byte offsets in the packed buffer are always implicitly 0, 1, ... 7.
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