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/Documentation/userspace-api/media/v4l/
Dpixfmt-indexed.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _pixfmt-indexed:
6 Indexed Format
16 .. flat-table:: Indexed Image Format
17 :header-rows: 2
18 :stub-columns: 0
20 * - Identifier
21 - Code
22 -
23 - :cspan:`7` Byte 0
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Dvidioc-subdev-enum-frame-size.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_SUBDEV_ENUM_FRAME_SIZE - Enumerate media bus frame sizes
35 supported by a sub-device on the specified pad
41 The enumerations are defined by the driver, and indexed using the ``index`` field
44 Each enumeration starts with the ``index`` of 0, and
50 and set ``index`` to 0.
59 Sub-devices that only support discrete frame sizes (such as most
64 supported. For instance, a scaler that uses a fixed-point scaling ratio
68 sub-device for an exact supported frame size.
71 pads of the sub-device, as well as on the current active links and the
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Dvidioc-subdev-enum-mbus-code.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_SUBDEV_ENUM_MBUS_CODE - Enumerate media bus formats
37 The enumerations are defined by the driver, and indexed using the ``index`` field
39 Each enumeration starts with the ``index`` of 0, and
42 Therefore, to enumerate media bus formats available at a given sub-device pad,
44 and set ``index`` to 0.
58 other pads of the sub-device, as well as on the current active links.
66 .. flat-table:: struct v4l2_subdev_mbus_code_enum
67 :header-rows: 0
68 :stub-columns: 0
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/Documentation/devicetree/bindings/timer/
Djcore,pit.txt1 J-Core Programmable Interval Timer and Clocksource
5 - compatible: Must be "jcore,pit".
7 - reg: Memory region(s) for timer/clocksource registers. For SMP,
8 there should be one region per cpu, indexed by the sequential,
9 zero-based hardware cpu number.
11 - interrupts: An interrupt to assign for the timer. The actual pit
22 reg = < 0x200 0x30 0x500 0x30 >;
23 interrupts = < 0x48 >;
Drenesas,mtu2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Multi-Function Timer Pulse Unit 2 (MTU2)
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 The MTU2 is a multi-purpose, multi-channel timer/counter with configurable clock inputs
18 independent. The MTU2 hardware supports five channels indexed from 0 to 4.
23 - enum:
24 - renesas,mtu2-r7s72100 # RZ/A1H
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/Documentation/devicetree/bindings/interrupt-controller/
Djcore,aic.txt1 J-Core Advanced Interrupt Controller
5 - compatible: Should be "jcore,aic1" for the (obsolete) first-generation aic
9 - reg: Memory region(s) for configuration. For SMP, there should be one
10 region per cpu, indexed by the sequential, zero-based hardware cpu
13 - interrupt-controller: Identifies the node as an interrupt controller
15 - #interrupt-cells: Specifies the number of cells needed to encode an
21 aic: interrupt-controller@200 {
23 reg = < 0x200 0x30 0x500 0x30 >;
24 interrupt-controller;
25 #interrupt-cells = <1>;
/Documentation/devicetree/bindings/clock/st/
Dst,clkgen-mux.txt3 This binding supports only simple indexed multiplexers, it does not
8 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - compatible : shall be:
13 "st,stih407-clkgen-a9-mux"
15 - #clock-cells : from common clock binding; shall be set to 0.
17 - reg : A Base address and length of the register set.
19 - clocks : from common clock binding
23 clk_m_a9: clk-m-a9@92b0000 {
24 #clock-cells = <0>;
25 compatible = "st,stih407-clkgen-a9-mux";
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/Documentation/devicetree/bindings/hwlock/
Dti,omap-hwspinlock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/hwlock/ti,omap-hwspinlock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
15 - ti,omap4-hwspinlock # for OMAP44xx, OMAP54xx, AM33xx, AM43xx, DRA7xx SoCs
16 - ti,am64-hwspinlock # for K3 AM64x SoCs
17 - ti,am654-hwspinlock # for K3 AM65x, J721E and J7200 SoCs
22 "#hwlock-cells":
25 The OMAP hwspinlock users will use a 0-indexed relative hwlock number as
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/Documentation/devicetree/bindings/iio/health/
Dmaxim,max30100.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matt Ranostay <matt.ranostay@konsulko.com>
23 maxim,led-current-microamp:
27 LED current whilst the engine is running. First indexed value is
33 - compatible
34 - reg
35 - interrupts
38 - |
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/Documentation/driver-api/iio/
Dcore.rst8 :file:`drivers/iio/industrialio-*`
11 ----------------------
13 * struct iio_dev - industrial I/O device
14 * iio_device_alloc() - allocate an :c:type:`iio_dev` from a driver
15 * iio_device_free() - free an :c:type:`iio_dev` from a driver
16 * iio_device_register() - register a device with the IIO subsystem
17 * iio_device_unregister() - unregister a device from the IIO
63 :file:`Documentation/ABI/testing/sysfs-bus-iio` file in the Linux kernel
69 struct iio_chan_spec - specification of a single channel
112 * set **.indexed** field of :c:type:`iio_chan_spec` to 1. In this case the
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/Documentation/devicetree/bindings/iommu/
Dti,omap-iommu.txt4 - compatible : Should be one of,
5 "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances
6 "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances
7 "ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances
8 "ti,dra7-iommu" for DRA7xx IOMMU instances
9 - ti,hwmods : Name of the hwmod associated with the IOMMU instance
10 - reg : Address space for the configuration registers
11 - interrupts : Interrupt specifier for the IOMMU instance
12 - #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices,
19 - ti,#tlb-entries : Number of entries in the translation look-aside buffer.
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/Documentation/devicetree/bindings/firmware/
Darm,scpi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sudeep Holla <sudeep.holla@arm.com>
15 0922B ("ARM Compute Subsystem SCP: Message Interface Protocols")[0] can be
21 [0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html
29 SCPI compliant firmware complying to SCPI v1.0 and above OR
31 prior to SCPI v1.0
33 - const: arm,scpi # SCPI v1.0 and above
34 - const: arm,scpi-pre-1.0 # Unversioned SCPI before v1.0
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/Documentation/ABI/stable/
Dsysfs-fs-orangefs13 echo a 0 or a 1 into perf_counter_reset to
40 other N-1 intervals remain available.
55 is an indexed buffer in the shared
/Documentation/admin-guide/mm/
Dpagemap.rst12 physical frame each virtual page is mapped to. It contains one 64-bit
16 * Bits 0-54 page frame number (PFN) if present
17 * Bits 0-4 swap type if swapped
18 * Bits 5-54 swap offset if swapped
19 * Bit 55 pte is soft-dirty (see
20 Documentation/admin-guide/mm/soft-dirty.rst)
22 * Bit 57 pte is uffd-wp write-protected (since 5.13) (see
23 Documentation/admin-guide/mm/userfaultfd.rst)
25 * Bits 59-60 zero
26 * Bit 61 page is file-page or shared-anon (since 3.5)
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/Documentation/virt/kvm/devices/
Darm-vgic-its.rst1 .. SPDX-License-Identifier: GPL-2.0
10 The ITS allows MSI(-X) interrupts to be injected into guests. This extension is
12 arm-vgic-v3.txt), but does not depend on having physical ITS controllers.
15 a separate, non-overlapping MMIO region.
22 -------------------------
25 KVM_VGIC_ITS_ADDR_TYPE (rw, 64-bit)
33 -E2BIG Address outside of addressable IPA range
34 -EINVAL Incorrectly aligned address
35 -EEXIST Address already configured
36 -EFAULT Invalid user pointer for attr->addr.
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Dxics.rst1 .. SPDX-License-Identifier: GPL-2.0
13 One per interrupt source, indexed by the source number.
25 -EINVAL Value greater than KVM_MAX_VCPU_IDS.
26 -EFAULT Invalid user pointer for attr->addr.
27 -EBUSY A vcpu is already connected to the device.
32 sources, each identified by a 20-bit source number, and a set of
37 capability for each vcpu, specifying KVM_CAP_IRQ_XICS in args[0] and
43 least-significant end of the word:
50 * Pending IPI (inter-processor interrupt) priority, 8 bits
64 bitfields, starting from the least-significant end of the word:
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/Documentation/devicetree/bindings/soc/qcom/
Dqcom,smsm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
25 '#address-cells':
28 qcom,local-host:
30 default: 0
42 (0-indexed).
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/Documentation/driver-api/cxl/
Daccess-coordinates.rst1 .. SPDX-License-Identifier: GPL-2.0
31 > CFMWS 0
35 > ACPI0017-0 ACPI0017-1
36 > GP0/HB0/ACPI0016-0 GP1/HB1/ACPI0016-1
40 > SW 0 SW 1 SW 2 SW 3
47 Min(SW 0 Upstream Link to RP0 BW,
68 'struct cxl_perf_ctx' in the xarray indexed by a device pointer. If the
/Documentation/core-api/
Dcachetlb.rst25 virtual-->physical address translations obtained from the software
59 modifications for the address space 'vma->vm_mm' in the range
60 'start' to 'end-1' will be visible to the cpu. That is, after
62 virtual addresses in the range 'start' to 'end-1'.
78 address space is available via vma->vm_mm. Also, one may
79 test (vma->vm_flags & VM_EXEC) to see if this region is
81 split-tlb type setups).
84 page table modification for address space 'vma->vm_mm' for
87 'vma->vm_mm' for virtual address 'addr'.
97 in the software page tables for address space "vma->vm_mm"
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/Documentation/filesystems/
Dorangefs.rst1 .. SPDX-License-Identifier: GPL-2.0
7 OrangeFS is an LGPL userspace scale-out parallel storage system. It is ideal
51 On Fedora, install orangefs and orangefs-server::
53 dnf -y install orangefs orangefs-server
64 pvfs2-client-core.
68 pvfs2-server -f /etc/orangefs/orangefs.conf
72 systemctl start orangefs-server
76 pvfs2-ping -m /pvfsmnt
81 systemctl start orangefs-client
85 mount -t pvfs2 tcp://localhost:3334/orangefs /pvfsmnt
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/Documentation/userspace-api/media/drivers/
Ddw100.rst1 .. SPDX-License-Identifier: GPL-2.0
11 pixel macroblocks indexed using X, Y vertex coordinates.
15 <--------------------------------------->
17 ^ .-------.-------.-------.-------.-------.
21 a | .-------.-------.-------.-------.-------.
25 h | .-------.-------.-------.-------.-------.
29 h | .-------.-------.-------.-------.-------.
33 v '-------'-------'-------'-------'-------'
42 .----------------------.--------..----------------------.--------.
43 | 31~20 | 19~16 || 15~4 | 3~0 |
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/Documentation/admin-guide/device-mapper/
Dunstriped.rst2 Device-mapper "unstriped" target
8 The device-mapper "unstriped" target provides a transparent mechanism to
9 unstripe a device-mapper "striped" target to access the underlying disks
10 without having to touch the true backing block-device. It can also be
11 used to unstripe a hardware RAID-0 to access backing disks.
17 The number of stripes in the RAID 0.
27 drive you wish to unstripe. This must be 0 indexed.
33 An example of undoing an existing dm-stripe
34 -------------------------------------------
47 SEQ_END=$((${NUM}-1))
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/Documentation/devicetree/bindings/pinctrl/
Drenesas,rza1-ports.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis
17 writing configuration values to per-port register sets.
25 - const: renesas,r7s72100-ports # RZ/A1H
26 - items:
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/Documentation/bpf/
Dmap_cpumap.rst1 .. SPDX-License-Identifier: GPL-2.0-only
9 - ``BPF_MAP_TYPE_CPUMAP`` was introduced in kernel version 4.15
11 .. kernel-doc:: kernel/bpf/cpumap.c
14 An example use-case for this map type is software based Receive Side Scaling (RSS).
16 The CPUMAP represents the CPUs in the system indexed as the map-key, and the
17 map-value is the config setting (per CPUMAP entry). Each CPUMAP entry has a dedicated
32 ----------
35 .. code-block:: c
47 ----------
55 .. code-block:: c
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/Documentation/devicetree/bindings/regulator/
Dti-abb-regulator.txt4 - compatible: Should be one of:
5 - "ti,abb-v1" for older SoCs like OMAP3
6 - "ti,abb-v2" for newer SoCs like OMAP4, OMAP5
7 - "ti,abb-v3" for a generic definition where setup and control registers are
9 - reg: Address and length of the register set for the device. It contains
10 the information of registers in the same order as described by reg-names
11 - reg-names: Should contain the reg names
12 - "base-address" - contains base address of ABB module (ti,abb-v1,ti,abb-v2)
13 - "control-address" - contains control register address of ABB module (ti,abb-v3)
14 - "setup-address" - contains setup register address of ABB module (ti,abb-v3)
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