| /Documentation/hwmon/ |
| D | mc13783-adc.rst | 47 0 Battery Voltage (BATT) 2.50 - 4.65V -2.40V
49 2 Application Supply (BP) 2.50 - 4.65V -2.40V
50 3 Charger Voltage (CHRGRAW) 0 - 10V / /5
51 0 - 20V /10
52 4 Charger Current (CHRGISNSP-CHRGISNSN) -0.25 - 0.25V x4
53 5 General Purpose ADIN5 / Battery Pack Thermistor 0 - 2.30V No
54 6 General Purpose ADIN6 / Backup Voltage (LICELL) 0 - 2.30V / No /
55 1.50 - 3.50V -1.20V
56 7 General Purpose ADIN7 / UID / Die Temperature 0 - 2.30V / No /
57 0 - 2.55V / x0.9 / No
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| D | dme1737.rst | 10 Addresses scanned: I2C 0x2c, 0x2d, 0x2e
26 Addresses scanned: I2C 0x2c, 0x2d, 0x2e
52 Include non-standard LPC addresses 0x162e and 0x164e
64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
94 in0: +5VTR (+5V standby) 0V - 6.64V
95 in1: Vccp (processor core) 0V - 3V
96 in2: VCC (internal +3.3V) 0V - 4.38V
97 in3: +5V 0V - 6.64V
98 in4: +12V 0V - 16V
99 in5: VTR (+3.3V standby) 0V - 4.38V
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| D | ltc4245.rst | 10 Addresses scanned: 0x20-0x3f
34 Example: the following will load the driver for an LTC4245 at address 0x23
38 $ echo ltc4245 0x23 > /sys/bus/i2c/devices/i2c-1/new_device
52 in1_input 12v input voltage (mV)
53 in2_input 5v input voltage (mV)
54 in3_input 3v input voltage (mV)
55 in4_input Vee (-12v) input voltage (mV)
57 in1_min_alarm 12v input undervoltage alarm
58 in2_min_alarm 5v input undervoltage alarm
59 in3_min_alarm 3v input undervoltage alarm
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| D | smsc47m192.rst | 10 Addresses scanned: I2C 0x2c - 0x2d
46 each voltage channel is 0V ... 255/192*(nominal voltage), the resolution
51 The +12V analog voltage input channel (in4_input) is multiplexed with
53 a +12V voltage measurement or a 5 bit CPU VID, but not both.
54 The default setting is to use the pin as 12V input, and use only 4 bit VID.
67 in0_input +2.5V voltage input
68 in1_input CPU voltage input (nominal 2.25V)
69 in2_input +3.3V voltage input
70 in3_input +5V voltage input
71 in4_input +12V voltage input (may be missing if used as VID4)
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| D | max197.rst | 25 The A/D converters MAX197, and MAX199 are both 8-Channel, Multi-Range, 5V,
28 The available ranges for the MAX197 are {0,-5V} to 5V, and {0,-10V} to 10V,
29 while they are {0,-2V} to 2V, and {0,-4V} to 4V on the MAX199.
51 2,1,0 A2,A1,A0 Channel
58 in[0-7]_input The conversion value for the corresponding channel.
61 in[0-7]_min The lower limit (in mV) for the corresponding channel.
62 For the MAX197, it will be adjusted to -10000, -5000, or 0.
63 For the MAX199, it will be adjusted to -4000, -2000, or 0.
66 in[0-7]_max The higher limit (in mV) for the corresponding channel.
67 For the MAX197, it will be adjusted to 0, 5000, or 10000.
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| /Documentation/devicetree/bindings/iio/dac/ |
| D | adi,ltc2664.yaml | 14 Analog Devices LTC2664 4 channel, 12-/16-Bit, +-10V DAC
31 v-pos-supply:
34 v-neg-supply:
61 0 - MPS2=GND, MPS1=GND, MSP0=GND (+-10V, reset to 0V)
62 1 - MPS2=GND, MPS1=GND, MSP0=VCC (+-5V, reset to 0V)
63 2 - MPS2=GND, MPS1=VCC, MSP0=GND (+-2.5V, reset to 0V)
64 3 - MPS2=GND, MPS1=VCC, MSP0=VCC (0V to 10, reset to 0V)
65 4 - MPS2=VCC, MPS1=GND, MSP0=GND (0V to 10V, reset to 5V)
66 5 - MPS2=VCC, MPS1=GND, MSP0=VCC (0V to 5V, reset to 0V)
67 6 - MPS2=VCC, MPS1=VCC, MSP0=GND (0V to 5V, reset to 2.5V)
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| D | adi,ad3552r.yaml | 46 internal reference will be used. External reference must be 2.5V
49 description: Vref I/O driven by internal vref to 2.5V. If not set, Vref pin
56 - 0: low SDO drive strength.
61 enum: [0, 1, 2, 3]
67 const: 0
70 "^channel@([0-1])$":
79 enum: [0, 1]
102 enum: [0, 1, 2, 3]
107 enum: [0, 1, 2, 3]
140 "^channel@([0-1])$":
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| /Documentation/devicetree/bindings/sound/ |
| D | cs35l32.txt | 8 of the AD0 pin. Level 0 is 0x40 while Level 1 is 0x41.
19 0 = Automatically managed. Boost-converter output voltage is the higher
25 3 = Boost voltage fixed at 5 V.
29 0 = Left/right channels VMON[11:0], IMON[11:0], VPMON[7:0].
30 1 = Left/right channels VMON[11:0], IMON[11:0], STATUS.
31 2 = (Default) left/right channels VMON[15:0], IMON [15:0].
32 3 = Left/right channels VPMON[7:0], STATUS.
36 0 = (Default) One IC.
40 0 = 3.1V
41 1 = 3.2V
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| D | ti,ts3a227e.yaml | 17 headset specification v1.0.
25 const: 0x3b
34 - 0 # 2.1 V
35 - 1 # 2.2 V
36 - 2 # 2.3 V
37 - 3 # 2.4 V
38 - 4 # 2.5 V
39 - 5 # 2.6 V
40 - 6 # 2.7 V
41 - 7 # 2.8 V
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| D | fsl,sgtl5000.yaml | 23 const: 0
44 values of 2k, 4k or 8k. If set to 0 it will be off. If this node is not
47 enum: [ 0, 2, 4, 8 ]
51 values from 1.25V to 3V by 250mV steps. If this node is not mentioned
52 or the value is unknown, then the value is set to 1.25V.
58 The LRCLK pad strength. Possible values are: 0, 1, 2 and 3 as per the
61 VDDIO 1.8V 2.5V 3.3V
62 0 = Disable
67 enum: [ 0, 1, 2, 3 ]
71 The SCLK pad strength. Possible values are: 0, 1, 2 and 3 as per the
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| D | adi,max98396.yaml | 13 The MAX98396 is a mono Class-DG speaker amplifier with I/V sense.
28 description: A 1.8V supply that powers up the AVDD pin.
31 description: A 1.2V supply that powers up the DVDD pin.
34 description: A 1.2V or 1.8V supply that powers up the VDDIO pin.
37 description: A 3.0V to 20V supply that powers up the PVDD pin.
40 description: A 3.3V to 5.5V supply that powers up the VBAT pin.
45 minimum: 0
47 default: 0
52 minimum: 0
59 minimum: 0
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | samsung,s5k5baf.yaml | 39 description: Analog power supply 2.8V (2.6V to 3.0V)
42 description: I/O power supply 1.8V (1.65V to 1.95V) or 2.8V (2.5V to 3.1V)
46 Regulator input power supply 1.8V (1.7V to 1.9V) or 2.8V (2.6V to 3.0)
80 #size-cells = <0>;
84 reg = <0x2d>;
85 clocks = <&camera 0>;
89 stbyn-gpios = <&gpl2 0 GPIO_ACTIVE_LOW>;
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| D | thine,thp7312.yaml | 38 minimum: 0
42 Boot mode of the THP7312, reflecting the value of the BOOT[0] pin strap.
43 0 is for the SPI/2-wire slave boot, 1 is for the SPI master boot (from
54 1.2V supply for core, PLL, MIPI rx and MIPI tx.
58 Supply for input (RX). 1.8V for MIPI, or 1.8/2.8/3.3V for parallel.
62 Supply for output (TX). 1.8V for MIPI, or 1.8/2.8/3.3V for parallel.
66 Supply for host interface. 1.8V, 2.8V, or 3.3V.
70 Supply for sensor interface. 1.8V, 2.8V, or 3.3V.
72 vddgpio-0-supply:
74 Supply for GPIO_0. 1.8V, 2.8V, or 3.3V.
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| /Documentation/userspace-api/media/v4l/ |
| D | pixfmt-packed-hsv.rst | 14 The *saturation* (s) and the *value* (v) are measured in percentage of the
15 cylinder: 0 being the smallest value and 255 the maximum.
33 :stub-columns: 0
38 - :cspan:`7` Byte 0 in memory
52 - 0
61 - 0
70 - 0
79 - 0
101 - h\ :sub:`0`
110 - s\ :sub:`0`
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| D | subdev-formats.rst | 15 :header-rows: 0
16 :stub-columns: 0
122 :header-rows: 0
123 :stub-columns: 0
129 - 0x0001
224 :stub-columns: 0
265 - 0
269 - 0x1016
294 - r\ :sub:`0`
298 - g\ :sub:`0`
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| /Documentation/virt/hyperv/ |
| D | clocks.rst | 8 On arm64, Hyper-V virtualizes the ARMv8 architectural system counter
12 architectural system counter is functional in guest VMs on Hyper-V.
13 While Hyper-V also provides a synthetic system clock and four synthetic
15 Linux kernel in a Hyper-V guest on arm64. However, older versions
16 of Hyper-V for arm64 only partially virtualize the ARMv8
19 Linux kernel versions on these older Hyper-V versions requires an
20 out-of-tree patch to use the Hyper-V synthetic clocks/timers instead.
24 On x86/x64, Hyper-V provides guest VMs with a synthetic system clock
25 and four synthetic per-CPU timers as described in the TLFS. Hyper-V
29 Hyper-V performs TSC calibration, and provides the TSC frequency
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| D | vpci.rst | 5 In a Hyper-V guest VM, PCI pass-thru devices (also called
16 Hyper-V terminology for vPCI devices is "Discrete Device
17 Assignment" (DDA). Public documentation for Hyper-V DDA is
20 .. _DDA: https://learn.microsoft.com/en-us/windows-server/virtualization/hyper-v/plan/plan-for-depl…
25 driver to interact directly with the hardware. See Hyper-V
35 Hyper-V provides full PCI functionality for a vPCI device when
40 its integration with the Linux PCI subsystem must use Hyper-V
41 specific mechanisms. Consequently, vPCI devices on Hyper-V
62 VMBus connection to the vPCI VSP on the Hyper-V host. That
76 PCI device setup follows a sequence that Hyper-V originally
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| /Documentation/litmus-tests/atomic/ |
| D | Atomic-RMW-ops-are-atomic-WRT-atomic_set.litmus | 11 atomic_t v = ATOMIC_INIT(1);
14 P0(atomic_t *v)
16 (void)atomic_add_unless(v, 1, 0);
19 P1(atomic_t *v)
21 atomic_set(v, 0);
25 (v=2)
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | chipone,icn6211.yaml | 40 description: A 1.8V/2.5V/3.3V supply that power the MIPI RX.
43 description: A 1.8V/2.5V/3.3V supply that power the PLL.
46 description: A 1.8V/2.5V/3.3V supply that power the RGB output.
52 port@0:
95 #size-cells = <0>;
97 bridge@0 {
99 reg = <0>;
100 enable-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* LCD-RST: PL5 */
104 #size-cells = <0>;
106 port@0 {
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| D | lontium,lt8912b.yaml | 31 port@0:
55 - port@0
59 description: A 1.8V supply that powers the HDMI PLL.
62 description: A 1.8V supply that powers the HDMI TX part.
65 description: A 1.8V supply that powers the LVDS PLL.
68 description: A 1.8V supply that powers the LVDS TX part.
71 description: A 1.8V supply that powers the MIPI RX part.
74 description: A 1.8V supply that powers the SYSCLK.
77 description: A 1.8V supply that powers the digital part.
93 #size-cells = <0>;
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| /Documentation/ |
| D | atomic_t.txt | 94 atomic_t v = ATOMIC_INIT(1);
97 P0(atomic_t *v)
99 (void)atomic_add_unless(v, 1, 0);
102 P1(atomic_t *v)
104 atomic_set(v, 0);
108 (v=2)
123 atomic_add_unless(v, 1, 0);
125 ret = READ_ONCE(v->counter); // == 1
126 atomic_set(v, 0);
127 if (ret != u) WRITE_ONCE(v->counter, 0);
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| /Documentation/arch/riscv/ |
| D | hwprobe.rst | 3 RISC-V Hardware Probing Interface
6 The RISC-V hardware probing interface is based around a single syscall, which
22 will be cleared to -1, and its value set to 0. The CPU set is defined by
27 Usermode can supply NULL for ``cpus`` and 0 for ``cpusetsize`` as a shortcut for
44 On success 0 is returned, on failure a negative error code is returned.
49 as defined by the RISC-V privileged architecture specification.
52 defined by the RISC-V privileged architecture specification.
55 defined by the RISC-V privileged architecture specification.
76 minimumNumber/maximumNumber, not minNum/maxNum") of the RISC-V ISA manual.
79 by version 2.2 of the RISC-V ISA manual.
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| /Documentation/devicetree/bindings/mfd/ |
| D | maxim,max8998.yaml | 46 enum: [0, 1, 2, 3]
47 default: 0
54 enum: [0, 1]
55 default: 0
108 "^(LDO([2-9]|1[0-7])|BUCK[1-4])$":
150 #size-cells = <0>;
154 reg = <0x66>;
158 pinctrl-0 = <&lp3974_irq>;
160 max8998,pmic-buck1-default-dvs-idx = <0>;
165 max8998,pmic-buck2-default-dvs-idx = <0>;
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| /Documentation/devicetree/bindings/mmc/ |
| D | nvidia,tegra20-sdhci.yaml | 113 description: Specify drive strength calibration offsets for 1.8 V
119 automatic calibration times out on a 1.8 V signaling mode.
123 description: Specify drive strength calibration offsets for 3.3 V
129 automatic calibration times out on a 3.3 V signaling mode.
141 description: Specify drive strength calibration offsets for 1.8 V
147 automatic calibration times out on a 1.8 V signaling mode.
151 description: Specify drive strength calibration offsets for 3.3 V
164 automatic calibration times out on a 3.3 V signaling mode.
175 nvidia,only-1-8v:
177 operates at a 1.8 V fixed I/O voltage.
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| /Documentation/devicetree/bindings/usb/ |
| D | st,stusb160x.yaml | 24 description: main power supply (4.1V-22V)
27 description: low power supply (3.0V-5.5V)
30 description: power supply (2.7V-5.5V) used to supply VConn on CC pin in
61 #size-cells = <0>;
65 reg = <0x28>;
80 #size-cells = <0>;
81 port@0 {
82 reg = <0>;
|