| /Documentation/networking/ |
| D | filter.rst | 24 BPF allows a user-space program to attach a filter onto any socket and
36 option. This will probably not be used much since when you close a socket
37 that has a filter on it the filter is automagically removed. The other
38 less common case may be adding a different filter on the same socket where
44 SO_LOCK_FILTER option allows to lock the filter attached to a socket. Once
45 set, a filter cannot be removed or changed. This allows one process to
46 setup a socket, attach a filter, lock it then drop privileges and be
49 The biggest user of this construct might be libpcap. Issuing a high-level
51 internal compiler that generates a structure that can eventually be loaded
64 Steven McCanne and Van Jacobson. 1993. The BSD packet filter: a new
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| /Documentation/admin-guide/thermal/ |
| D | intel_powerclamp.rst | 34 Consider the situation where a system’s power consumption must be
65 #define MSR_PKG_C2_RESIDENCY 0x60D
66 #define MSR_PKG_C3_RESIDENCY 0x3F8
67 #define MSR_PKG_C6_RESIDENCY 0x3F9
68 #define MSR_PKG_C7_RESIDENCY 0x3FA
70 If the kernel can also inject idle time to the system, then a
72 level C-state. The intel_powerclamp driver is conceived as such a
73 control system, where the target set point is a user-selected idle
84 of jiffies, so accumulated errors can be prevented to avoid a jittery
92 values. This effect can be better visualized using a Perf timechart.
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| /Documentation/devicetree/bindings/dvfs/ |
| D | performance-domain.yaml | 15 be confused with power domains. A performance domain is defined by a set
16 of devices that always have to run at the same performance level. For a given
17 performance domain, there is a single point of control that affects all the
20 that domain. For example, a set of CPUs that share a voltage domain, and
21 have a common frequency control, is said to be in the same performance
26 providers. A performance domain provider can be represented by any node in
27 the device tree and can provide one or more performance domains. A consumer
28 node can refer to the provider by a phandle and a set of phandle arguments
37 Number of cells in a performance domain specifier. Typically 0 for nodes
38 representing a single performance domain and 1 for nodes providing
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| /Documentation/arch/powerpc/ |
| D | vcpudispatch_stats.rst | 7 For Shared Processor LPARs, the POWER Hypervisor maintains a relatively
11 scenarios, vcpus may be dispatched on a different processor chip (away
16 collecting the statistics, while writing '0' disables the statistics.
17 By default, the DTLB log for each vcpu is processed 50 times a second so
23 a vcpu as represented by the first field, followed by 8 numbers.
33 3. number of times this vcpu was dispatched on a different processor core
35 4. number of times this vcpu was dispatched on a different chip
36 5. number of times this vcpu was dispatches on a different socket/drawer
43 7. number of times this vcpu was dispatched in a different node
44 8. number of times this vcpu was dispatched in a node further away (numa
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| /Documentation/mm/ |
| D | slub.rst | 9 an impact on overall system performance which may make a bug more
40 after a comma)
55 A Enable failslab filter mark for the cache
82 a result of storing the metadata (for example, caches with PAGE_SIZE object
83 sizes). This has a higher likelihood of resulting in slab allocation errors
97 debugged by specifying global debug options followed by a list of slab names
102 The state of each debug option for a slab can be found in the respective files
107 If the file contains 1, the option is enabled, 0 means disabled. The debug
115 A failslab
117 failslab file is writable, so writing 1 or 0 will enable or disable
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| /Documentation/devicetree/bindings/pci/ |
| D | pci-iommu.txt | 4 Each PCI(e) device under a root complex is uniquely identified by its Requester
5 ID (AKA RID). A Requester ID is a triplet of a Bus number, Device number, and
8 For the purpose of this document, when treated as a numeric value, a RID is
13 * Bits [2:0] are the Function number.
17 Requester ID. While a given PCI device can only master through one IOMMU, a
18 root complex may split masters across a set of IOMMUs (e.g. with one IOMMU per
22 and a mechanism is required to map from a PCI device to its IOMMU and sideband
35 - iommu-map: Maps a Requester ID to an IOMMU and associated IOMMU specifier
44 - iommu-map-mask: A mask to be applied to each Requester ID prior to being
55 iommu: iommu@a {
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| D | pci-msi.txt | 4 Each PCI device under a root complex is uniquely identified by its Requester ID
5 (AKA RID). A Requester ID is a triplet of a Bus number, Device number, and
8 For the purpose of this document, when treated as a numeric value, a RID is
13 * Bits [2:0] are the Function number.
18 Requester ID. A mechanism is required to associate a device with both the MSI
32 - msi-map: Maps a Requester ID to an MSI controller and associated
36 * rid-base is a single cell describing the first RID matched by the entry.
38 * msi-controller is a single phandle to an MSI controller
43 * length is a single cell describing how many consecutive RIDs are matched
49 - msi-map-mask: A mask to be applied to each Requester ID prior to being mapped
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| /Documentation/gpu/amdgpu/ |
| D | debugging.rst | 8 To aid in debugging GPU virtual memory related problems, the driver supports a
11 `vm_fault_stop` - If non-0, halt the GPU memory controller on a GPU page fault.
13 `vm_update_mode` - If non-0, use the CPU to update GPU page tables rather than
17 Decoding a GPUVM Page Fault
20 If you see a GPU page fault in the kernel log, you can decode it to figure
21 out what is going wrong in your application. A page fault in your kernel
26 …[gfxhub0] no-retry page fault (src_id:0 ring:24 vmid:3 pasid:32777, for process glxinfo pid 2424 t…
27 in page starting at address 0x0000800102800000 from IH client 0x1b (UTCL2)
28 VM_L2_PROTECTION_FAULT_STATUS:0x00301030
29 Faulty UTCL2 client ID: TCP (0x8)
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| /Documentation/accounting/ |
| D | delay-accounting.rst | 6 for some kernel resource to become available e.g. a
7 runnable task may wait for a free CPU to run on.
10 the delays experienced by a task while
12 a) waiting for a CPU (while being runnable)
24 Such delays provide feedback for setting a task's cpu priority,
26 important tasks could be a trigger for raising its corresponding priority.
29 delay statistics aggregated for all tasks (or threads) belonging to a
30 thread group (corresponding to a traditional Unix process). This is a commonly
35 statistics of a task are available both during its lifetime as well as on its
43 in detail in a separate document in this directory. Taskstats returns a
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| /Documentation/devicetree/bindings/sound/ |
| D | cs35l33.txt | 22 0, then VBST = VP. If greater than 0, the boost voltage will be 3300mV with
23 a value of 1 and will increase at a step size of 100mV until a maximum of
27 up sequence begins to the time the audio reaches a full-scale output.
31 20ms. If this property is set to 0,1,2,3 then ramp times would be 40ms,
35 The range starts at 1850000uA and goes to a maximum of 3600000uA
36 with a step size of 15625uA. The default is 2500000uA.
39 ADC data word. This property can be set as a value of 0 for bits 15 down
40 to 0, 6 for 21 down to 6, 7, for 22 down to 7, 8 for 23 down to 8.
45 The cs35l33 node can have a single "cirrus,hg-algo" sub-node that will enable
54 LRCLK cycles. If this property is set to 0, 1, 2, or 3 then the memory
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| /Documentation/userspace-api/media/v4l/ |
| D | vidioc-queryctrl.rst | 41 To query the attributes of a control applications set the ``id`` field
42 of a struct :ref:`v4l2_queryctrl <v4l2-queryctrl>` and call the
43 ``VIDIOC_QUERYCTRL`` ioctl with a pointer to this structure. The driver
49 exclusive ``V4L2_CID_LASTP1``. Drivers may return ``EINVAL`` if a control in
81 ``VIDIOC_QUERYMENU`` ioctl with a pointer to this structure. The driver
93 this driver. Also note that the ``minimum`` value is not necessarily 0.
104 :header-rows: 0
105 :stub-columns: 0
113 returns the first control with a higher ID. Drivers which do not
120 - Name of the control, a NUL-terminated ASCII string. This
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| /Documentation/devicetree/bindings/usb/ |
| D | usb-device.yaml | 22 A combined node shall be used instead of a device node and an interface node
23 for devices of class 0 or 9 (hub) with a single configuration and a single
26 A "hub node" is a combined node or an interface node that represents a USB
31 pattern: "^usb[0-9a-f]{1,4},[0-9a-f]{1,4}$"
37 but a device adhering to this binding may leave out all except
51 const: 0
54 "^interface@[0-9a-f]{1,2}(,[0-9a-f]{1,2})$":
62 pattern: "^usbif[0-9a-f]{1,4},[0-9a-f]{1,4}.config[0-9a-f]{1,2}.[0-9a-f]{1,2}$"
69 also be used, but a device adhering to this binding may leave out
87 # interface 0 of configuration 1
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| /Documentation/wmi/devices/ |
| D | msi-wmi-platform.rst | 11 by the embedded controller, with the ACPI firmware exposing a standard ACPI WMI interface on top
22 [WMI, Locale("MS\0x409"),
29 [WMI, Locale("MS\0x409"),
36 [WMI, Dynamic, Provider("WmiProv"), Locale("MS\0x409"),
37 Description("Class used to operate methods on a package"),
43 [WmiMethodId(1), Implemented, read, write, Description("Return the contents of a package")]
44 void GetPackage([out, id(0)] Package Data);
46 [WmiMethodId(2), Implemented, read, write, Description("Set the contents of a package")]
47 void SetPackage([in, id(0)] Package Data);
49 [WmiMethodId(3), Implemented, read, write, Description("Return the contents of a package")]
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| /Documentation/arch/arm64/ |
| D | memory-tagging-extension.rst | 17 feature. MTE is built on top of the ARMv8.0 virtual address tagging TBI
18 (Top Byte Ignore) feature and allows software to access a 4-bit
21 attribute. A logical tag is derived from bits 59-56 of the virtual
22 address used for the memory access. A CPU with MTE enabled will compare
36 To access the allocation tags, a user process must enable the Tagged
37 memory attribute on an address range using a new ``prot`` flag for
42 The allocation tag is set to 0 when such pages are first mapped in the
55 ``MADV_FREE`` may have the allocation tags cleared (set to 0) at any
61 When ``PROT_MTE`` is enabled on an address range and a mismatch between
68 - *Synchronous* - The kernel raises a ``SIGSEGV`` synchronously, with
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| /Documentation/admin-guide/device-mapper/ |
| D | dm-service-time.rst | 5 dm-service-time is a path selector module for device-mapper targets,
6 which selects a path with the shortest estimated service time for
10 of in-flight I/Os on a path with the performance value of the path.
11 The performance value is a relative throughput value among all paths
12 in a path-group, and it can be specified as a table argument.
27 The valid range is 0-100.
29 If '0' is given, the path isn't selected while
30 other paths having a positive value are available.
36 'A' if the path is active, 'F' if the path is failed.
51 Basically, dm-service-time selects a path having minimum service time
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| D | dm-dust.rst | 8 This target behaves similarly to a linear target. At a given time,
9 the user can send a message to the target to start failing read
10 requests on specific blocks (to emulate the behavior of a hard disk
22 This emulates the "remapped sector" behavior of a drive with bad
25 Normally, a drive that is encountering bad sectors will most likely
32 simulating a "failure" event where bad sectors start to appear.
48 (minimum 512, maximum 1073741824, must be a power of 2)
59 (For a device with a block size of 512 bytes)
63 $ sudo dmsetup create dust1 --table '0 33552384 dust /dev/vdb1 0 512'
65 (For a device with a block size of 4096 bytes)
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| /Documentation/admin-guide/ |
| D | ramoops.rst | 12 crashes. It works by logging oopses and panics in a circular buffer. Ramoops
13 needs a system with persistent RAM so that the content of that area can
14 survive after a restart.
19 Ramoops uses a predefined memory area to store the dump. The start and size
23 * ``mem_size`` for the size. The memory size will be rounded down to a
26 * ``mem_name`` to specify a memory region defined by ``reserve_mem`` command
29 Typically the default value of ``mem_type=0`` should be used as that sets the pstore
39 power of two) and each kmesg dump writes a ``record_size`` chunk of
46 ``max_reason`` should be set to 1 (KMSG_DUMP_PANIC). Setting this to 0
51 The module uses a counter to record multiple dumps but the counter gets reset
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| /Documentation/arch/x86/ |
| D | topology.rst | 26 The kernel does not care about the concept of physical sockets because a
28 the past a socket always contained a single package (see below), but with the
29 advent of Multi Chip Modules (MCM) a socket can hold more than one package. So
33 The topology of a system is described in the units of:
41 Packages contain a number of cores plus shared resources, e.g. DRAM
52 The number of threads in a package.
56 The number of cores in a package.
60 The maximum number of dies in a package.
72 packages within a socket. This value may differ from topo.die_id.
77 packages in a consistent way, we introduced the concept of logical package
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| /Documentation/leds/ |
| D | leds-qcom-lpg.rst | 10 The Qualcomm LPG can be found in a variety of Qualcomm PMICs and consists of a
11 number of PWM channels, a programmable pattern lookup table and a RGB LED
19 The each PWM channel can operate with a period between 27us and 384 seconds and
20 has a 9 bit resolution of the duty cycle.
23 deeper idle states the LPG provides pattern support. This consists of a shared
27 The pattern for a channel can be programmed using the "pattern" trigger, using
33 Specify a hardware pattern for a Qualcomm LPG LED.
35 The pattern is a series of brightness and hold-time pairs, with the hold-time
36 expressed in milliseconds. The hold time is a property of the pattern and must
40 pattern must be followed a zero-length entry of the same brightness.
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| /Documentation/core-api/ |
| D | workqueue.rst | 17 When such an asynchronous execution context is needed, a work item
18 describing which function to execute is put on a queue. An
25 When a new work item gets queued, the worker begins executing again.
31 In the original wq implementation, a multi threaded (MT) wq had one
32 worker thread per CPU and a single threaded (ST) wq had one worker
33 thread system-wide. A single MT wq needed to keep around the same
34 number of workers as the number of CPUs. The kernel grew a lot of MT
39 Although MT wq wasted a lot of resource, the level of concurrency
55 Concurrency Managed Workqueue (cmwq) is a reimplementation of wq with
61 flexible level of concurrency on demand without wasting a lot of
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| /Documentation/staging/ |
| D | lzo.rst | 8 This is not a specification. No specification seems to be publicly available
20 The stream is composed of a series of instructions, operands, and data. The
21 instructions consist in a few bits representing an opcode, and bits forming
26 - a distance when copying data from the dictionary (past output buffer)
27 - a length (number of bytes to copy from dictionary)
29 as a piece of information for next instructions.
32 extra data can be a complement for the operand (eg: a length or a distance
33 encoded on larger values), or a literal to be copied to the output buffer.
35 The first byte of the block follows a different encoding from other bytes, it
39 Lengths are always encoded on a variable size starting with a small number
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| /Documentation/devicetree/bindings/mips/cavium/ |
| D | bootbus.txt | 3 The Octeon Boot Bus is a configurable parallel bus with 8 chip
29 - cavium,cs-index: A single cell indicating the chip select that
32 - cavium,t-adr: A cell specifying the ADR timing (in nS).
34 - cavium,t-ce: A cell specifying the CE timing (in nS).
36 - cavium,t-oe: A cell specifying the OE timing (in nS).
38 - cavium,t-we: A cell specifying the WE timing (in nS).
40 - cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS).
42 - cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS).
44 - cavium,t-pause: A cell specifying the PAUSE timing (in nS).
46 - cavium,t-wait: A cell specifying the WAIT timing (in nS).
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio.txt | 8 of this GPIO for the device. While a non-existent <name> is considered valid
16 distinct functions, reference each of them under its own property, giving it a
18 several GPIOs serve the same function (e.g. a parallel data line).
32 data-gpios = <&gpio1 12 0>,
33 <&gpio1 13 0>,
34 <&gpio1 14 0>,
35 <&gpio1 15 0>;
37 In the above example, &gpio1 uses 2 cells to specify a gpio. The first cell is
38 a local offset to the GPIO line and the second cell represent consumer flags,
46 Most controllers are specifying a generic flag bitfield in the last cell, so
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | ti,pruss.yaml | 16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
31 - a 16550-compatible UART to support PROFIBUS
34 A PRU-ICSS subsystem can have up to three shared data memories. A PRU core
35 acts on a primary Data RAM (there are usually 2 Data RAMs) at its address
36 0x0, but also has access to a secondary Data RAM (primary to the other PRU
37 core) at its address 0x2000. A shared Data RAM, if present, can be accessed
38 by both the PRU cores. The Interrupt Controller (INTC) and a CFG module are
39 common to both the PRU cores. Each PRU core also has a private instruction
42 Various sub-modules within a PRU-ICSS subsystem are represented as individual
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| /Documentation/hwmon/ |
| D | abituguru-datasheet.rst | 8 And just for the record, you may have noticed uGuru isn't a chip developed by
34 0xE0 and 0xE4, so we don't have to scan any port-range, just check what the two
35 ports are holding for detection. We will refer to 0xE0 as CMD (command-port)
36 and 0xE4 as DATA because Abit refers to them with these names.
38 If DATA holds 0x00 or 0x08 and CMD holds 0x00 or 0xAC an uGuru could be
40 after a reboot uGuru will hold 0x00 here, but if the driver is removed and
41 later on attached again data-port will hold 0x08, more about this later.
44 turned up which will hold 0x00 instead of 0xAC at the CMD port, thus we also
46 hold 0x09 and will only hold 0x08 after reading CMD first, so CMD must be read
49 To be really sure an uGuru is present a test read of one or more register
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