Searched +full:0 +full:x0 (Results 1 – 25 of 669) sorted by relevance
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| /Documentation/devicetree/bindings/pci/ |
| D | cdns,cdns-pcie-host.yaml | 44 bus-range = <0x0 0xff>;
45 linux,pci-domain = <0>;
46 vendor-id = <0x17cd>;
47 device-id = <0x0200>;
49 reg = <0x0 0xfb000000 0x0 0x01000000>,
50 <0x0 0x41000000 0x0 0x00001000>;
53 ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>,
54 <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;
55 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
57 #interrupt-cells = <0x1>;
[all …]
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| D | xgene-pci-msi.txt | 8 - reg: physical base address (0x79000000) and length (0x900000) for controller
13 interrupt number 0x10 to 0x1f.
27 reg = <0x00 0x79000000 0x0 0x900000>;
28 interrupts = <0x0 0x10 0x4>
29 <0x0 0x11 0x4>
30 <0x0 0x12 0x4>
31 <0x0 0x13 0x4>
32 <0x0 0x14 0x4>
33 <0x0 0x15 0x4>
34 <0x0 0x16 0x4>
[all …]
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| D | 83xx-512x-pci.txt | 12 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
14 /* IDSEL 0x0E -mini PCI */
15 0x7000 0x0 0x0 0x1 &ipic 18 0x8
16 0x7000 0x0 0x0 0x2 &ipic 18 0x8
17 0x7000 0x0 0x0 0x3 &ipic 18 0x8
18 0x7000 0x0 0x0 0x4 &ipic 18 0x8
20 /* IDSEL 0x0F - PCI slot */
21 0x7800 0x0 0x0 0x1 &ipic 17 0x8
22 0x7800 0x0 0x0 0x2 &ipic 18 0x8
23 0x7800 0x0 0x0 0x3 &ipic 17 0x8
[all …]
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| D | sifive,fu740-pcie.yaml | 94 reg = <0xe 0x00000000 0x0 0x80000000>,
95 <0xd 0xf0000000 0x0 0x10000000>,
96 <0x0 0x100d0000 0x0 0x1000>;
100 bus-range = <0x0 0xff>;
101 ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */
102 <0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */
103 <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */
104 … <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */
105 num-lanes = <0x8>;
109 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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| D | xgene-pci.txt | 35 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
36 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
38 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
39 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
40 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
41 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
42 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
43 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
44 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
45 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
[all …]
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| D | starfive,jh7110-pcie.yaml | 81 reg = <0x9 0x40000000 0x0 0x10000000>,
82 <0x0 0x2b000000 0x0 0x1000000>;
88 ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
89 <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
91 bus-range = <0x0 0xff>;
94 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
95 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
96 <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
97 <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
98 <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
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| D | xlnx,nwl-pcie.yaml | 50 - const: 0
51 - const: 0
52 - const: 0
87 const: 0
125 reg = <0x0 0xfd0e0000 0x0 0x1000>,
126 <0x0 0xfd480000 0x0 0x1000>,
127 <0x80 0x00000000 0x0 0x10000000>;
129 ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
130 <0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>;
141 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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| D | hisilicon,kirin-pcie.yaml | 78 reg = <0x0 0xf4000000 0x0 0x1000>,
79 <0x0 0xff3fe000 0x0 0x1000>,
80 <0x0 0xf3f20000 0x0 0x40000>,
81 <0x0 0xf5000000 0x0 0x2000>;
83 bus-range = <0x0 0xff>;
87 ranges = <0x02000000 0x0 0x00000000
88 0x0 0xf6000000
89 0x0 0x02000000>;
92 interrupts = <0 283 4>;
94 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
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| D | apple,pcie.yaml | 114 reg = <0x6 0x90000000 0x0 0x1000000>,
115 <0x6 0x80000000 0x0 0x100000>,
116 <0x6 0x81000000 0x0 0x4000>,
117 <0x6 0x82000000 0x0 0x4000>,
118 <0x6 0x83000000 0x0 0x4000>;
130 iommu-map = <0x100 &dart0 1 1>,
131 <0x200 &dart1 1 1>,
132 <0x300 &dart2 1 1>;
133 iommu-map-mask = <0xff00>;
135 bus-range = <0 3>;
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| D | host-generic-pci.yaml | 94 property. If no "bus-range" is specified, this will be bus 0 (the
160 bus-range = <0x0 0x1>;
163 reg = <0x0 0x40000000 0x0 0x1000000>;
166 ranges = <0x01000000 0x0 0x01000000 0x0 0x01000000 0x0 0x00010000>,
167 <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x3f000000>;
169 #interrupt-cells = <0x1>;
172 interrupt-map = < 0x0 0x0 0x0 0x1 &gic 0x0 0x4 0x1>,
173 < 0x800 0x0 0x0 0x1 &gic 0x0 0x5 0x1>,
174 <0x1000 0x0 0x0 0x1 &gic 0x0 0x6 0x1>,
175 <0x1800 0x0 0x0 0x1 &gic 0x0 0x7 0x1>;
[all …]
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| D | qcom,pcie-sa8775p.yaml | 91 reg = <0x0 0x01c00000 0x0 0x3000>,
92 <0x0 0x40000000 0x0 0xf20>,
93 <0x0 0x40000f20 0x0 0xa8>,
94 <0x0 0x40001000 0x0 0x4000>,
95 <0x0 0x40100000 0x0 0x100000>,
96 <0x0 0x01c03000 0x0 0x1000>;
98 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
99 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
101 bus-range = <0x00 0xff>;
103 linux,pci-domain = <0>;
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| D | brcm,stb-pcie.yaml | 190 reg = <0x0 0x7d500000 0x9310>;
198 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
199 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
200 0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH
201 0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH
202 0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
206 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;
207 dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>,
208 <0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>;
210 brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>;
[all …]
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| D | qcom,pcie-sc8280xp.yaml | 107 reg = <0x0 0x01c20000 0x0 0x3000>,
108 <0x0 0x3c000000 0x0 0xf1d>,
109 <0x0 0x3c000f20 0x0 0xa8>,
110 <0x0 0x3c001000 0x0 0x1000>,
111 <0x0 0x3c100000 0x0 0x100000>,
112 <0x0 0x01c23000 0x0 0x1000>;
114 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>,
115 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
117 bus-range = <0x00 0xff>;
152 interrupt-map-mask = <0 0 0 0x7>;
[all …]
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| D | pcie-al.txt | 33 reg = <0x0 0xfb600000 0x0 0x00100000
34 0x0 0xfd800000 0x0 0x00010000
35 0x0 0xfd810000 0x0 0x00001000>;
37 bus-range = <0 255>;
43 interrupt-map-mask = <0x00 0 0 7>;
44 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; /* INTa */
45 ranges = <0x02000000 0x0 0xc0010000 0x0 0xc0010000 0x0 0x07ff0000>;
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| D | xilinx-versal-cpm.yaml | 55 const: 0
87 interrupts = <0 72 4>;
89 interrupt-map-mask = <0 0 0 7>;
90 interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
91 <0 0 0 2 &pcie_intc_0 1>,
92 <0 0 0 3 &pcie_intc_0 2>,
93 <0 0 0 4 &pcie_intc_0 3>;
94 bus-range = <0x00 0xff>;
95 ranges = <0x02000000 0x0 0xe0010000 0x0 0xe0010000 0x0 0x10000000>,
96 <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
[all …]
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| /Documentation/devicetree/bindings/ata/ |
| D | apm-xgene.txt | 41 reg = <0x0 0x1f22a000 0x0 0x100>;
47 reg = <0x0 0x1f23a000 0x0 0x100>;
53 reg = <0x0 0x1a400000 0x0 0x1000>,
54 <0x0 0x1f220000 0x0 0x1000>,
55 <0x0 0x1f22d000 0x0 0x1000>,
56 <0x0 0x1f22e000 0x0 0x1000>,
57 <0x0 0x1f227000 0x0 0x1000>;
58 interrupts = <0x0 0x87 0x4>;
60 clocks = <&sataclk 0>;
61 phys = <&phy2 0>;
[all …]
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| /Documentation/devicetree/bindings/perf/ |
| D | apm-xgene-pmu.txt | 43 reg = <0x0 0x7e200000 0x0 0x1000>;
48 reg = <0x0 0x7e700000 0x0 0x1000>;
53 reg = <0x0 0x7e720000 0x0 0x1000>;
64 reg = <0x0 0x78810000 0x0 0x1000>;
65 interrupts = <0x0 0x22 0x4>;
69 reg = <0x0 0x7e610000 0x0 0x1000>;
74 reg = <0x0 0x7e940000 0x0 0x1000>;
79 reg = <0x0 0x7e710000 0x0 0x1000>;
80 enable-bit-index = <0>;
85 reg = <0x0 0x7e730000 0x0 0x1000>;
[all …]
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| /Documentation/devicetree/bindings/dma/ |
| D | apm-xgene-dma.txt | 27 clocks = <&socplldiv2 0>;
28 reg = <0x0 0x1f27c000 0x0 0x1000>;
36 reg = <0x0 0x1f270000 0x0 0x10000>,
37 <0x0 0x1f200000 0x0 0x10000>,
38 <0x0 0x1b000000 0x0 0x400000>,
39 <0x0 0x1054a000 0x0 0x100>;
40 interrupts = <0x0 0x82 0x4>,
41 <0x0 0xb8 0x4>,
42 <0x0 0xb9 0x4>,
43 <0x0 0xba 0x4>,
[all …]
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| /Documentation/devicetree/bindings/crypto/ |
| D | hisilicon,hip07-sec.txt | 9 Region 0 has registers to control the backend processing engines.
16 Interrupt 0 is for the SEC unit error queue.
29 reg = <0x400 0xd0000000 0x0 0x10000
30 0x400 0xd2000000 0x0 0x10000
31 0x400 0xd2010000 0x0 0x10000
32 0x400 0xd2020000 0x0 0x10000
33 0x400 0xd2030000 0x0 0x10000
34 0x400 0xd2040000 0x0 0x10000
35 0x400 0xd2050000 0x0 0x10000
36 0x400 0xd2060000 0x0 0x10000
[all …]
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| /Documentation/devicetree/bindings/edac/ |
| D | apm-xgene-edac.txt | 53 reg = <0x0 0x7e200000 0x0 0x1000>;
58 reg = <0x0 0x7e700000 0x0 0x1000>;
63 reg = <0x0 0x7e720000 0x0 0x1000>;
68 reg = <0x0 0x1054a000 0x0 0x20>;
73 reg = <0x0 0x7e000000 0x0 0x10>;
86 reg = <0x0 0x78800000 0x0 0x100>;
87 interrupts = <0x0 0x20 0x4>,
88 <0x0 0x21 0x4>,
89 <0x0 0x27 0x4>;
93 reg = <0x0 0x7e800000 0x0 0x1000>;
[all …]
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | xlnx,zynqmp-r5fss.yaml | 39 enum: [0, 1, 2]
44 clock-for-clock) or Single CPU mode (RPU core 0 is held in reset while
47 If set to 1 then lockstep mode and if 0 then split mode.
50 0: split mode
56 enum: [0, 1]
59 0: split mode
63 "^r(.*)@[0-9a-f]+$":
162 "^r52f@[0-9a-f]+$":
206 "^r5f@[0-9a-f]+$":
241 enum: [0]
[all …]
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| /Documentation/devicetree/bindings/mailbox/ |
| D | xgene-slimpro-mailbox.txt | 14 - interrupts: 8 interrupts must be from 0 to 7, interrupt 0 define the
15 the interrupt for mailbox channel 0 and interrupt 1 for
25 reg = <0x0 0x10540000 0x0 0xa000>;
27 interrupts = <0x0 0x0 0x4>,
28 <0x0 0x1 0x4>,
29 <0x0 0x2 0x4>,
30 <0x0 0x3 0x4>,
31 <0x0 0x4 0x4>,
32 <0x0 0x5 0x4>,
33 <0x0 0x6 0x4>,
[all …]
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| /Documentation/devicetree/bindings/phy/ |
| D | airoha,en7581-pcie-phy.yaml | 38 const: 0
58 #phy-cells = <0>;
59 reg = <0x0 0x1fa5a000 0x0 0xfff>,
60 <0x0 0x1fa5b000 0x0 0xfff>,
61 <0x0 0x1fa5c000 0x0 0xfff>,
62 <0x0 0x1fc10044 0x0 0x4>,
63 <0x0 0x1fc30044 0x0 0x4>,
64 <0x0 0x1fc15030 0x0 0x104>;
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra186-mc.yaml | 27 pattern: "^memory-controller@[0-9a-f]+$"
62 "^external-memory-controller@[0-9a-f]+$":
95 const: 0
244 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
245 <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */
246 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */
247 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */
248 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */
249 <0x0 0x02c50000 0x0 0x10000>; /* MC3 */
256 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
[all …]
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| /Documentation/devicetree/bindings/clock/ |
| D | xgene.txt | 50 Default is 0.
51 - csr-mask : CSR reset mask bit. Default is 0xF.
53 Default is 0x8.
54 - enable-mask : CSR enable mask bit. Default is 0xF.
56 Default is 0x0.
57 - divider-width : Width of the divider register. Default is 0.
58 - divider-shift : Bit shift of the divider register. Default is 0.
65 clocks = <&refclk 0>;
67 reg = <0x0 0x17000100 0x0 0x1000>;
69 type = <0>;
[all …]
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