| /Documentation/devicetree/bindings/input/ |
| D | dlg,da7280.txt | 25 device enabled by sending magnitude (X > 0),
31 Valid values: 0 - 6000000.
33 Valid values: 0 - 6000000.
35 Valid values: 0 - 252000.
38 Valid values: 0 - 1500000000.
49 Valid range: 0 - 15.
52 Valid range: 0 - 15.
54 when gpi0 is triggered, 'N' must be 0 - 2.
55 Valid range: 0 - 15.
57 "Single-pattern" or "Multi-pattern", 'N' must be 0 - 2.
[all …]
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| D | st-keyscan.txt | 34 reg = <0xfe4b0000 0x2000>;
38 pinctrl-0 = <&pinctrl_keyscan>;
44 linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_F13)
45 MATRIX_KEY(0x00, 0x01, KEY_F9)
46 MATRIX_KEY(0x00, 0x02, KEY_F5)
47 MATRIX_KEY(0x00, 0x03, KEY_F1)
48 MATRIX_KEY(0x01, 0x00, KEY_F14)
49 MATRIX_KEY(0x01, 0x01, KEY_F10)
50 MATRIX_KEY(0x01, 0x02, KEY_F6)
51 MATRIX_KEY(0x01, 0x03, KEY_F2)
[all …]
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| D | adi,adp5588.yaml | 98 #size-cells = <0>;
102 reg = <0x34>;
112 MATRIX_KEY(0x00, 0x00, KEY_1)
113 MATRIX_KEY(0x00, 0x01, KEY_2)
114 MATRIX_KEY(0x00, 0x02, KEY_3)
115 MATRIX_KEY(0x00, 0x03, KEY_4)
116 MATRIX_KEY(0x00, 0x04, KEY_5)
117 MATRIX_KEY(0x00, 0x05, KEY_6)
118 MATRIX_KEY(0x00, 0x06, KEY_7)
119 MATRIX_KEY(0x00, 0x07, KEY_8)
[all …]
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| D | brcm,bcm-keypad.txt | 31 KEYPAD_DEBOUNCE_1_ms = 0
42 KEYPAD_DEBOUNCE_1_ms = 0
76 linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_F) /* key_forward */
77 MATRIX_KEY(0x00, 0x03, KEY_HOME) /* key_home */
78 MATRIX_KEY(0x00, 0x04, KEY_M) /* key_message */
79 MATRIX_KEY(0x01, 0x00, KEY_A) /* key_contacts */
80 MATRIX_KEY(0x01, 0x01, KEY_1) /* key_1 */
81 MATRIX_KEY(0x01, 0x02, KEY_2) /* key_2 */
82 MATRIX_KEY(0x01, 0x03, KEY_3) /* key_3 */
83 MATRIX_KEY(0x01, 0x04, KEY_S) /* key_speaker */
[all …]
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | qcom,pm8018-adc.yaml | 27 ADC base address in the PMIC, typically 0x197.
41 with two valid bits so legal values are 0x00, 0x01 or 0x02.
42 The second cell is the main analog mux setting (0x00..0x0f).
47 const: 0
67 "^(adc-channel@)[0-9a-f]$":
74 1:1 ratio converters that sample 625, 1250 and 0 milliV and create
104 0 = XO_IN/XOADC_GND
121 #size-cells = <0>;
125 reg = <0x197>;
128 #size-cells = <0>;
[all …]
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| /Documentation/devicetree/bindings/net/ |
| D | marvell-bt-8xxx.txt | 52 #size-cells = <0>;
60 0x37 0x01 0x1c 0x00 0xff 0xff 0xff 0xff 0x01 0x7f 0x04 0x02
61 0x00 0x00 0xba 0xce 0xc0 0xc6 0x2d 0x00 0x00 0x00 0x00 0x00
62 0x00 0x00 0xf0 0x00>;
63 marvell,wakeup-pin = /bits/ 16 <0x0d>;
64 marvell,wakeup-gap-ms = /bits/ 16 <0x64>;
72 #size-cells = <0>;
80 marvell,wakeup-pin = /bits/ 16 <0x0d>;
81 marvell,wakeup-gap-ms = /bits/ 16 <0x64>;
|
| /Documentation/admin-guide/ |
| D | binfmt-misc.rst | 32 defaults to 0 if you omit it (i.e. you write ``:name:type::magic...``).
44 is an (optional, defaults to all 0xff) mask. You can mask out some
57 ``P`` - preserve-argv[0]
59 the original argv[0] with the full path to the binary. When this
61 vector for this purpose, thus preserving the original ``argv[0]``.
102 a line ``none /proc/sys/fs/binfmt_misc binfmt_misc defaults 0 0`` to your
116 …echo ':i386:M::\x7fELF\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x03:\xff\xff\xff\xf…
117 …echo ':i486:M::\x7fELF\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x06:\xff\xff\xff\xf…
130 You can enable/disable binfmt_misc or one binary type by echoing 0 (to disable)
|
| /Documentation/devicetree/bindings/pci/ |
| D | xgene-pci.txt | 35 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
36 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
38 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
39 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
40 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
41 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
42 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
43 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
44 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
45 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
[all …]
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| D | xgene-pci-msi.txt | 8 - reg: physical base address (0x79000000) and length (0x900000) for controller
13 interrupt number 0x10 to 0x1f.
27 reg = <0x00 0x79000000 0x0 0x900000>;
28 interrupts = <0x0 0x10 0x4>
29 <0x0 0x11 0x4>
30 <0x0 0x12 0x4>
31 <0x0 0x13 0x4>
32 <0x0 0x14 0x4>
33 <0x0 0x15 0x4>
34 <0x0 0x16 0x4>
[all …]
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| D | ti,j721e-pci-ep.yaml | 127 reg = <0x00 0x02900000 0x00 0x1000>,
128 <0x00 0x02907000 0x00 0x400>,
129 <0x00 0x0d000000 0x00 0x00800000>,
130 <0x00 0x10000000 0x00 0x08000000>;
132 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
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| D | ti,j721e-pci-host.yaml | 78 const: 0x104c
82 - 0xb00d
83 - 0xb00f
84 - 0xb010
85 - 0xb012
86 - 0xb013
177 reg = <0x00 0x02900000 0x00 0x1000>,
178 <0x00 0x02907000 0x00 0x400>,
179 <0x00 0x0d000000 0x00 0x00800000>,
180 <0x00 0x10000000 0x00 0x00001000>;
[all …]
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| D | xilinx-versal-cpm.yaml | 55 const: 0
87 interrupts = <0 72 4>;
89 interrupt-map-mask = <0 0 0 7>;
90 interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
91 <0 0 0 2 &pcie_intc_0 1>,
92 <0 0 0 3 &pcie_intc_0 2>,
93 <0 0 0 4 &pcie_intc_0 3>;
94 bus-range = <0x00 0xff>;
95 ranges = <0x02000000 0x0 0xe0010000 0x0 0xe0010000 0x0 0x10000000>,
96 <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
[all …]
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | ti,k3-r5f-rproc.yaml | 72 It should be either a value of 1 (LockStep mode) or 0 (Split mode) on
76 It should be either a value of 0 (Split mode) or 2 (Single-CPU mode) and
103 either of them can be configured to appear at that R5F's address 0x0.
177 enum: [0, 1]
181 either a value of 1 (enabled) or 0 (disabled), default is disabled
186 enum: [0, 1]
190 either a value of 1 (enabled) or 0 (disabled), default is enabled if
195 enum: [0, 1]
198 address 0 (from core's view). Should be either a value of 1 (ATCM
199 at 0x0) or 0 (BTCM at 0x0), default value is 1 if omitted.
[all …]
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| D | ti,k3-dsp-rproc.yaml | 161 mailbox0_cluster3: mailbox-0 {
173 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
174 <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71_0 */
175 <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
176 <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>; /* C66_1 */
181 reg = <0x4d 0x80800000 0x00 0x00048000>,
182 <0x4d 0x80e00000 0x00 0x00008000>,
183 <0x4d 0x80f00000 0x00 0x00008000>;
187 ti,sci-proc-ids = <0x03 0xFF>;
198 reg = <0x00 0x64800000 0x00 0x00080000>,
[all …]
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| D | ti,k3-m4f-rproc.yaml | 92 reg = <0x00 0x9cb00000 0x00 0x100000>;
98 reg = <0x00 0x9cc00000 0x00 0xe00000>;
107 mailbox0_cluster0: mailbox-0 {
113 reg = <0x00 0x5000000 0x00 0x30000>,
114 <0x00 0x5040000 0x00 0x10000>;
123 ti,sci-proc-ids = <0x18 0xff>;
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| /Documentation/devicetree/bindings/usb/ |
| D | ti,j721e-usb.yaml | 44 If present, it restricts the controller to USB2.0 mode of
87 reg = <0x00 0x4104000 0x00 0x100>;
98 reg = <0x00 0x6000000 0x00 0x10000>,
99 <0x00 0x6010000 0x00 0x10000>,
100 <0x00 0x6020000 0x00 0x10000>;
102 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
104 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
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| D | cdns,usb3.yaml | 100 reg = <0x00 0x6000000 0x00 0x10000>,
101 <0x00 0x6010000 0x00 0x10000>,
102 <0x00 0x6020000 0x00 0x10000>;
|
| D | ti,am62-usb.yaml | 62 "^usb@[0-9a-f]+$":
88 reg = <0x00 0x0f910000 0x00 0x800>,
89 <0x00 0x0f918000 0x00 0x400>;
92 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
99 reg = <0x00 0x31100000 0x00 0x50000>;
100 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
101 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
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| /Documentation/devicetree/bindings/soundwire/ |
| D | qcom,soundwire.yaml | 64 const: 0
80 Value of 0xff indicates that this option is not implemented
91 Value of 0xff indicates that this option is not implemented
102 Value of 0xffff indicates that this option is not implemented
113 Value of 0xff indicates that this option is not implemented
124 Value of 0xff indicates that this option is not implemented
135 Value of 0xff indicates that this option is not implemented
145 0 to indicate Blocks are per Channel
148 Value of 0xff indicates that this option is not implemented
155 - minimum: 0
[all …]
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-event_source-devices-dfl_fme | 13 event = "config:0-11" - event ID
19 fab_mmio_read = "event=0x06,evtype=0x02,portid=0xff"
21 It shows this fab_mmio_read is a fabric type (0x02) event with
22 0x06 local event id for overall monitoring (portid=0xff).
43 Basic events (evtype=0x00)::
45 clock = "event=0x00,evtype=0x00,portid=0xff"
47 Cache events (evtype=0x01)::
49 cache_read_hit = "event=0x00,evtype=0x01,portid=0xff"
50 cache_read_miss = "event=0x01,evtype=0x01,portid=0xff"
51 cache_write_hit = "event=0x02,evtype=0x01,portid=0xff"
[all …]
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| /Documentation/devicetree/bindings/sound/ |
| D | cs35l35.txt | 27 0 = Data Packet received on Left I2S Channel
31 0 = Data Packet received on Left I2S Channel
43 0 = 1x (Default)
47 0 - Hi-Z
48 2 - Drive 0's (Default)
144 reg = <0x20>;
147 reset-gpios = <&axi_gpio 54 0>;
153 cirrus,audio-channel = <0x00>;
154 cirrus,advisory-channel = <0x01>;
159 cirrus,classh-bst-max-limit = <0x01>;
[all …]
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| /Documentation/devicetree/bindings/mfd/ |
| D | st,stmpe.yaml | 53 enum: [ 0, 1, 2, 3, 4, 5, 6 ]
56 0 = 36 clock ticks
66 enum: [ 0, 1 ]
67 description: ADC bit mode 0 = 10bit ADC, 1 = 12bit ADC
71 enum: [ 0, 1 ]
72 description: ADC reference source 0 = internal, 1 = external
76 enum: [ 0, 1, 2, 3 ]
79 0 = 1.625 MHz
142 enum: [ 0, 1, 2, 3 ]
145 0 = 1 sample
[all …]
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| /Documentation/devicetree/bindings/media/ |
| D | img,e5010-jpeg-enc.yaml | 68 reg = <0x00 0xfd20000 0x00 0x100>,
69 <0x00 0xfd20200 0x00 0x200>;
71 clocks = <&k3_clks 201 0>;
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| /Documentation/networking/ |
| D | mac80211-injection.rst | 75 0x00, 0x00, // <-- radiotap version
76 0x0b, 0x00, // <- radiotap header length
77 0x04, 0x0c, 0x00, 0x00, // <-- bitmap
78 0x6c, // <-- rate
79 0x0c, //<-- tx power
80 0x01 //<-- antenna
85 0x08, 0x01, 0x00, 0x00,
86 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
87 0x13, 0x22, 0x33, 0x44, 0x55, 0x66,
88 0x13, 0x22, 0x33, 0x44, 0x55, 0x66,
[all …]
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| /Documentation/hwmon/ |
| D | gl518sm.rst | 6 * Genesys Logic GL518SM release 0x00
10 Addresses scanned: I2C 0x2c and 0x2d
12 * Genesys Logic GL518SM release 0x80
16 Addresses scanned: I2C 0x2c and 0x2d
31 For the revision 0x00 chip, the in0, in1, and in2 values (+5V, +3V,
35 two revision of this chip, which we call revision 0x00 and 0x80. Revision
36 0x80 chips support the reading of all voltages and revision 0x00 only
64 a resolution of 0.019 volt. Note that revision 0x00 chips do not support
|