Searched +full:0 +full:x00000001 (Results 1 – 25 of 47) sorted by relevance
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra124-mc.yaml | 47 "^emc-timings-[0-9]+$":
56 "^timing-[0-9]+$":
118 reg = <0x70019000 0x1000>;
122 interrupts = <0 77 4>;
135 0x40040001 /* MC_EMEM_ARB_CFG */
136 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
137 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
138 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
139 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
140 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
[all …]
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| D | nvidia,tegra20-emc.yaml | 38 const: 0
41 const: 0
145 "^emc-table@[0-9]+$":
165 const: 0
172 "^emc-table@[0-9]+$":
199 reg = <0x7000f400 0x400>;
200 interrupts = <0 78 4>;
207 #interconnect-cells = <0>;
209 #size-cells = <0>;
213 emc-tables@0 {
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| D | nvidia,tegra30-emc.yaml | 35 const: 0
53 "^emc-timings-[0-9]+$":
62 "^timing-[0-9]+$":
75 minimum: 0
91 Mode Register 0.
98 minimum: 0
239 reg = <0x7000f400 0x400>;
240 interrupts = <0 78 4>;
247 #interconnect-cells = <0>;
255 nvidia,emc-auto-cal-interval = <0x001fffff>;
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| D | nvidia,tegra30-mc.yaml | 64 "^emc-timings-[0-9]+$":
73 "^timing-[0-9]+$":
134 reg = <0x7000f000 0x400>;
138 interrupts = <0 77 4>;
151 0x0000000a /* MC_EMEM_ARB_CFG */
152 0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */
153 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */
154 0x00000004 /* MC_EMEM_ARB_TIMING_RP */
155 0x00000010 /* MC_EMEM_ARB_TIMING_RC */
156 0x0000000b /* MC_EMEM_ARB_TIMING_RAS */
[all …]
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| /Documentation/devicetree/bindings/net/ |
| D | socfpga-dwmac.txt | 39 reg = <0x00000001 0x00000240 0x00000008>,
40 <0x00000001 0x00000200 0x00000040>;
48 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
49 reg = <0xff700000 0x2000>;
50 interrupts = <0 115 4>;
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| /Documentation/devicetree/bindings/usb/ |
| D | dwc3-cavium.txt | 14 reg = <0x00011800 0x69000000 0x00000000 0x00000100>;
16 #address-cells = <0x00000002>;
17 #size-cells = <0x00000002>;
18 refclk-frequency = <0x05f5e100>;
21 power = <0x00000002 0x00000002 0x00000001>;
24 reg = <0x00016900 0x00000000 0x00000010 0x00000000>;
25 interrupt-parent = <0x00000010>;
26 interrupts = <0x00000009 0x00000004>;
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| /Documentation/devicetree/bindings/mtd/ |
| D | ibm,ndfc.txt | 5 - reg : should specify chip select and size used for the chip (0x2000).
8 - ccr : NDFC config and control register value (default 0).
9 - bank-settings : NDFC bank configuration register value (default 0).
16 ndfc@1,0 {
18 reg = <0x00000001 0x00000000 0x00002000>;
19 ccr = <0x00001000>;
20 bank-settings = <0x80002222>;
28 partition@0 {
30 reg = <0x00000000 0x00200000>;
34 reg = <0x00200000 0x03E00000>;
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| /Documentation/firmware-guide/acpi/ |
| D | debug.rst | 40 ACPI_UTILITIES 0x00000001
41 ACPI_HARDWARE 0x00000002
42 ACPI_EVENTS 0x00000004
43 ACPI_TABLES 0x00000008
44 ACPI_NAMESPACE 0x00000010
45 ACPI_PARSER 0x00000020
46 ACPI_DISPATCHER 0x00000040
47 ACPI_EXECUTER 0x00000080
48 ACPI_RESOURCES 0x00000100
49 ACPI_CA_DEBUGGER 0x00000200
[all …]
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| D | chromeos-acpi-device.rst | 63 * - 0x00000002
66 * - 0x00000004
70 * - 0x00000020
73 * - 0x00000200
77 All other bits are reserved and should be set to 0.
153 - Set to 256 (0x100). This indicates this field is no longer used.
157 - Set to 256 (0x100). This indicates this field is no longer used.
163 - 0 - Read-only (recovery) firmware
166 Set to 0 if EC firmware is always read-only.
172 - 0 - Recovery
[all …]
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-altera.txt | 6 - compatible : should be "altr,softip-i2c-v1.0"
11 - #size-cells = <0>;
23 compatible = "altr,softip-i2c-v1.0";
24 reg = <0x00000001 0x00080000 0x00000040>;
26 interrupts = <0 43 4>;
30 #size-cells = <0>;
35 reg = <0x51>;
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| /Documentation/userspace-api/media/v4l/ |
| D | metafmt-d4xx.rst | 40 :stub-columns: 0
46 - 0x80000000
61 - Power of the laser LED 0-360, used for depth measurement
63 - 0: manual; 1: automatic exposure
65 - Exposure priority value: 0 - constant frame rate
68 and lie between 0 and maximum width or height respectively)
76 - Preset selector value, default: 0, unless changed by the user
78 - 0: off, 1: on, same as __u32 Laser mode for v1
82 - Led power value 0-360 (F416 SKU)
85 - 0x80000001
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| D | vidioc-reqbufs.rst | 79 :header-rows: 0
80 :stub-columns: 0
98 - Set by the driver. If 0, then the driver doesn't support
105 then this can be called with ``count`` set to 0, ``memory`` set to
129 :header-rows: 0
130 :stub-columns: 0
134 - 0x00000001
137 - 0x00000002
140 - 0x00000004
143 - 0x00000008
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| D | vidioc-subdev-querycap.rst | 46 :header-rows: 0
47 :stub-columns: 0
65 ``__u32 version = KERNEL_VERSION(0, 8, 1);``
69 ``(version >> 16) & 0xFF, (version >> 8) & 0xFF, version & 0xFF);``
76 - Reserved for future extensions. Set to 0 by the V4L2 core.
85 :header-rows: 0
86 :stub-columns: 0
90 - 0x00000001
99 On success 0 is returned, on error -1 and the ``errno`` variable is set
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| D | ext-ctrls-codec-stateless.rst | 44 :header-rows: 0
45 :stub-columns: 0
114 :header-rows: 0
115 :stub-columns: 0
119 - 0x00000001
122 - 0x00000002
125 - 0x00000004
128 - 0x00000008
131 - 0x00000010
134 - 0x00000020
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| D | vidioc-subdev-enum-mbus-code.rst | 39 Each enumeration starts with the ``index`` of 0, and
44 and set ``index`` to 0.
67 :header-rows: 0
68 :stub-columns: 0
109 :header-rows: 0
110 :stub-columns: 0
114 - 0x00000001
121 - 0x00000002
128 - 0x00000004
135 - 0x00000004
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| /Documentation/devicetree/bindings/clock/ |
| D | nxp,imx95-display-master-csr.yaml | 52 reg = <0x4c410000 0x10000>;
60 mux-reg-masks = <0x4 0x00000001>; /* Pixel_link_sel */
61 idle-states = <0>;
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| /Documentation/devicetree/bindings/soc/dove/ |
| D | pmu.txt | 24 - #power-domain-cells: must be 0.
35 reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
43 #power-domain-cells = <0>;
44 marvell,pmu_pwr_mask = <0x00000008>;
45 marvell,pmu_iso_mask = <0x00000001>;
50 #power-domain-cells = <0>;
51 marvell,pmu_pwr_mask = <0x00000004>;
52 marvell,pmu_iso_mask = <0x00000002>;
|
| /Documentation/arch/x86/ |
| D | iommu.rst | 74 Interrupt ranges are not address translated, (0xfee00000 - 0xfeefffff).
105 ACPI: DMAR (v001 A M I OEMDMAR 0x00000001 MSFT 0x00000097) @ 0x000000007f5b5ef0
113 ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed90000
114 ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed91000
115 ACPI DMAR:DRHD (flags: 0x00000001)base: 0x00000000fed93000
116 ACPI DMAR:RMRR base: 0x00000000000ed000 end: 0x00000000000effff
117 ACPI DMAR:RMRR base: 0x000000007f600000 end: 0x000000007fffffff
150 AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0007 address=0xffffc02000 flags=0x0000]
151 AMD-Vi: Event logged [IO_PAGE_FAULT device=07:00.0 domain=0x0007 address=0xffffc02000 flags=0x0000]
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| /Documentation/devicetree/bindings/firmware/ |
| D | gunyah-hypervisor.yaml | 27 description: must be 0, because capability IDs are not memory address
29 const: 0
72 #size-cells = <0>;
75 gunyah-resource-mgr@0 {
79 reg = <0x00000000 0x00000000>, /* TX capability ID */
80 <0x00000000 0x00000001>; /* RX capability ID */
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| /Documentation/devicetree/bindings/thermal/ |
| D | qoriq-thermal.yaml | 20 Register (IPBRR0) at offset 0x0BF8.
24 0x01900102 T1040
82 reg = <0xf0000 0x1000>;
83 interrupts = <18 2 0 0>;
84 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
85 fsl,tmu-calibration = <0x00000000 0x00000025>,
86 <0x00000001 0x00000028>,
87 <0x00000002 0x0000002d>,
88 <0x00000003 0x00000031>,
89 <0x00000004 0x00000036>,
[all …]
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| /Documentation/userspace-api/media/cec/ |
| D | cec-ioc-adap-g-caps.rst | 43 :header-rows: 0
44 :stub-columns: 0
71 :header-rows: 0
72 :stub-columns: 0
78 - 0x00000001
87 - 0x00000002
95 - 0x00000004
105 - 0x00000008
111 - 0x00000010
116 - 0x00000020
[all …]
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| /Documentation/admin-guide/acpi/ |
| D | initrd_table_override.rst | 65 DefinitionBlock ("DSDT.aml", "DSDT", 2, "INTEL ", "TEMPLATE", 0x00000000)
67 DefinitionBlock ("DSDT.aml", "DSDT", 2, "INTEL ", "TEMPLATE", 0x00000001)
92 acpi.debug_level=0x2 acpi.debug_layer=0xFFFFFFFF
95 [ 1.272091] [ACPI Debug] String [0x0B] "HELLO WORLD"
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| /Documentation/devicetree/bindings/memory-controllers/fsl/ |
| D | fsl,imx-weim.yaml | 21 pattern: "^memory-controller@[0-9a-f]+$"
63 WEIM CS GPR register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0]
67 IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3
69 05 128M 0M 0M 0M
70 033 64M 64M 0M 0M
71 0113 64M 32M 32M 0M
75 sets up in IOMUXC_GPR1[11:0] will be used.
90 "^.*@[0-7],[0-9a-f]+$":
133 "^.*@[0-7],[0-9a-f]+$":
149 "^.*@[0-7],[0-9a-f]+$":
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| /Documentation/devicetree/bindings/dma/ |
| D | stericsson,dma40.yaml | 22 0: SPI controller 0
23 1: SD/MMC controller 0 (unused)
35 13: UART port 0
37 15: I2C port 0
42 20: SLIMbus or HSI channel 0
51 29: SD/MMC controller 0
53 31: MSP port 0 or SLIMbus channel 0
83 61: Crypto Accelerator 0
84 62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX
85 63: Hash Accelerator 0 TX
[all …]
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| /Documentation/devicetree/bindings/powerpc/opal/ |
| D | power-mgt.txt | 44 0x00000001 /* Decrementer would stop */
45 0x00000002 /* Needs timebase restore */
46 0x00001000 /* Restore GPRs like nap */
47 0x00002000 /* Restore hypervisor resource from PACA pointer */
48 0x00004000 /* Program PORE to restore PACA pointer */
49 0x00010000 /* This is a nap state (POWER7,POWER8) */
50 0x00020000 /* This is a fast-sleep state (POWER8)*/
51 0x00040000 /* This is a winkle state (POWER8) */
52 0x00080000 /* This is a fast-sleep state which requires a */
55 0x00800000 /* This state uses SPR PMICR instruction */
[all …]
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