Searched +full:0 +full:x00000005 (Results 1 – 5 of 5) sorted by relevance
| /Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra124-emc.yaml | 33 const: 0
51 "^emc-timings-[0-9]+$":
62 "^timing-[0-9]+$":
93 minimum: 0
156 minimum: 0
356 reg = <0x70019000 0x1000>;
369 reg = <0x7001b000 0x1000>;
377 #interconnect-cells = <0>;
379 emc-timings-0 {
382 timing-0 {
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| D | nvidia,tegra20-emc.yaml | 38 const: 0
41 const: 0
145 "^emc-table@[0-9]+$":
165 const: 0
172 "^emc-table@[0-9]+$":
199 reg = <0x7000f400 0x400>;
200 interrupts = <0 78 4>;
207 #interconnect-cells = <0>;
209 #size-cells = <0>;
213 emc-tables@0 {
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| D | nvidia,tegra30-emc.yaml | 35 const: 0
53 "^emc-timings-[0-9]+$":
62 "^timing-[0-9]+$":
75 minimum: 0
91 Mode Register 0.
98 minimum: 0
239 reg = <0x7000f400 0x400>;
240 interrupts = <0 78 4>;
247 #interconnect-cells = <0>;
255 nvidia,emc-auto-cal-interval = <0x001fffff>;
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| /Documentation/devicetree/bindings/thermal/ |
| D | qoriq-thermal.yaml | 20 Register (IPBRR0) at offset 0x0BF8.
24 0x01900102 T1040
82 reg = <0xf0000 0x1000>;
83 interrupts = <18 2 0 0>;
84 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
85 fsl,tmu-calibration = <0x00000000 0x00000025>,
86 <0x00000001 0x00000028>,
87 <0x00000002 0x0000002d>,
88 <0x00000003 0x00000031>,
89 <0x00000004 0x00000036>,
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| /Documentation/driver-api/media/drivers/ |
| D | cx2341x-devel.rst | 23 ivtvctl -O min=0x02000000,max=0x020000ff
32 (Base Address Register 0). The addresses here are offsets relative to the
37 0x00000000-0x00ffffff Encoder memory space
38 0x00000000-0x0003ffff Encode.rom
44 0x01000000-0x01ffffff Decoder memory space
45 0x01000000-0x0103ffff Decode.rom
47 0x0114b000-0x0115afff Audio.rom (deprecated?)
49 0x02000000-0x0200ffff Register Space
54 The registers occupy the 64k space starting at the 0x02000000 offset from BAR0.
59 DMA Registers 0x000-0xff:
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