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/Documentation/devicetree/bindings/usb/
Ddwc3-cavium.txt14 reg = <0x00011800 0x69000000 0x00000000 0x00000100>;
16 #address-cells = <0x00000002>;
17 #size-cells = <0x00000002>;
18 refclk-frequency = <0x05f5e100>;
21 power = <0x00000002 0x00000002 0x00000001>;
24 reg = <0x00016900 0x00000000 0x00000010 0x00000000>;
25 interrupt-parent = <0x00000010>;
26 interrupts = <0x00000009 0x00000004>;
/Documentation/devicetree/bindings/thermal/
Dqoriq-thermal.yaml20 Register (IPBRR0) at offset 0x0BF8.
24 0x01900102 T1040
82 reg = <0xf0000 0x1000>;
83 interrupts = <18 2 0 0>;
84 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
85 fsl,tmu-calibration = <0x00000000 0x00000025>,
86 <0x00000001 0x00000028>,
87 <0x00000002 0x0000002d>,
88 <0x00000003 0x00000031>,
89 <0x00000004 0x00000036>,
[all …]
/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra20-emc.yaml38 const: 0
41 const: 0
145 "^emc-table@[0-9]+$":
165 const: 0
172 "^emc-table@[0-9]+$":
199 reg = <0x7000f400 0x400>;
200 interrupts = <0 78 4>;
207 #interconnect-cells = <0>;
209 #size-cells = <0>;
213 emc-tables@0 {
[all …]
Dnvidia,tegra30-emc.yaml35 const: 0
53 "^emc-timings-[0-9]+$":
62 "^timing-[0-9]+$":
75 minimum: 0
91 Mode Register 0.
98 minimum: 0
239 reg = <0x7000f400 0x400>;
240 interrupts = <0 78 4>;
247 #interconnect-cells = <0>;
255 nvidia,emc-auto-cal-interval = <0x001fffff>;
[all …]