Searched +full:0 +full:x0000000a (Results 1 – 4 of 4) sorted by relevance
| /Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra30-emc.yaml | 35 const: 0 53 "^emc-timings-[0-9]+$": 62 "^timing-[0-9]+$": 75 minimum: 0 91 Mode Register 0. 98 minimum: 0 239 reg = <0x7000f400 0x400>; 240 interrupts = <0 78 4>; 247 #interconnect-cells = <0>; 255 nvidia,emc-auto-cal-interval = <0x001fffff>; [all …]
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| D | nvidia,tegra30-mc.yaml | 64 "^emc-timings-[0-9]+$": 73 "^timing-[0-9]+$": 134 reg = <0x7000f000 0x400>; 138 interrupts = <0 77 4>; 151 0x0000000a /* MC_EMEM_ARB_CFG */ 152 0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */ 153 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ 154 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ 155 0x00000010 /* MC_EMEM_ARB_TIMING_RC */ 156 0x0000000b /* MC_EMEM_ARB_TIMING_RAS */ [all …]
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| D | nvidia,tegra124-emc.yaml | 33 const: 0 51 "^emc-timings-[0-9]+$": 62 "^timing-[0-9]+$": 93 minimum: 0 156 minimum: 0 356 reg = <0x70019000 0x1000>; 369 reg = <0x7001b000 0x1000>; 377 #interconnect-cells = <0>; 379 emc-timings-0 { 382 timing-0 { [all …]
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| /Documentation/devicetree/bindings/thermal/ |
| D | qoriq-thermal.yaml | 20 Register (IPBRR0) at offset 0x0BF8. 24 0x01900102 T1040 82 reg = <0xf0000 0x1000>; 83 interrupts = <18 2 0 0>; 84 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>; 85 fsl,tmu-calibration = <0x00000000 0x00000025>, 86 <0x00000001 0x00000028>, 87 <0x00000002 0x0000002d>, 88 <0x00000003 0x00000031>, 89 <0x00000004 0x00000036>, [all …]
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