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/Documentation/devicetree/bindings/usb/
Ddwc3-cavium.txt14 reg = <0x00011800 0x69000000 0x00000000 0x00000100>;
16 #address-cells = <0x00000002>;
17 #size-cells = <0x00000002>;
18 refclk-frequency = <0x05f5e100>;
21 power = <0x00000002 0x00000002 0x00000001>;
24 reg = <0x00016900 0x00000000 0x00000010 0x00000000>;
25 interrupt-parent = <0x00000010>;
26 interrupts = <0x00000009 0x00000004>;
/Documentation/userspace-api/media/v4l/
Dmetafmt-d4xx.rst40 :stub-columns: 0
46 - 0x80000000
61 - Power of the laser LED 0-360, used for depth measurement
63 - 0: manual; 1: automatic exposure
65 - Exposure priority value: 0 - constant frame rate
68 and lie between 0 and maximum width or height respectively)
76 - Preset selector value, default: 0, unless changed by the user
78 - 0: off, 1: on, same as __u32 Laser mode for v1
82 - Led power value 0-360 (F416 SKU)
85 - 0x80000001
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Dvidioc-enuminput.rst46 :header-rows: 0
47 :stub-columns: 0
66 corresponds to audio input 0, the MSB to input 31. Any number of
109 :header-rows: 0
110 :stub-columns: 0
131 :header-rows: 0
132 :stub-columns: 0
136 - 0x00000001
139 - 0x00000002
142 - 0x00000004
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Dext-ctrls-codec-stateless.rst44 :header-rows: 0
45 :stub-columns: 0
114 :header-rows: 0
115 :stub-columns: 0
119 - 0x00000001
122 - 0x00000002
125 - 0x00000004
128 - 0x00000008
131 - 0x00000010
134 - 0x00000020
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Dvidioc-reqbufs.rst79 :header-rows: 0
80 :stub-columns: 0
98 - Set by the driver. If 0, then the driver doesn't support
105 then this can be called with ``count`` set to 0, ``memory`` set to
129 :header-rows: 0
130 :stub-columns: 0
134 - 0x00000001
137 - 0x00000002
140 - 0x00000004
143 - 0x00000008
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Dvidioc-querycap.rst48 :header-rows: 0
49 :stub-columns: 0
101 ``__u32 version = KERNEL_VERSION(4, 14, 0);``
105 ``(version >> 16) & 0xFF, (version >> 8) & 0xFF, version & 0xFF);``
142 :header-rows: 0
143 :stub-columns: 0
147 - 0x00000001
151 - 0x00001000
155 - 0x00000002
159 - 0x00002000
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Dvidioc-enumstd.rst53 :header-rows: 0
54 :stub-columns: 0
92 :header-rows: 0
93 :stub-columns: 0
108 :header-rows: 0
109 :stub-columns: 0
122 #define V4L2_STD_PAL_B ((v4l2_std_id)0x00000001)
123 #define V4L2_STD_PAL_B1 ((v4l2_std_id)0x00000002)
124 #define V4L2_STD_PAL_G ((v4l2_std_id)0x00000004)
125 #define V4L2_STD_PAL_H ((v4l2_std_id)0x00000008)
[all …]
Dbuffer.rst91 #. VIDIOC_REQBUFS(0)
165 :header-rows: 0
166 :stub-columns: 0
290 must set this to 0.
320 :header-rows: 0
321 :stub-columns: 0
333 which may not be 0.
390 :header-rows: 0
391 :stub-columns: 0
457 :header-rows: 0
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/Documentation/devicetree/bindings/pci/
Daltr,msi-controller.yaml58 reg = <0xff200000 0x00000010>,
59 <0xff200010 0x00000080>;
/Documentation/devicetree/bindings/thermal/
Dqoriq-thermal.yaml20 Register (IPBRR0) at offset 0x0BF8.
24 0x01900102 T1040
82 reg = <0xf0000 0x1000>;
83 interrupts = <18 2 0 0>;
84 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
85 fsl,tmu-calibration = <0x00000000 0x00000025>,
86 <0x00000001 0x00000028>,
87 <0x00000002 0x0000002d>,
88 <0x00000003 0x00000031>,
89 <0x00000004 0x00000036>,
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/Documentation/firmware-guide/acpi/
Ddebug.rst40 ACPI_UTILITIES 0x00000001
41 ACPI_HARDWARE 0x00000002
42 ACPI_EVENTS 0x00000004
43 ACPI_TABLES 0x00000008
44 ACPI_NAMESPACE 0x00000010
45 ACPI_PARSER 0x00000020
46 ACPI_DISPATCHER 0x00000040
47 ACPI_EXECUTER 0x00000080
48 ACPI_RESOURCES 0x00000100
49 ACPI_CA_DEBUGGER 0x00000200
[all …]
/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra30-mc.yaml64 "^emc-timings-[0-9]+$":
73 "^timing-[0-9]+$":
134 reg = <0x7000f000 0x400>;
138 interrupts = <0 77 4>;
151 0x0000000a /* MC_EMEM_ARB_CFG */
152 0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */
153 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */
154 0x00000004 /* MC_EMEM_ARB_TIMING_RP */
155 0x00000010 /* MC_EMEM_ARB_TIMING_RC */
156 0x0000000b /* MC_EMEM_ARB_TIMING_RAS */
[all …]
/Documentation/firmware-guide/acpi/apei/
Deinj.rst13 ACPI: EINJ 0x000000007370A000 000150 (v01 INTEL 00000001 INTL 00000001)
50 0x00000001 Processor Correctable
51 0x00000002 Processor Uncorrectable non-fatal
52 0x00000004 Processor Uncorrectable fatal
53 0x00000008 Memory Correctable
54 0x00000010 Memory Uncorrectable non-fatal
55 0x00000020 Memory Uncorrectable fatal
56 0x00000040 PCI Express Correctable
57 0x00000080 PCI Express Uncorrectable non-fatal
58 0x00000100 PCI Express Uncorrectable fatal
[all …]
/Documentation/userspace-api/media/cec/
Dcec-ioc-adap-g-caps.rst43 :header-rows: 0
44 :stub-columns: 0
71 :header-rows: 0
72 :stub-columns: 0
78 - 0x00000001
87 - 0x00000002
95 - 0x00000004
105 - 0x00000008
111 - 0x00000010
116 - 0x00000020
[all …]
/Documentation/devicetree/bindings/dma/
Dstericsson,dma40.yaml22 0: SPI controller 0
23 1: SD/MMC controller 0 (unused)
35 13: UART port 0
37 15: I2C port 0
42 20: SLIMbus or HSI channel 0
51 29: SD/MMC controller 0
53 31: MSP port 0 or SLIMbus channel 0
83 61: Crypto Accelerator 0
84 62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX
85 63: Hash Accelerator 0 TX
[all …]
/Documentation/devicetree/bindings/net/
Dibm,emac.txt29 ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on
40 For Axon, 0x00000010
43 For Axon, 0x00000100 (I think ...)
54 channel or 0xffffffff if ZMII is only used for MDIO.
68 for, used if phy-address is absent. bit 0x00000001 is
69 MDIO address 0.
72 0x00ffffff in it.
95 - #size-cells: Must be <0>.
111 mal-tx-channel = <0 1>;
112 mal-rx-channel = <0>;
[all …]
/Documentation/driver-api/
Dmtdnand.rst141 .offset = 0,
197 should return 0, if the device is busy (R/B pin is low) and 1, if the
217 int err = 0;
325 GPIO(BOARD_NAND_NCE) |= 0xff;
326 if (chip >= 0)
344 case 0:
654 terminated by an {0, 0} entry.
667 <spare data page 0><ecc result 0>...<ecc result n>
671 <spare data page n><ecc result 0>...<ecc result n>
699 0x00 ECC byte 0 Error correction code byte 0
[all …]
/Documentation/admin-guide/
Dxfs.rst255 delaylog/nodelaylog v4.0
256 ihashsize v4.0
257 irixsgid v4.0
258 osyncisdsync/osyncisosync v4.0
268 fs.xfs.stats_clear (Min: 0 Default: 0 Max: 1)
270 in /proc/fs/xfs/stat. It then immediately resets to "0".
291 fs.xfs.error_level (Min: 0 Default: 3 Max: 11)
296 XFS_ERRLEVEL_OFF: 0
300 fs.xfs.panic_mask (Min: 0 Default: 0 Max: 511)
304 XFS_NO_PTAG 0
[all …]
/Documentation/scsi/
Dsym53c8xx_2.rst294 - target 2 all luns on controller 0 --> 15
295 - target 3 all luns on controller 0 --> 15
296 - target 4 all luns on controller 0 --> 7
297 - target 1 lun 0 on controller 1 --> 32
319 boot your system using 'sym53c8xx=verb:0' option.
321 apply "setverbose 0" control command to the proc fs entry
348 echo "<verb> <parameters>" >/proc/scsi/sym53c8xx/0
349 (assumes controller number is 0)
366 Specify a period of 0, to force asynchronous transfer mode.
379 :size: 0=8 bits, 1=16bits
[all …]
Dncr53c8xx.rst253 - SYM53C810 revision < 0x10 (16)
255 - SYM53C825 revision < 0x10 (16)
314 - target 2 all luns on controller 0 --> 15
315 - target 3 all luns on controller 0 --> 15
316 - target 4 all luns on controller 0 --> 7
317 - target 1 lun 0 on controller 1 --> 32
339 boot your system using 'ncr53c8xx=verb:0' option.
342 apply "setverbose 0" control command to the proc fs entry
365 /proc/scsi/ncr53c8xx/N (N=0,1,2 ....)
369 /proc/scsi/ncr53c8xx/0
[all …]
/Documentation/networking/
Dfilter.rst108 { 0x28, 0, 0, 0x0000000c },
109 { 0x15, 0, 8, 0x000086dd },
110 { 0x30, 0, 0, 0x00000014 },
111 { 0x15, 2, 0, 0x00000084 },
112 { 0x15, 1, 0, 0x00000006 },
113 { 0x15, 0, 17, 0x00000011 },
114 { 0x28, 0, 0, 0x00000036 },
115 { 0x15, 14, 0, 0x00000016 },
116 { 0x28, 0, 0, 0x00000038 },
117 { 0x15, 12, 13, 0x00000016 },
[all …]
/Documentation/ABI/testing/
Dsysfs-fs-f2fs23 Setting gc_idle = 0(default) will disable this option. Setting:
54 0x00 DISABLE disable IPU(=default option in LFS mode)
55 0x01 FORCE all the time
56 0x02 SSR if SSR mode is activated
57 0x04 UTIL if FS utilization is over threshold
58 0x08 SSR_UTIL if SSR mode is activated and FS utilization is over
60 0x10 FSYNC activated in fsync path only for high performance
64 0x20 ASYNC do IPU given by asynchronous write requests
65 0x40 NOCACHE disable IPU bio cache
66 0x80 HONOR_OPU_WRITE use OPU write prior to IPU write if inode has
[all …]