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/Documentation/devicetree/bindings/mtd/
Dibm,ndfc.txt5 - reg : should specify chip select and size used for the chip (0x2000).
8 - ccr : NDFC config and control register value (default 0).
9 - bank-settings : NDFC bank configuration register value (default 0).
16 ndfc@1,0 {
18 reg = <0x00000001 0x00000000 0x00002000>;
19 ccr = <0x00001000>;
20 bank-settings = <0x80002222>;
28 partition@0 {
30 reg = <0x00000000 0x00200000>;
34 reg = <0x00200000 0x03E00000>;
Dmtd-physmap.yaml154 reg = <0xff000000 0x01000000>;
160 ranges = <0 0xff000000 0x01000000>;
162 fs@0 {
164 reg = <0 0xf80000>;
168 reg = <0xf80000 0x80000>;
176 flash@0 {
178 reg = <0x00000000 0x02000000>,
179 <0x02000000 0x02000000>;
184 ranges = <0 0 0x04000000>;
186 partition@0 {
[all …]
Datmel-nand.txt38 device (always 0)
39 3rd entry: the memory region size (always 0x800000)
67 reg = <0x70000000 0x8000000>;
72 reg = <0xffffc070 0x490>,
73 <0xffffc500 0x100>;
81 reg = <0x10000000 0x10000000
82 0x40000000 0x30000000>;
83 ranges = <0x0 0x0 0x10000000 0x10000000
84 0x1 0x0 0x40000000 0x10000000
85 0x2 0x0 0x50000000 0x10000000
[all …]
/Documentation/devicetree/bindings/bus/
Dsocionext,uniphier-system-bus.yaml45 implementation defined. Some SoCs can use 0x00000000-0x0fffffff and
46 0x40000000-0x4fffffff, while other SoCs only 0x40000000-0x4fffffff.
53 bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
55 bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
61 "^.*@[1-5],[1-9a-f][0-9a-f]+$":
77 // - the Ethernet device is connected at the offset 0x01f00000 of CS1 and
78 // mapped to 0x43f00000 of the parent bus.
79 // - the UART device is connected at the offset 0x00200000 of CS5 and
80 // mapped to 0x46200000 of the parent bus.
84 reg = <0x58c00000 0x400>;
[all …]
/Documentation/devicetree/bindings/display/
Dsm501fb.txt25 display@1,0 {
27 reg = <1 0x00000000 0x00800000
28 1 0x03e00000 0x00200000>;
/Documentation/devicetree/bindings/pci/
Dintel,keembay-pcie.yaml79 reg = <0x37000000 0x00001000>,
80 <0x37300000 0x00001000>,
81 <0x36e00000 0x00200000>,
82 <0x37800000 0x00000200>;
87 ranges = <0x02000000 0 0x36000000 0x36000000 0 0x00e00000>;
Dmobiveil-pcie.txt49 reg = <0xa0000000 0x00001000>,
50 <0xb0000000 0x00010000>,
51 <0xff000000 0x00200000>,
52 <0xb0010000 0x00001000>;
60 bus-range = <0x00000000 0x000000ff>;
64 interrupts = < 0 89 4 >;
65 interrupt-map-mask = <0 0 0 7>;
66 interrupt-map = <0 0 0 0 &pci_express 0>,
67 <0 0 0 1 &pci_express 1>,
68 <0 0 0 2 &pci_express 2>,
[all …]
Drcar-pci-host.yaml115 reg = <0 0xfe000000 0 0x80000>;
118 bus-range = <0x00 0xff>;
120 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
121 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
122 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
123 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
124 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>,
125 <0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
130 interrupt-map-mask = <0 0 0 0>;
131 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
/Documentation/devicetree/bindings/powerpc/4xx/
Dppc440spe-adma.txt23 reg = <0x00000004 0x00100000 0x100>;
24 dcr-reg = <0x060 0x020>;
34 (typically 0x0 and 0x1 for DMA0 and DMA1)
46 cell-index = <0>;
47 reg = <0x00000004 0x00100100 0x100>;
48 dcr-reg = <0x060 0x020>;
50 interrupts = <0 1>;
52 #address-cells = <0>;
53 #size-cells = <0>;
55 0 &UIC0 0x14 4
[all …]
/Documentation/devicetree/bindings/usb/
Dda8xx-usb.txt37 channel number (0 … 3 for endpoints 1 … 4).
38 The second number is 0 for RX and 1 for TX transfers.
45 #phy-cells = <0>;
49 reg = <0x00200000 0x1000>;
58 phys = <&usb_phy 0>;
61 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
62 &cppi41dma 2 0 &cppi41dma 3 0
63 &cppi41dma 0 1 &cppi41dma 1 1
72 reg = <0x201000 0x1000
73 0x202000 0x1000
[all …]
/Documentation/firmware-guide/acpi/
Ddebug.rst40 ACPI_UTILITIES 0x00000001
41 ACPI_HARDWARE 0x00000002
42 ACPI_EVENTS 0x00000004
43 ACPI_TABLES 0x00000008
44 ACPI_NAMESPACE 0x00000010
45 ACPI_PARSER 0x00000020
46 ACPI_DISPATCHER 0x00000040
47 ACPI_EXECUTER 0x00000080
48 ACPI_RESOURCES 0x00000100
49 ACPI_CA_DEBUGGER 0x00000200
[all …]
/Documentation/devicetree/bindings/powerpc/opal/
Dpower-mgt.txt44 0x00000001 /* Decrementer would stop */
45 0x00000002 /* Needs timebase restore */
46 0x00001000 /* Restore GPRs like nap */
47 0x00002000 /* Restore hypervisor resource from PACA pointer */
48 0x00004000 /* Program PORE to restore PACA pointer */
49 0x00010000 /* This is a nap state (POWER7,POWER8) */
50 0x00020000 /* This is a fast-sleep state (POWER8)*/
51 0x00040000 /* This is a winkle state (POWER8) */
52 0x00080000 /* This is a fast-sleep state which requires a */
55 0x00800000 /* This state uses SPR PMICR instruction */
[all …]
/Documentation/userspace-api/media/v4l/
Dvidioc-querycap.rst48 :header-rows: 0
49 :stub-columns: 0
101 ``__u32 version = KERNEL_VERSION(4, 14, 0);``
105 ``(version >> 16) & 0xFF, (version >> 8) & 0xFF, version & 0xFF);``
142 :header-rows: 0
143 :stub-columns: 0
147 - 0x00000001
151 - 0x00001000
155 - 0x00000002
159 - 0x00002000
[all …]
Dvidioc-enumstd.rst53 :header-rows: 0
54 :stub-columns: 0
92 :header-rows: 0
93 :stub-columns: 0
108 :header-rows: 0
109 :stub-columns: 0
122 #define V4L2_STD_PAL_B ((v4l2_std_id)0x00000001)
123 #define V4L2_STD_PAL_B1 ((v4l2_std_id)0x00000002)
124 #define V4L2_STD_PAL_G ((v4l2_std_id)0x00000004)
125 #define V4L2_STD_PAL_H ((v4l2_std_id)0x00000008)
[all …]
/Documentation/driver-api/media/drivers/
Dcx2341x-devel.rst23 ivtvctl -O min=0x02000000,max=0x020000ff
32 (Base Address Register 0). The addresses here are offsets relative to the
37 0x00000000-0x00ffffff Encoder memory space
38 0x00000000-0x0003ffff Encode.rom
44 0x01000000-0x01ffffff Decoder memory space
45 0x01000000-0x0103ffff Decode.rom
47 0x0114b000-0x0115afff Audio.rom (deprecated?)
49 0x02000000-0x0200ffff Register Space
54 The registers occupy the 64k space starting at the 0x02000000 offset from BAR0.
59 DMA Registers 0x000-0xff:
[all …]