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/Documentation/devicetree/bindings/ata/
Dintel,ixp4xx-compact-flash.yaml48 reg = <0xc4000000 0x1000>;
52 ranges = <0 0x0 0x50000000 0x01000000>, <1 0x0 0x51000000 0x01000000>;
53 dma-ranges = <0 0x0 0x50000000 0x01000000>, <1 0x0 0x51000000 0x01000000>;
54 ide@1,0 {
56 reg = <1 0x00000000 0x1000>, <1 0x00040000 0x1000>;
/Documentation/devicetree/bindings/memory-controllers/
Dintel,ixp4xx-expansion-bus-controller.yaml19 pattern: '^bus@[0-9a-f]+$'
55 "^.*@[0-7],[0-9a-f]+$":
78 reg = <0xc4000000 0x28>;
82 ranges = <0 0x0 0x50000000 0x01000000>,
83 <1 0x0 0x51000000 0x01000000>;
84 dma-ranges = <0 0x0 0x50000000 0x01000000>,
85 <1 0x0 0x51000000 0x01000000>;
86 flash@0,0 {
89 reg = <0 0x00000000 0x1000000>;
91 intel,ixp4xx-eb-cycle-type = <0>;
[all …]
/Documentation/devicetree/bindings/gpu/
Dnvidia,gk20a.txt46 reg = <0x0 0x57000000 0x0 0x01000000>,
47 <0x0 0x58000000 0x0 0x01000000>;
64 reg = <0x0 0x57000000 0x0 0x01000000>,
65 <0x0 0x58000000 0x0 0x01000000>;
82 reg = <0x0 0x17000000 0x0 0x1000000>,
83 <0x0 0x18000000 0x0 0x1000000>;
100 reg = <0x17000000 0x1000000>,
101 <0x18000000 0x1000000>;
Daspeed-gfx.txt28 reg = <0x1e6e6000 0x1000>;
32 interrupts = <0x19>;
37 size = <0x01000000>;
38 alignment = <0x01000000>;
/Documentation/devicetree/bindings/mtd/
Dti,gpmc-onenand.yaml19 pattern: "^onenand@[0-9],[0,9]$"
38 "@[0-9a-f]+$":
56 reg = <0x6e000000 0x02d0>;
65 ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */
66 <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */
68 onenand@0,0 {
70 reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
74 partition@0 {
76 reg = <0x00000000 0x00100000>;
81 reg = <0x00100000 0x002c0000>;
Dmtd-physmap.yaml154 reg = <0xff000000 0x01000000>;
160 ranges = <0 0xff000000 0x01000000>;
162 fs@0 {
164 reg = <0 0xf80000>;
168 reg = <0xf80000 0x80000>;
176 flash@0 {
178 reg = <0x00000000 0x02000000>,
179 <0x02000000 0x02000000>;
184 ranges = <0 0 0x04000000>;
186 partition@0 {
[all …]
/Documentation/devicetree/bindings/pci/
Dcdns,cdns-pcie-host.yaml44 bus-range = <0x0 0xff>;
45 linux,pci-domain = <0>;
46 vendor-id = <0x17cd>;
47 device-id = <0x0200>;
49 reg = <0x0 0xfb000000 0x0 0x01000000>,
50 <0x0 0x41000000 0x0 0x00001000>;
53 ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>,
54 <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;
55 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
57 #interrupt-cells = <0x1>;
[all …]
Dv3-v360epc-pci.txt18 each be exactly 256MB (0x10000000) in size.
38 reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
42 bus-range = <0x00 0xff>;
43 ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */
44 0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */
45 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
46 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
47 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
48 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
49 dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
[all …]
Dhisilicon-histb-pcie.txt38 - phys: List of phandle and phy mode specifier, should be 0.
44 reg = <0xf9860000 0x1000>,
45 <0xf0000000 0x2000>,
46 <0xf2000000 0x01000000>;
51 bus-range = <0 15>;
53 ranges=<0x81000000 0 0 0xf4000000 0 0x00010000
54 0x82000000 0 0xf3000000 0xf3000000 0 0x01000000>;
58 interrupt-map-mask = <0 0 0 0>;
59 interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
65 resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
Dhost-generic-pci.yaml94 property. If no "bus-range" is specified, this will be bus 0 (the
160 bus-range = <0x0 0x1>;
163 reg = <0x0 0x40000000 0x0 0x1000000>;
166 ranges = <0x01000000 0x0 0x01000000 0x0 0x01000000 0x0 0x00010000>,
167 <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x3f000000>;
169 #interrupt-cells = <0x1>;
172 interrupt-map = < 0x0 0x0 0x0 0x1 &gic 0x0 0x4 0x1>,
173 < 0x800 0x0 0x0 0x1 &gic 0x0 0x5 0x1>,
174 <0x1000 0x0 0x0 0x1 &gic 0x0 0x6 0x1>,
175 <0x1800 0x0 0x0 0x1 &gic 0x0 0x7 0x1>;
[all …]
Dcdns,cdns-pcie-ep.yaml41 reg = <0x0 0xfc000000 0x0 0x01000000>,
42 <0x0 0x80000000 0x0 0x40000000>;
Dloongson.yaml56 reg = <0x0 0x1a000000 0x0 0x2000000>;
59 ranges = <0x01000000 0x0 0x00004000 0x0 0x00004000 0x0 0x00004000>,
60 <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
D83xx-512x-pci.txt12 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
14 /* IDSEL 0x0E -mini PCI */
15 0x7000 0x0 0x0 0x1 &ipic 18 0x8
16 0x7000 0x0 0x0 0x2 &ipic 18 0x8
17 0x7000 0x0 0x0 0x3 &ipic 18 0x8
18 0x7000 0x0 0x0 0x4 &ipic 18 0x8
20 /* IDSEL 0x0F - PCI slot */
21 0x7800 0x0 0x0 0x1 &ipic 17 0x8
22 0x7800 0x0 0x0 0x2 &ipic 18 0x8
23 0x7800 0x0 0x0 0x3 &ipic 17 0x8
[all …]
Dfsl,imx6q-pcie.yaml212 reg = <0x01ffc000 0x04000>,
213 <0x01f00000 0x80000>;
218 bus-range = <0x00 0xff>;
219 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>,
220 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
225 interrupt-map-mask = <0 0 0 0x7>;
226 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
227 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
228 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
229 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
Dintel,keembay-pcie-ep.yaml57 reg = <0x37000000 0x00001000>,
58 <0x37100000 0x00001000>,
59 <0x37300000 0x00001000>,
60 <0x36000000 0x01000000>,
61 <0x37800000 0x00000200>;
Dxgene-pci.txt35 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
36 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
38 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
39 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
40 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
41 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
42 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
43 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
44 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
45 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
[all …]
Dversatile.yaml38 - const: 0x1800
39 - const: 0
40 - const: 0
58 reg = <0x10001000 0x1000>,
59 <0x41000000 0x10000>,
60 <0x42000000 0x100000>;
61 bus-range = <0 0xff>;
67 <0x01000000 0 0x00000000 0x43000000 0 0x00010000>, /* downstream I/O */
68 <0x02000000 0 0x50000000 0x50000000 0 0x10000000>, /* non-prefetchable memory */
69 <0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
[all …]
Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]
Dxgene-pci-msi.txt8 - reg: physical base address (0x79000000) and length (0x900000) for controller
13 interrupt number 0x10 to 0x1f.
27 reg = <0x00 0x79000000 0x0 0x900000>;
28 interrupts = <0x0 0x10 0x4>
29 <0x0 0x11 0x4>
30 <0x0 0x12 0x4>
31 <0x0 0x13 0x4>
32 <0x0 0x14 0x4>
33 <0x0 0x15 0x4>
34 <0x0 0x16 0x4>
[all …]
/Documentation/devicetree/bindings/remoteproc/
Dst-rproc.txt29 reg = <0x42000000 0x01000000>;
40 st,syscfg = <&syscfg_core 0x228>;
/Documentation/devicetree/bindings/misc/
Difm-csi.txt22 csi@3,0 {
24 reg = <3 0 0x00100000>; /* CS 3, 1 MiB range */
28 gpios = <&gpio_simple 23 0 /* image_capture */
29 &gpio_simple 26 0 /* image_reset */
30 &gpio_simple 29 0>; /* image_master_en */
34 ifm,csi-wait-cycles = <0>;
40 ranges = <0 0 0xff000000 0x01000000
41 3 0 0xe3000000 0x00100000>;
/Documentation/devicetree/bindings/clock/
Dallwinner,sun8i-a83t-de2-clk.yaml69 reg = <0x01000000 0x100000>;
/Documentation/devicetree/bindings/pinctrl/
Dqcom,ipq4019-pinctrl.yaml39 "-hog(-[0-9]+)?$":
59 pattern: "^gpio([0-9]|[1-9][0-9])$"
89 reg = <0x01000000 0x300000>;
93 gpio-ranges = <&tlmm 0 0 100>;
Dqcom,mdm9615-pinctrl.yaml50 pattern: "^gpio([0-9]|[1-7][0-9]|8[0-7])$"
76 reg = <0x01000000 0x300000>;
79 gpio-ranges = <&msmgpio 0 0 88>;
Dqcom,ipq9574-tlmm.yaml57 pattern: "^gpio([0-9]|[1-5][0-9]|6[0-4])$"
100 reg = <0x01000000 0x300000>;
106 gpio-ranges = <&tlmm 0 0 65>;

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