| /Documentation/devicetree/bindings/dma/ |
| D | nvidia,tegra20-apbdma.txt | 23 reg = <0x6000a000 0x1200>;
24 interrupts = < 0 136 0x04
25 0 137 0x04
26 0 138 0x04
27 0 139 0x04
28 0 140 0x04
29 0 141 0x04
30 0 142 0x04
31 0 143 0x04
32 0 144 0x04
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-ep9301.yaml | 70 reg = <0x80840000 0x04>,
71 <0x80840010 0x04>,
72 <0x80840090 0x1c>;
84 reg = <0x80840004 0x04>,
85 <0x80840014 0x04>,
86 <0x808400ac 0x1c>;
98 reg = <0x80840008 0x04>,
99 <0x80840018 0x04>;
107 reg = <0x8084000c 0x04>,
108 <0x8084001c 0x04>;
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-event_source-devices-dfl_fme | 13 event = "config:0-11" - event ID
19 fab_mmio_read = "event=0x06,evtype=0x02,portid=0xff"
21 It shows this fab_mmio_read is a fabric type (0x02) event with
22 0x06 local event id for overall monitoring (portid=0xff).
43 Basic events (evtype=0x00)::
45 clock = "event=0x00,evtype=0x00,portid=0xff"
47 Cache events (evtype=0x01)::
49 cache_read_hit = "event=0x00,evtype=0x01,portid=0xff"
50 cache_read_miss = "event=0x01,evtype=0x01,portid=0xff"
51 cache_write_hit = "event=0x02,evtype=0x01,portid=0xff"
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| /Documentation/devicetree/bindings/input/ |
| D | brcm,bcm-keypad.txt | 31 KEYPAD_DEBOUNCE_1_ms = 0
42 KEYPAD_DEBOUNCE_1_ms = 0
76 linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_F) /* key_forward */
77 MATRIX_KEY(0x00, 0x03, KEY_HOME) /* key_home */
78 MATRIX_KEY(0x00, 0x04, KEY_M) /* key_message */
79 MATRIX_KEY(0x01, 0x00, KEY_A) /* key_contacts */
80 MATRIX_KEY(0x01, 0x01, KEY_1) /* key_1 */
81 MATRIX_KEY(0x01, 0x02, KEY_2) /* key_2 */
82 MATRIX_KEY(0x01, 0x03, KEY_3) /* key_3 */
83 MATRIX_KEY(0x01, 0x04, KEY_S) /* key_speaker */
[all …]
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| D | google,cros-ec-keyb.yaml | 43 (((row) & 0xFF) << 24) | (((column) & 0xFF) << 16)
77 MATRIX_KEY(0x00, 0x02, 0) /* T1 */
78 MATRIX_KEY(0x03, 0x02, 0) /* T2 */
79 MATRIX_KEY(0x02, 0x02, 0) /* T3 */
80 MATRIX_KEY(0x01, 0x02, 0) /* T4 */
81 MATRIX_KEY(0x03, 0x04, 0) /* T5 */
82 MATRIX_KEY(0x02, 0x04, 0) /* T6 */
83 MATRIX_KEY(0x01, 0x04, 0) /* T7 */
84 MATRIX_KEY(0x02, 0x09, 0) /* T8 */
85 MATRIX_KEY(0x01, 0x09, 0) /* T9 */
[all …]
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| D | input-reset.txt | 26 keyset = <0x03
27 0x04
28 0x0a>;
|
| /Documentation/devicetree/bindings/pinctrl/ |
| D | brcm,nsp-pinmux.txt | 28 reg = <0x1803f1c0 0x04>,
29 <0x18030028 0x04>,
30 <0x1803f408 0x04>;
33 pinctrl-0 = <&pwm>, <&gpio_b>, <&nand_sel>;
|
| /Documentation/devicetree/bindings/display/tegra/ |
| D | nvidia,tegra20-host1x.yaml | 175 use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
211 - description: host1x syncpoint interrupt 0
235 use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
251 reg = <0x50000000 0x00024000>;
252 interrupts = <0 65 0x04>, /* mpcore syncpt */
253 <0 67 0x04>; /* mpcore general */
263 ranges = <0x54000000 0x54000000 0x04000000>;
267 reg = <0x54040000 0x00040000>;
268 interrupts = <0 68 0x04>;
276 reg = <0x54080000 0x00040000>;
[all …]
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| /Documentation/devicetree/bindings/leds/ |
| D | register-bit-led.yaml | 26 pattern: '^led@[0-9a-f]+,[0-9a-f]{1,2}$'
41 [ 0x1, 0x2, 0x4, 0x8, 0x10, 0x20, 0x40, 0x80, 0x100, 0x200, 0x400, 0x800,
42 0x1000, 0x2000, 0x4000, 0x8000, 0x10000, 0x20000, 0x40000, 0x80000,
43 0x100000, 0x200000, 0x400000, 0x800000, 0x1000000, 0x2000000, 0x4000000,
44 0x8000000, 0x10000000, 0x20000000, 0x40000000, 0x80000000 ]
64 reg = <0x10000000 0x1000>;
67 ranges = <0x0 0x10000000 0x1000>;
69 led@8,0 {
71 reg = <0x08 0x04>;
72 offset = <0x08>;
[all …]
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| /Documentation/devicetree/bindings/reset/ |
| D | lantiq,reset.yaml | 47 reg = <0x10 0x04>, <0x14 0x04>;
|
| D | brcm,bcm4908-misc-pcie-reset.yaml | 37 reg = <0xff802644 0x04>;
|
| /Documentation/devicetree/bindings/pci/ |
| D | mvebu-pci.txt | 23 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
32 registers area. This range entry translates the '0x82000000 0 r' PCI
33 address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
34 of the internal register window (as identified by MBUS_ID(0xf0,
35 0x01)).
39 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
79 value is 0.
99 bus-range = <0x00 0xff>;
103 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
104 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
[all …]
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| /Documentation/driver-api/media/drivers/ |
| D | tuners.rst | 12 - L= LG_API (VHF_LO=0x01, VHF_HI=0x02, UHF=0x08, radio=0x04)
13 - P= PHILIPS_API (VHF_LO=0xA0, VHF_HI=0x90, UHF=0x30, radio=0x04)
14 - T= TEMIC_API (VHF_LO=0x02, VHF_HI=0x04, UHF=0x01)
15 - A= ALPS_API (VHF_LO=0x14, VHF_HI=0x12, UHF=0x11)
16 - M= PHILIPS_MK3 (VHF_LO=0x01, VHF_HI=0x02, UHF=0x04, radio=0x19)
113 - TADC-M201D: PAL D/K+B/G+I (L,143/425) (sound control at I2C address 0xc8)
131 - TSBE1 has extra API 05,02,08 Control_byte=0xCB Source:[#f1]_
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| /Documentation/devicetree/bindings/net/ |
| D | marvell-neta-bm.txt | 12 - pool<0 : 3>,capacity: size of external buffer pointers' ring maintained
13 in DRAM. Can be set for each pool (id 0 : 3) separately. The value has
17 - pool<0 : 3>,pkt-size: maximum size of a packet accepted by a given buffer
18 pointers' pool (id 0 : 3). It will be taken into consideration only when pool
31 reg = <0xc8000 0xac>;
42 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
43 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
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| /Documentation/devicetree/bindings/sound/ |
| D | cs35l35.txt | 27 0 = Data Packet received on Left I2S Channel
31 0 = Data Packet received on Left I2S Channel
43 0 = 1x (Default)
47 0 - Hi-Z
48 2 - Drive 0's (Default)
144 reg = <0x20>;
147 reset-gpios = <&axi_gpio 54 0>;
153 cirrus,audio-channel = <0x00>;
154 cirrus,advisory-channel = <0x01>;
159 cirrus,classh-bst-max-limit = <0x01>;
[all …]
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | mrvl,intc.yaml | 110 reg = <0xd4282000 0x1000>;
119 reg = <0x150 0x4>, <0x168 0x4>;
128 reg = <0xfed20204 0x04>,
129 <0xfed20214 0x04>;
|
| /Documentation/devicetree/bindings/input/touchscreen/ |
| D | egalax-ts.txt | 14 reg = <0x04>;
|
| /Documentation/admin-guide/media/ |
| D | si476x.rst | 41 0x00 blend_int Flag, set when stereo separation has
43 0x01 hblend_int Flag, set when HiBlend cutoff
45 0x02 hicut_int Flag, set when HiCut cutoff
47 0x03 chbw_int Flag, set when channel filter
49 0x04 softmute_int Flag indicating that softmute
52 0x05 smute 0 - Audio is not soft muted
54 0x06 smattn Soft mute attenuation level in dB
55 0x07 chbw Channel filter bandwidth in kHz
56 0x08 hicut HiCut cutoff frequency in units of
58 0x09 hiblend HiBlend cutoff frequency in units
[all …]
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| /Documentation/devicetree/bindings/watchdog/ |
| D | sunplus,sp7021-wdt.yaml | 43 reg = <0x9c000630 0x08>, <0x9c000274 0x04>;
44 clocks = <&clkc 0x24>;
45 resets = <&rstc 0x14>;
|
| /Documentation/devicetree/bindings/rng/ |
| D | timeriomem_rng.yaml | 22 default: 0
46 reg = <0x44 0x04>;
|
| /Documentation/devicetree/bindings/clock/ |
| D | vf610-clock.txt | 29 reg = <0x4006b000 0x1000>;
37 reg = <0x40028000 0x1000>;
38 interrupts = <0 62 0x04>;
|
| /Documentation/devicetree/bindings/rtc/ |
| D | brcm,brcmstb-waketimer.yaml | 47 reg = <0xf041a080 0x14>;
48 interrupts-extended = <&aon_pm_l2_intc 0x04>,
49 <&upg_aux_aon_intr2_intc 0x08>;
|
| D | nvidia,tegra20-rtc.yaml | 58 reg = <0x7000e000 0x100>;
59 interrupts = <0 2 0x04>;
|
| /Documentation/devicetree/bindings/misc/ |
| D | nvidia,tegra20-apbmisc.yaml | 49 reg = <0x70000800 0x64>, /* Chip revision */
50 <0x70000008 0x04>; /* Strapping options */
|
| /Documentation/devicetree/bindings/net/can/ |
| D | bosch,m_can.yaml | 66 0x0 if you're using a private Message RAM. The remain cells
70 11-bit Filter 0-128 elements / 0-128 words
71 29-bit Filter 0-64 elements / 0-128 words
72 Rx FIFO 0 0-64 elements / 0-1152 words
73 Rx FIFO 1 0-64 elements / 0-1152 words
74 Rx Buffers 0-64 elements / 0-1152 words
75 Tx Event FIFO 0-32 elements / 0-64 words
76 Tx Buffers 0-32 elements / 0-576 words
83 the following elements start from. This is usually set to 0x0 if
85 default: 0
[all …]
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