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/Documentation/devicetree/bindings/net/
Dcavium-mdio.txt15 - #size-cells: Must be <0>. MDIO addresses have no size component.
23 #size-cells = <0>;
24 reg = <0x11800 0x00001800 0x0 0x40>;
26 ethernet-phy@0 {
28 reg = <0>;
58 reg = <0x0b00 0 0 0 0>; /* DEVFN = 0x0b (1:3) */
59 assigned-addresses = <0x03000000 0x87e0 0x05000000 0x0 0x800000>;
60 ranges = <0x87e0 0x05000000 0x03000000 0x87e0 0x05000000 0x0 0x800000>;
65 #size-cells = <0>;
66 reg = <0x87e0 0x05003800 0x0 0x30>;
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/Documentation/devicetree/bindings/memory-controllers/
Dexynos-srom.yaml35 <bank-number> 0 <parent address of bank> <size>
39 "^.*@[0-3],[a-f0-9]+$":
53 typically 0 as this is the start of the bank.
77 Tacp: Page mode access cycle at Page mode (0 - 15)
78 Tcah: Address holding time after CSn (0 - 15)
79 Tcoh: Chip selection hold on OEn (0 - 15)
80 Tacc: Access cycle (0 - 31, the actual time is N + 1)
81 Tcos: Chip selection set-up before OEn (0 - 15)
82 Tacs: Address set-up before CSn (0 - 15)
99 reg = <0x12560000 0x14>;
[all …]
/Documentation/devicetree/bindings/dma/ti/
Dk3-udma.yaml56 for source thread IDs (rx): 0 - 0x7fff
57 for destination thread IDs (tx): 0x8000 - 0xffff
164 ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0x05000000>;
170 reg = <0x0 0x31150000 0x0 0x100>,
171 <0x0 0x34000000 0x0 0x100000>,
172 <0x0 0x35000000 0x0 0x100000>,
173 <0x0 0x30b00000 0x0 0x20000>,
174 <0x0 0x30c00000 0x0 0x8000>,
175 <0x0 0x30d00000 0x0 0x4000>;
186 ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
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