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/Documentation/devicetree/bindings/pci/
Drcar-pci-host.yaml115 reg = <0 0xfe000000 0 0x80000>;
118 bus-range = <0x00 0xff>;
120 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
121 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
122 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
123 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
124 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>,
125 <0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
130 interrupt-map-mask = <0 0 0 0>;
131 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
Dfaraday,ftpci100.yaml18 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
19 Technology) and product ID 0x4321.
34 interrupt-map-mask = <0xf800 0 0 7>;
36 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
37 <0x4800 0 0 2 &pci_intc 1>,
38 <0x4800 0 0 3 &pci_intc 2>,
39 <0x4800 0 0 4 &pci_intc 3>,
40 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
41 <0x5000 0 0 2 &pci_intc 2>,
42 <0x5000 0 0 3 &pci_intc 3>,
[all …]
Dmicrochip,pcie-host.yaml41 0-3
45 pattern: '^fic[0-3]$'
64 reg = <0x0 0x70000000 0x0 0x08000000>,
65 <0x0 0x43000000 0x0 0x00010000>;
72 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
73 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
74 <0 0 0 2 &pcie_intc0 1>,
75 <0 0 0 3 &pcie_intc0 2>,
76 <0 0 0 4 &pcie_intc0 3>;
80 bus-range = <0x00 0x7f>;
[all …]
Dstarfive,jh7110-pcie.yaml81 reg = <0x9 0x40000000 0x0 0x10000000>,
82 <0x0 0x2b000000 0x0 0x1000000>;
88 ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
89 <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
91 bus-range = <0x0 0xff>;
94 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
95 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
96 <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
97 <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
98 <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
[all …]
Dti,j721e-pci-ep.yaml127 reg = <0x00 0x02900000 0x00 0x1000>,
128 <0x00 0x02907000 0x00 0x400>,
129 <0x00 0x0d000000 0x00 0x00800000>,
130 <0x00 0x10000000 0x00 0x08000000>;
132 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
Dbaikal,bt1-pcie.yaml127 reg = <0x1f052000 0x1000>, <0x1f053000 0x1000>, <0x1bdbf000 0x1000>;
131 ranges = <0x81000000 0 0x00000000 0x1bdb0000 0 0x00008000>,
132 <0x82000000 0 0x20000000 0x08000000 0 0x13db0000>;
133 bus-range = <0x0 0xff>;
163 reset-gpios = <&port0 0 GPIO_ACTIVE_LOW>;
Dnvidia,tegra194-pcie.yaml85 - const: p2u-0
123 0: C0
132 0 : C0
260 bus@0 {
263 ranges = <0x0 0x0 0x0 0x8 0x0>;
268 reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
269 <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
270 <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
271 <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
278 linux,pci-domain = <0>;
[all …]
Dqcom,pcie.yaml588 reg = <0x1b500000 0x1000>,
589 <0x1b502000 0x80>,
590 <0x1b600000 0x100>,
591 <0x0ff00000 0x100000>;
594 linux,pci-domain = <0>;
595 bus-range = <0x00 0xff>;
599 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>,
600 <0x82000000 0 0 0x08000000 0 0x07e00000>;
604 interrupt-map-mask = <0 0 0 0x7>;
605 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>,
[all …]
Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]
/Documentation/devicetree/bindings/memory-controllers/fsl/
Dfsl,imx-weim.yaml21 pattern: "^memory-controller@[0-9a-f]+$"
63 WEIM CS GPR register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0]
67 IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3
69 05 128M 0M 0M 0M
70 033 64M 64M 0M 0M
71 0113 64M 32M 32M 0M
75 sets up in IOMUXC_GPR1[11:0] will be used.
90 "^.*@[0-7],[0-9a-f]+$":
133 "^.*@[0-7],[0-9a-f]+$":
149 "^.*@[0-7],[0-9a-f]+$":
[all …]
/Documentation/devicetree/bindings/mtd/
Dti,gpmc-nand.yaml82 dmas = <&edma 52 0>;
86 reg = <0x50000000 0x2000>;
97 ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */
98 nand@0,0 {
100 reg = <0 0 4>; /* device IO registers */
102 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
112 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
117 partition@0 {
119 reg = <0x00000000 0x00040000>;
123 reg = <0x00040000 0x00040000>;
/Documentation/firmware-guide/acpi/
Ddebug.rst40 ACPI_UTILITIES 0x00000001
41 ACPI_HARDWARE 0x00000002
42 ACPI_EVENTS 0x00000004
43 ACPI_TABLES 0x00000008
44 ACPI_NAMESPACE 0x00000010
45 ACPI_PARSER 0x00000020
46 ACPI_DISPATCHER 0x00000040
47 ACPI_EXECUTER 0x00000080
48 ACPI_RESOURCES 0x00000100
49 ACPI_CA_DEBUGGER 0x00000200
[all …]
/Documentation/devicetree/bindings/memory-controllers/
Drenesas,rpc-if.yaml84 "flash@[0-9a-f]+$":
132 reg = <0xee200000 0x200>,
133 <0x08000000 0x4000000>,
134 <0xee208000 0x100>;
140 #size-cells = <0>;
142 flash@0 {
144 reg = <0>;
Dti,gpmc.yaml82 <cs-number> 0 <physical address of mapping> <size>
84 - description: NAND bank 0
85 - description: NOR/SRAM bank 0
97 0 - NAND_fifoevent
109 0 maps to GPMC_WAIT0 pin.
126 "@[0-7],[a-f0-9]+$":
163 reg = <0x50000000 0x2000>;
167 dmas = <&edma 52 0>;
173 ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
179 nand@0,0 {
[all …]
/Documentation/arch/x86/
Dmtrr.rst73 reg00: base=0x00000000 ( 0MB), size= 128MB: write-back, count=1
74 reg01: base=0x08000000 ( 128MB), size= 64MB: write-back, count=1
78 # echo "base=0xf8000000 size=0x400000 type=write-combining" >! /proc/mtrr
82 # echo "base=0xf8000000 size=0x400000 type=write-combining" >| /proc/mtrr
87 reg00: base=0x00000000 ( 0MB), size= 128MB: write-back, count=1
88 reg01: base=0x08000000 ( 128MB), size= 64MB: write-back, count=1
89 reg02: base=0xf8000000 (3968MB), size= 4MB: write-combining, count=1
91 This is for video RAM at base address 0xf8000000 and size 4 megabytes. To
96 (--) S3: PCI: 968 rev 0, Linear FB @ 0xf8000000
107 That's 4 megabytes, which is 0x400000 bytes (in hexadecimal).
[all …]
/Documentation/devicetree/bindings/bus/
Dqcom,ebi2.yaml31 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
32 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
33 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
34 CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
35 CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
36 CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
105 "^.*@[0-5],[0-9a-f]+$":
120 actually 1, so a value of 0 will still yield 1 recovery cycle.
121 minimum: 0
129 asserted. With a hold of 1 (value = 0), the CS stays active
[all …]
Dmvebu-mbus.txt65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
/Documentation/userspace-api/media/v4l/
Dvidioc-querycap.rst48 :header-rows: 0
49 :stub-columns: 0
101 ``__u32 version = KERNEL_VERSION(4, 14, 0);``
105 ``(version >> 16) & 0xFF, (version >> 8) & 0xFF, version & 0xFF);``
142 :header-rows: 0
143 :stub-columns: 0
147 - 0x00000001
151 - 0x00001000
155 - 0x00000002
159 - 0x00002000
[all …]
Dvidioc-dqevent.rst46 :header-rows: 0
47 :stub-columns: 0
93 is 0.
107 :header-rows: 0
108 :stub-columns: 0
112 - 0
186 - 0x08000000
195 :header-rows: 0
196 :stub-columns: 0
209 :header-rows: 0
[all …]
/Documentation/filesystems/ext4/
Dinodes.rst24 is no inode 0.
40 * - 0x0
44 * - 0x2
48 * - 0x4
52 * - 0x8
58 * - 0xC
65 * - 0x10
72 * - 0x14
76 * - 0x18
80 * - 0x1A
[all …]