Searched +full:0 +full:x0a00 (Results 1 – 3 of 3) sorted by relevance
31 - #clock-cells : from common clock binding; shall be set to 045 #clock-cells = <0>;48 reg = <0x0a00>;53 #clock-cells = <0>;56 reg = <0x0a00>;61 #clock-cells = <0>;64 reg = <0x0e00>;65 ti,bit-shift = <0>;69 #clock-cells = <0>;72 reg = <0x059c>;[all …]
15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.22 shared 0x0000 SPLLC23 0x0100 FMREG24 u2 port0 0x0800 U2PHY_COM25 u3 port0 0x0900 U3PHYD26 0x0a00 U3PHYD_BANK227 0x0b00 U3PHYA28 0x0c00 U3PHYA_DA29 u2 port1 0x1000 U2PHY_COM30 u3 port1 0x1100 U3PHYD[all …]
19 module_model_id 0x0000 1620 module_revision_number_major 0x0002 821 frame_count 0x0005 822 pixel_order 0x0006 823 - e GRBG 027 MIPI_CCS_version 0x0007 828 - e v1_0 0x1029 - e v1_1 0x1131 - f minor 0 332 data_pedestal 0x0008 16[all …]