Searched +full:0 +full:x10 (Results 1 – 25 of 319) sorted by relevance
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| /Documentation/devicetree/bindings/ |
| D | resource-names.txt | 27 ranges = <0 0 0x48000000 0x00001000>, /* MPU path */
28 <1 0 0x49000000 0x00001000>; /* L3 path */
31 reg = <0 0x10 0x10>, <0 0x20 0x10>,
32 <1 0x10 0x10>, <1 0x20 0x10>;
41 reg = <0 0x40 0x10>, <1 0x40 0x10>;
49 reg = <0x4a064000 0x800>, <0x4a064800 0x200>,
50 <0x4a064c00 0x200>;
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| /Documentation/devicetree/bindings/timer/ |
| D | realtek,otto-timer.yaml | 18 pattern: "^timer@[0-9a-f]+$"
57 reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>,
58 <0x3230 0x10>, <0x3240 0x10>;
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| D | arm,armv7m-systick.yaml | 43 reg = <0xe000e010 0x10>;
50 reg = <0xe000e010 0x10>;
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| /Documentation/i2c/ |
| D | i2c-address-translators.rst | 40 Slave X @ 0x10
46 Slave Y @ 0x10
62 X (bus B, 0x10) 0x20
63 Y (bus C, 0x10) 0x30
68 - Slave X driver requests a transaction (on adapter B), slave address 0x10
69 - ATR driver finds slave X is on bus B and has alias 0x20, rewrites
70 messages with address 0x20, forwards to adapter A
71 - Physical I2C transaction on bus A, slave address 0x20
72 - ATR chip detects transaction on address 0x20, finds it in table,
73 propagates transaction on bus B with address translated to 0x10,
[all …]
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| D | ten-bit-addresses.rst | 7 do not intersect: the 7 bit address 0x10 is not the same as the 10 bit
8 address 0x10 (though a single device could respond to both of them).
10 address space, namely 0xa000-0xa3ff. The leading 0xa (= 10) represents the
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| /Documentation/devicetree/bindings/net/ |
| D | mdio-mux-gpio.yaml | 44 gpios = <&gpio1 3 0>, <&gpio1 4 0>;
47 #size-cells = <0>;
52 #size-cells = <0>;
56 marvell,reg-init = <3 0x10 0 0x5777>,
57 <3 0x11 0 0x00aa>,
58 <3 0x12 0 0x4105>,
59 <3 0x13 0 0x0a60>;
65 marvell,reg-init = <3 0x10 0 0x5777>,
66 <3 0x11 0 0x00aa>,
67 <3 0x12 0 0x4105>,
[all …]
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| D | brcm,mdio-mux-iproc.yaml | 43 reg = <0x66020000 0x250>;
45 #size-cells = <0>;
47 mdio@0 {
48 reg = <0x0>;
50 #size-cells = <0>;
52 pci_phy0: pci-phy@0 {
54 reg = <0x0>;
55 #phy-cells = <0>;
60 reg = <0x7>;
62 #size-cells = <0>;
[all …]
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| /Documentation/devicetree/bindings/powerpc/opal/ |
| D | oppanel-opal.txt | 6 - #lines : Number of lines on the operator panel e.g. <0x2>.
7 - #length : Number of characters per line of the operator panel e.g. <0x10>.
12 #lines = <0x2>;
13 #length = <0x10>;
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| /Documentation/devicetree/bindings/power/supply/ |
| D | qcom,pm8916-lbc.yaml | 96 #size-cells = <0>;
100 reg = <0x1000>, <0x1200>, <0x1300>, <0x1600>;
103 interrupts = <0x0 0x10 0 IRQ_TYPE_EDGE_BOTH>,
104 <0x0 0x10 5 IRQ_TYPE_EDGE_BOTH>,
105 <0x0 0x10 6 IRQ_TYPE_EDGE_BOTH>,
106 <0x0 0x10 7 IRQ_TYPE_EDGE_BOTH>,
107 <0x0 0x12 0 IRQ_TYPE_EDGE_BOTH>,
108 <0x0 0x12 1 IRQ_TYPE_EDGE_BOTH>,
109 <0x0 0x13 0 IRQ_TYPE_EDGE_BOTH>,
110 <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>,
[all …]
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| /Documentation/devicetree/bindings/watchdog/ |
| D | mpc8xxx-wdt.txt | 10 On the 83xx, "Watchdog Timer Registers" area: <0x200 0x100>
11 On the 86xx, "Watchdog Timer Registers" area: <0xe4000 0x100>
12 On the 8xx, "General System Interface Unit" area: <0x0 0x10>
17 On the 83xx, it is located at offset 0x910
18 On the 86xx, it is located at offset 0xe0094
19 On the 8xx, it is located at offset 0x288
22 WDT: watchdog@0 {
24 reg = <0x0 0x10 0x288 0x4>;
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| /Documentation/trace/ |
| D | fprobetrace.rst | 40 can be probed simultaneously, or 0 for the default value
48 $stackN : Fetch Nth entry of stack (N >= 0)
62 (\*2) only for the probe on function entry (offs == 0). Note, this argument access
102 field:unsigned short common_type; offset:0; size:2; signed:0;
103 field:unsigned char common_flags; offset:2; size:1; signed:0;
104 field:unsigned char common_preempt_count; offset:3; size:1; signed:0;
107 field:unsigned long __probe_ip; offset:8; size:8; signed:0;
108 field:u64 count; offset:16; size:8; signed:0;
109 field:u64 pos; offset:24; size:8; signed:0;
111 print fmt: "(%lx) count=%Lu pos=0x%Lx", REC->__probe_ip, REC->count, REC->pos
[all …]
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| /Documentation/devicetree/bindings/clock/ |
| D | snps,pll-clock.txt | 14 - #clock-cells: from common clock binding; Should always be set to 0.
20 #clock-cells = <0>;
25 reg = <0x80 0x10>, <0x100 0x10>;
26 #clock-cells = <0>;
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| D | gpio.txt | 30 reg = <0x950 0x10>;
37 reg = <0xab8 0x10>;
44 reg = <0x960 0x10>;
45 fsl,cpm1-gpio-irq-mask = <0x0fff>;
54 reg = <0xac8 0x18>;
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| /Documentation/firmware-guide/acpi/ |
| D | method-tracing.rst | 47 # echo "0xXXXXXXXX" > trace_debug_layer
48 # echo "0xYYYYYYYY" > trace_debug_level
55 # echo "0xXXXXXXXX" > trace_debug_layer
56 # echo "0xYYYYYYYY" > trace_debug_level
64 # echo "0xXXXXXXXX" > trace_debug_layer
65 # echo "0xYYYYYYYY" > trace_debug_level
70 0xXXXXXXXX/0xYYYYYYYY
85 …[ 0.186427] exdebug-0398 ex_trace_point : Method Begin [0xf58394d8:\_SB.PCI0.LPCB.ECOK…
86 [ 0.186630] exdebug-0398 ex_trace_point : Opcode Begin [0xf5905c88:If] execution.
87 [ 0.186820] exdebug-0398 ex_trace_point : Opcode Begin [0xf5905cc0:LEqual] execution.
[all …]
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| /Documentation/devicetree/bindings/pwm/ |
| D | marvell,pxa-pwm.yaml | 24 # Length should be 0x10
47 reg = <0x40b00000 0x10>;
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| D | pwm-tipwmss.txt | 25 reg = <0x48300000 0x10>;
29 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
30 0x48300180 0x48300180 0x80 /* EQEP */
31 0x48300200 0x48300200 0x80>; /* EHRPWM */
38 reg = <0x48300000 0x10>;
42 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
43 0x48300180 0x48300180 0x80 /* EQEP */
44 0x48300200 0x48300200 0x80>; /* EHRPWM */
51 reg = <0x4843e000 0x30>;
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| /Documentation/devicetree/bindings/mips/lantiq/ |
| D | rcu.txt | 25 reg = <0x203000 0x100>;
26 ranges = <0x0 0x203000 0x100>;
31 reg = <0x10 4>, <0x14 4>;
38 reg = <0x48 4>, <0x24 4>;
45 reg = <0x18 4>, <0x38 4>;
49 #phy-cells = <0>;
54 reg = <0x34 4>, <0x3C 4>;
58 #phy-cells = <0>;
63 reg = <0x10 4>;
66 offset = <0x10>;
[all …]
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| /Documentation/devicetree/bindings/nvmem/ |
| D | amlogic,meson-gxbb-efuse.yaml | 51 reg = <0x14 0x10>;
55 reg = <0x34 0x10>;
59 reg = <0x46 0x30>;
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| /Documentation/networking/caif/ |
| D | caif.rst | 63 - 0x02 means SENDING, this is a transient state.
64 - 0x10 means FLOW_OFF_SENT, i.e. the previous frame has not been sent
70 - 0x01 - tty->warned is on.
71 - 0x04 - tty->packed is on.
72 - 0x08 - tty->flow.tco_stopped is on.
73 - 0x10 - tty->hw_stopped is on.
74 - 0x20 - tty->flow.stopped is on.
113 bit 0x20 set in the command bit, and Channel Setup has added one byte
135 tty_status = 0x10 (hw_stopped) and ser_state = 0x10 (FLOW_OFF_SENT).
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | marvell,orion-intc.txt | 13 - 0 maps to bit 0 of first base address,
15 - 32 maps to bit 0 of second base address, and so on.
23 reg = <0x20200 0x10>, <0x20210 0x10>;
44 reg = <0x20110 0x8>;
45 interrupts = <0>;
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| /Documentation/devicetree/bindings/soc/socionext/ |
| D | socionext,uniphier-dwc3-glue.yaml | 7 title: Socionext UniPhier SoC DWC3 USB3.0 glue layer
13 DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is
15 USB3.0 component.
41 "^reset-controller@[0-9a-f]+$":
44 "^regulator@[0-9a-f]+$":
47 "^phy@[0-9a-f]+$":
62 reg = <0x65b00000 0x400>;
65 ranges = <0 0x65b00000 0x400>;
67 reset-controller@0 {
69 reg = <0x0 0x4>;
[all …]
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| D | socionext,uniphier-ahci-glue.yaml | 37 "^reset-controller@[0-9a-f]+$":
40 "phy@[0-9a-f]+$":
53 reg = <0x65b00000 0x400>;
56 ranges = <0 0x65700000 0x100>;
58 reset-controller@0 {
60 reg = <0x0 0x4>;
70 reg = <0x10 0x10>;
75 #phy-cells = <0>;
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| /Documentation/devicetree/bindings/iio/light/ |
| D | veml6030.yaml | 34 - 0x10 # ADDR pin pulled down
35 - 0x48 # ADDR pin pulled up
56 #size-cells = <0>;
60 reg = <0x10>;
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| /Documentation/devicetree/bindings/input/ |
| D | elan,ekth6915.yaml | 31 const: 0x10
70 #size-cells = <0>;
74 reg = <0x10>;
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| /Documentation/devicetree/bindings/spi/ |
| D | st,stm32-qspi.yaml | 69 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
72 dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
73 <&mdma1 22 0x10 0x100008 0x0 0x0>;
79 #size-cells = <0>;
81 flash@0 {
83 reg = <0>;
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