Searched +full:0 +full:x10000000 (Results 1 – 25 of 79) sorted by relevance
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | atmel,ebi.txt | 103 reg = <0x10000000 0x10000000
104 0x40000000 0x30000000>;
105 ranges = <0x0 0x0 0x10000000 0x10000000
106 0x1 0x0 0x40000000 0x10000000
107 0x2 0x0 0x50000000 0x10000000
108 0x3 0x0 0x60000000 0x10000000>;
112 pinctrl-0 = <&pinctrl_ebi_addr>;
114 nor: flash@0,0 {
118 reg = <0x0 0x0 0x1000000>;
124 atmel,smc-ncs-rd-setup-ns = <0>;
[all …]
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| /Documentation/devicetree/bindings/mtd/ |
| D | atmel-nand.txt | 38 device (always 0)
39 3rd entry: the memory region size (always 0x800000)
67 reg = <0x70000000 0x8000000>;
72 reg = <0xffffc070 0x490>,
73 <0xffffc500 0x100>;
81 reg = <0x10000000 0x10000000
82 0x40000000 0x30000000>;
83 ranges = <0x0 0x0 0x10000000 0x10000000
84 0x1 0x0 0x40000000 0x10000000
85 0x2 0x0 0x50000000 0x10000000
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| D | hisilicon,fmc-spi-nor.txt | 7 - size-cells : Should be 0.
16 #size-cells = <0>;
17 reg = <0x10000000 0x1000>, <0x14000000 0x1000000>;
20 flash@0 {
22 reg = <0>;
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| D | flctl-nand.txt | 26 reg = <0xe6a30000 0x100>;
27 interrupts = <0x0d80>;
35 system@0 {
37 reg = <0x0 0x8000000>;
42 reg = <0x8000000 0x10000000>;
47 reg = <0x18000000 0x8000000>;
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| /Documentation/devicetree/bindings/arm/stm32/ |
| D | st,mlahb.yaml | 62 dma-ranges = <0x00000000 0x38000000 0x10000>,
63 <0x10000000 0x10000000 0x60000>,
64 <0x30000000 0x30000000 0x60000>;
67 reg = <0x10000000 0x40000>;
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| /Documentation/devicetree/bindings/pci/ |
| D | altr,pcie-root-port.yaml | 40 - const: 0
41 - const: 0
42 - const: 0
95 reg = <0xc0000000 0x20000000>,
96 <0xff220000 0x00004000>;
102 bus-range = <0x0 0xff>;
107 interrupt-map-mask = <0 0 0 7>;
108 interrupt-map = <0 0 0 1 &pcie_0 0 0 0 1>,
109 <0 0 0 2 &pcie_0 0 0 0 2>,
110 <0 0 0 3 &pcie_0 0 0 0 3>,
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| D | 83xx-512x-pci.txt | 12 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
14 /* IDSEL 0x0E -mini PCI */
15 0x7000 0x0 0x0 0x1 &ipic 18 0x8
16 0x7000 0x0 0x0 0x2 &ipic 18 0x8
17 0x7000 0x0 0x0 0x3 &ipic 18 0x8
18 0x7000 0x0 0x0 0x4 &ipic 18 0x8
20 /* IDSEL 0x0F - PCI slot */
21 0x7800 0x0 0x0 0x1 &ipic 17 0x8
22 0x7800 0x0 0x0 0x2 &ipic 18 0x8
23 0x7800 0x0 0x0 0x3 &ipic 17 0x8
[all …]
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| D | xilinx-versal-cpm.yaml | 55 const: 0
87 interrupts = <0 72 4>;
89 interrupt-map-mask = <0 0 0 7>;
90 interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
91 <0 0 0 2 &pcie_intc_0 1>,
92 <0 0 0 3 &pcie_intc_0 2>,
93 <0 0 0 4 &pcie_intc_0 3>;
94 bus-range = <0x00 0xff>;
95 ranges = <0x02000000 0x0 0xe0010000 0x0 0xe0010000 0x0 0x10000000>,
96 <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
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| D | v3-v360epc-pci.txt | 18 each be exactly 256MB (0x10000000) in size.
38 reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
42 bus-range = <0x00 0xff>;
43 ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */
44 0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */
45 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
46 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
47 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
48 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
49 dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
[all …]
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| D | versatile.yaml | 38 - const: 0x1800
39 - const: 0
40 - const: 0
58 reg = <0x10001000 0x1000>,
59 <0x41000000 0x10000>,
60 <0x42000000 0x100000>;
61 bus-range = <0 0xff>;
67 <0x01000000 0 0x00000000 0x43000000 0 0x00010000>, /* downstream I/O */
68 <0x02000000 0 0x50000000 0x50000000 0 0x10000000>, /* non-prefetchable memory */
69 <0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
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| D | nvidia,tegra20-pcie.txt | 27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
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| D | xlnx,nwl-pcie.yaml | 50 - const: 0
51 - const: 0
52 - const: 0
87 const: 0
125 reg = <0x0 0xfd0e0000 0x0 0x1000>,
126 <0x0 0xfd480000 0x0 0x1000>,
127 <0x80 0x00000000 0x0 0x10000000>;
129 ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
130 <0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>;
141 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
[all …]
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| /Documentation/devicetree/bindings/leds/ |
| D | register-bit-led.yaml | 26 pattern: '^led@[0-9a-f]+,[0-9a-f]{1,2}$'
41 [ 0x1, 0x2, 0x4, 0x8, 0x10, 0x20, 0x40, 0x80, 0x100, 0x200, 0x400, 0x800,
42 0x1000, 0x2000, 0x4000, 0x8000, 0x10000, 0x20000, 0x40000, 0x80000,
43 0x100000, 0x200000, 0x400000, 0x800000, 0x1000000, 0x2000000, 0x4000000,
44 0x8000000, 0x10000000, 0x20000000, 0x40000000, 0x80000000 ]
64 reg = <0x10000000 0x1000>;
67 ranges = <0x0 0x10000000 0x1000>;
69 led@8,0 {
71 reg = <0x08 0x04>;
72 offset = <0x08>;
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| /Documentation/devicetree/bindings/mips/lantiq/ |
| D | fpi-bus.txt | 20 ranges = <0x0 0x10000000 0xf000000>;
21 reg = <0x1f400000 0x1000>,
22 <0x10000000 0xf000000>;
24 lantiq,offset-endianness = <0x4c>;
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| /Documentation/arch/parisc/ |
| D | debugging.rst | 15 address you can lookup in System.map, add __PAGE_OFFSET (0x10000000
30 than __PAGE_OFFSET (0x10000000) which mean a virtual address didn't
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| /Documentation/devicetree/bindings/bus/ |
| D | arm,integrator-ap-lm.yaml | 15 determine if a logic module is connected at index 0, 1, 2 or 3. The logic
35 "^bus(@[0-9a-f]*)?$":
37 and are named with bus. The first module is at 0xc0000000, the second
38 at 0xd0000000 and so on until the top of the memory of the system at
39 0xffffffff. All information about the memory used by the module is
55 ranges = <0xc0000000 0xc0000000 0x40000000>;
60 ranges = <0x00000000 0xc0000000 0x10000000>;
61 /* The Logic Modules sees the Core Module 0 RAM @80000000 */
62 dma-ranges = <0x00000000 0x80000000 0x10000000>;
68 reg = <0x00100000 0x1000>;
[all …]
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| D | microsoft,vmbus.yaml | 51 ranges = <0x0f 0xf0000000 0x0f 0xf0000000 0x10000000>;
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| /Documentation/devicetree/bindings/net/ |
| D | cirrus,cs89x0.txt | 11 reg = <0x10000000 0x400>;
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| /Documentation/devicetree/bindings/clock/ |
| D | ingenic,cgu.yaml | 37 pattern: "^clock-controller@[0-9a-f]+$"
112 reg = <0x10000000 0x100>;
115 ranges = <0x0 0x10000000 0x100>;
124 reg = <0x3c 0x10>;
130 #phy-cells = <0>;
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| D | mediatek,mt8365-sys-clock.yaml | 45 reg = <0x10000000 0x1000>;
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | srio.txt | 9 Revision Register (SRIO IPBRR1) Major ID equal to 0x01c0.
20 be set to 0x11000.
83 reg = <0xf 0xfe0c0000 0 0x11000>;
94 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
102 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
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| /Documentation/translations/zh_CN/arch/parisc/ |
| D | debugging.rst | 34 系统响应程序地址的典型值是大于__PAGE_OFFSET （0x10000000）的地址，这意味着
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| /Documentation/translations/zh_TW/arch/parisc/ |
| D | debugging.rst | 34 系統響應程序地址的典型值是大於__PAGE_OFFSET （0x10000000）的地址，這意味着
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| /Documentation/devicetree/bindings/ptp/ |
| D | timestamper.txt | 21 reg = <0x10000000 0x80>;
27 timestamper = <&tstamper 0>;
41 appear on time stamp channel 0 (zero), and those from phy@2 appear on
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| /Documentation/devicetree/bindings/nvmem/ |
| D | rmem.yaml | 48 reg = <0x10000000 0x1000>;
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