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Searched +full:0 +full:x12000000 (Results 1 – 5 of 5) sorted by relevance

/Documentation/devicetree/bindings/timer/
Dingenic,sysost.yaml53 reg = <0x12000000 0x3c>;
/Documentation/devicetree/bindings/pci/
Dmediatek-pcie-gen3.yaml27 |0|1|2|3|4|5|6|7| (PCIe intc)
34 |0|1|...|30|31| |0|1|...|30|31| |0|1|...|30|31| (MSI sets)
76 const: 0
120 const: 0
265 reg = <0x00 0x11230000 0x00 0x4000>;
267 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
268 bus-range = <0x00 0xff>;
269 ranges = <0x82000000 0x00 0x12000000 0x00
270 0x12000000 0x00 0x1000000>;
290 interrupt-map-mask = <0 0 0 0x7>;
[all …]
Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]
/Documentation/devicetree/bindings/usb/
Dsamsung,exynos-dwc3.yaml44 "^usb@[0-9a-f]+$":
149 ranges = <0x0 0x12000000 0x10000>;
155 usb@0 {
157 reg = <0x0 0x10000>;
159 phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
/Documentation/devicetree/bindings/media/
Dsamsung,exynos4212-fimc-is.yaml85 "^pmu@[0-9a-f]+$":
100 "^i2c-isp@[0-9a-f]+$":
122 pinctrl-0: true
154 reg = <0x12000000 0x260000>;
198 reg = <0x12140000 0x100>;
201 pinctrl-0 = <&fimc_is_i2c1>;
204 #size-cells = <0>;
208 reg = <0x10>;