Searched +full:0 +full:x1300 (Results 1 – 8 of 8) sorted by relevance
| /Documentation/devicetree/bindings/net/can/ |
| D | mpc5xxx-mscan.txt | 41 interrupts = <12 0x8>;
43 reg = <0x1300 0x80>;
48 interrupts = <13 0x8>;
50 reg = <0x1380 0x80>;
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| /Documentation/devicetree/bindings/power/supply/ |
| D | qcom,pm8916-lbc.yaml | 96 #size-cells = <0>;
100 reg = <0x1000>, <0x1200>, <0x1300>, <0x1600>;
103 interrupts = <0x0 0x10 0 IRQ_TYPE_EDGE_BOTH>,
104 <0x0 0x10 5 IRQ_TYPE_EDGE_BOTH>,
105 <0x0 0x10 6 IRQ_TYPE_EDGE_BOTH>,
106 <0x0 0x10 7 IRQ_TYPE_EDGE_BOTH>,
107 <0x0 0x12 0 IRQ_TYPE_EDGE_BOTH>,
108 <0x0 0x12 1 IRQ_TYPE_EDGE_BOTH>,
109 <0x0 0x13 0 IRQ_TYPE_EDGE_BOTH>,
110 <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>,
[all …]
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| /Documentation/devicetree/bindings/phy/ |
| D | mediatek,tphy.yaml | 15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
22 shared 0x0000 SPLLC
23 0x0100 FMREG
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
26 0x0a00 U3PHYD_BANK2
27 0x0b00 U3PHYA
28 0x0c00 U3PHYA_DA
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
[all …]
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| D | mediatek,xsphy.yaml | 20 u2 port0 0x0000 MISC
21 0x0100 FMREG
22 0x0300 U2PHY_COM
23 u2 port1 0x1000 MISC
24 0x1100 FMREG
25 0x1300 U2PHY_COM
26 u2 port2 0x2000 MISC
28 u31 common 0x3000 DIG_GLB
29 0x3100 PHYA_GLB
30 u31 port0 0x3400 DIG_LN_TOP
[all …]
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| /Documentation/devicetree/bindings/display/tegra/ |
| D | nvidia,tegra20-vi.yaml | 15 pattern: "^vi@[0-9a-f]+$"
83 port@0:
89 "^csi@[0-9a-f]+$":
125 #size-cells = <0>;
128 reg = <0x48>;
141 reg = <0x54080000 0x00040000>;
151 #size-cells = <0>;
152 port@0 {
153 reg = <0>;
169 #size-cells = <0>;
[all …]
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| D | nvidia,tegra20-host1x.yaml | 175 use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
211 - description: host1x syncpoint interrupt 0
235 use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
251 reg = <0x50000000 0x00024000>;
252 interrupts = <0 65 0x04>, /* mpcore syncpt */
253 <0 67 0x04>; /* mpcore general */
263 ranges = <0x54000000 0x54000000 0x04000000>;
267 reg = <0x54040000 0x00040000>;
268 interrupts = <0 68 0x04>;
276 reg = <0x54080000 0x00040000>;
[all …]
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| /Documentation/devicetree/bindings/net/ |
| D | mediatek-dwmac.yaml | 80 or will round down. Range 0~31*170.
82 or will round down. Range 0~31*550.
84 or will round down. Range 0~31*290.
90 or will round down. Range 0~31*170.
92 or will round down. Range 0~31*550.
94 of 290, or will round down. Range 0~31*290.
156 reg = <0x1101c000 0x1300>;
183 snps,reset-delays-us = <0 10000 10000>;
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| /Documentation/driver-api/media/drivers/ccs/ |
| D | ccs-regs.asc | 19 module_model_id 0x0000 16
20 module_revision_number_major 0x0002 8
21 frame_count 0x0005 8
22 pixel_order 0x0006 8
23 - e GRBG 0
27 MIPI_CCS_version 0x0007 8
28 - e v1_0 0x10
29 - e v1_1 0x11
31 - f minor 0 3
32 data_pedestal 0x0008 16
[all …]
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