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/Documentation/devicetree/bindings/fsi/
Dibm,fsi2spi.yaml30 const: 0
33 "^spi@[0-9a-f]+$":
47 reg = <0x1c00 0x400>;
49 #size-cells = <0>;
51 spi@0 {
53 reg = <0>;
55 #size-cells = <0>;
57 eeprom@0 {
59 reg = <0>;
62 size = <0x80000>;
/Documentation/devicetree/bindings/iommu/
Dqcom,tbu.yaml62 reg = <0x150e1000 0x1000>;
67 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>;
/Documentation/devicetree/bindings/soc/qcom/
Dqcom,rpmh-rsc.yaml78 enum: [ 0, 1, 2, 3 ]
97 - const: drv-0
115 '^regulators(-[0-9])?$':
133 // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of
134 // 2, the register offsets for DRV2 start at 0D00, the register
136 // DRV0: 0x179C0000
137 // DRV2: 0x179C0000 + 0x10000 = 0x179D0000
138 // DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
139 // TCS-OFFSET: 0xD00
145 reg = <0x179c0000 0x10000>,
[all …]
/Documentation/devicetree/bindings/pci/
Dqcom,pcie-sm8350.yaml92 reg = <0 0x01c00000 0 0x3000>,
93 <0 0x60000000 0 0xf1d>,
94 <0 0x60000f20 0 0xa8>,
95 <0 0x60001000 0 0x1000>,
96 <0 0x60100000 0 0x100000>;
98 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
99 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
101 bus-range = <0x00 0xff>;
103 linux,pci-domain = <0>;
139 interrupt-map-mask = <0 0 0 0x7>;
[all …]
Dqcom,pcie-sm8250.yaml102 reg = <0 0x01c00000 0 0x3000>,
103 <0 0x60000000 0 0xf1d>,
104 <0 0x60000f20 0 0xa8>,
105 <0 0x60001000 0 0x1000>,
106 <0 0x60100000 0 0x100000>,
107 <0 0x01c03000 0 0x1000>;
109 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
110 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
112 bus-range = <0x00 0xff>;
114 linux,pci-domain = <0>;
[all …]
Dqcom,pcie-sm8450.yaml103 reg = <0 0x01c00000 0 0x3000>,
104 <0 0x60000000 0 0xf1d>,
105 <0 0x60000f20 0 0xa8>,
106 <0 0x60001000 0 0x1000>,
107 <0 0x60100000 0 0x100000>;
109 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
110 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
112 bus-range = <0x00 0xff>;
114 linux,pci-domain = <0>;
158 interrupt-map-mask = <0 0 0 0x7>;
[all …]
/Documentation/devicetree/bindings/display/msm/
Dqcom,x1e80100-mdss.yaml38 "^display-controller@[0-9a-f]+$":
45 "^displayport-controller@[0-9a-f]+$":
52 "^phy@[0-9a-f]+$":
74 reg = <0x0ae00000 0x1000>;
77 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
78 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>,
79 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_DISPLAY_CFG 0>;
95 iommus = <&apps_smmu 0x1c00 0x2>;
103 reg = <0x0ae01000 0x8f000>,
104 <0x0aeb0000 0x2008>;
[all …]
Dqcom,sm8650-mdss.yaml38 "^display-controller@[0-9a-f]+$":
45 "^displayport-controller@[0-9a-f]+$":
52 "^dsi@[0-9a-f]+$":
61 "^phy@[0-9a-f]+$":
81 reg = <0x0ae00000 0x1000>;
97 iommus = <&apps_smmu 0x1c00 0x2>;
105 reg = <0x0ae01000 0x8f000>,
106 <0x0aeb0000 0x2008>;
127 interrupts = <0>;
131 #size-cells = <0>;
[all …]
Dqcom,sm8550-mdss.yaml39 "^display-controller@[0-9a-f]+$":
47 "^displayport-controller@[0-9a-f]+$":
57 "^dsi@[0-9a-f]+$":
67 "^phy@[0-9a-f]+$":
91 reg = <0x0ae00000 0x1000>;
94 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
95 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
112 iommus = <&apps_smmu 0x1c00 0x2>;
120 reg = <0x0ae01000 0x8f000>,
121 <0x0aeb0000 0x2008>;
[all …]
/Documentation/devicetree/bindings/phy/
Dmediatek,tphy.yaml15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
22 shared 0x0000 SPLLC
23 0x0100 FMREG
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
26 0x0a00 U3PHYD_BANK2
27 0x0b00 U3PHYA
28 0x0c00 U3PHYA_DA
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
[all …]
/Documentation/arch/x86/
Dboot.rst28 Protocol 2.02 (Kernel 2.4.0-test3-pre3) New command line protocol.
99 0A0000 +------------------------+
121 0x100000 ("high memory"), and the kernel real-mode block (boot sector,
123 0x10000 and end of low memory. Unfortunately, in protocols 2.00 and
124 2.01 the 0x90000+ memory range is still used internally by the kernel;
139 0x90000 segment, the boot loader should make sure not to use memory
140 above the 0x9A000 point; too many BIOSes will break above that point.
149 0A0000 +------------------------+
180 following header at offset 0x01f1. The real-mode code can total up to
195 01FE/2 ALL boot_flag 0xAA55 magic number
[all …]
/Documentation/devicetree/bindings/net/wireless/
Dqcom,ath11k.yaml270 reg = <0xc000000 0x2000000>;
271 interrupts = <0 320 1>,
272 <0 319 1>,
273 <0 318 1>,
274 <0 317 1>,
275 <0 316 1>,
276 <0 315 1>,
277 <0 314 1>,
278 <0 311 1>,
279 <0 310 1>,
[all …]
/Documentation/driver-api/media/drivers/ccs/
Dccs-regs.asc19 module_model_id 0x0000 16
20 module_revision_number_major 0x0002 8
21 frame_count 0x0005 8
22 pixel_order 0x0006 8
23 - e GRBG 0
27 MIPI_CCS_version 0x0007 8
28 - e v1_0 0x10
29 - e v1_1 0x11
31 - f minor 0 3
32 data_pedestal 0x0008 16
[all …]