Searched +full:0 +full:x1f (Results 1 – 25 of 44) sorted by relevance
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| /Documentation/devicetree/bindings/net/ |
| D | micrel.txt | 12 KSZ8001: register 0x1e, bits 15..14
13 KSZ8041: register 0x1e, bits 15..14
14 KSZ8021: register 0x1f, bits 5..4
15 KSZ8031: register 0x1f, bits 5..4
16 KSZ8051: register 0x1f, bits 5..4
17 KSZ8081: register 0x1f, bits 5..4
18 KSZ8091: register 0x1f, bits 5..4
19 LAN8814: register EP5.0, bit 6
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| /Documentation/devicetree/bindings/mmc/ |
| D | cdns,sdhci.yaml | 36 # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
42 minimum: 0
43 maximum: 0x1f
48 minimum: 0
49 maximum: 0x1f
54 minimum: 0
55 maximum: 0x1f
60 minimum: 0
61 maximum: 0x1f
66 minimum: 0
[all …]
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| D | sdhci-am654.yaml | 64 minimum: 0
65 maximum: 0xf
70 minimum: 0
71 maximum: 0xf
76 minimum: 0
77 maximum: 0xf
82 minimum: 0
83 maximum: 0xf
88 minimum: 0
89 maximum: 0xf
[all …]
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| D | sdhci-pxa.yaml | 73 pinctrl-0:
99 reg = <0xd4280800 0x800>;
111 reg = <0xd8000 0x1000>,
112 <0xdc000 0x100>,
113 <0x18454 0x4>;
114 interrupts = <0 25 0x4>;
117 mrvl,clk-delay-cycles = <0x1F>;
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| D | marvell,xenon-sdhci.yaml | 66 minimum: 0
70 Operation Control Register Bit[7:0]. Set/clear the corresponding bit to
91 minimum: 0
92 maximum: 0x1f
93 default: 0xf
100 minimum: 0
101 maximum: 0x1f
102 default: 0xf
111 default: 0x4
133 default: 0x9
[all …]
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| /Documentation/devicetree/bindings/pci/ |
| D | xgene-pci-msi.txt | 8 - reg: physical base address (0x79000000) and length (0x900000) for controller
13 interrupt number 0x10 to 0x1f.
27 reg = <0x00 0x79000000 0x0 0x900000>;
28 interrupts = <0x0 0x10 0x4>
29 <0x0 0x11 0x4>
30 <0x0 0x12 0x4>
31 <0x0 0x13 0x4>
32 <0x0 0x14 0x4>
33 <0x0 0x15 0x4>
34 <0x0 0x16 0x4>
[all …]
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| /Documentation/devicetree/bindings/watchdog/ |
| D | mstar,msc313e-wdt.yaml | 10 - Daniel Palmer <daniel@0x0f.com>
38 reg = <0x6000 0x1f>;
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| /Documentation/devicetree/bindings/bus/ |
| D | omap-ocp2scp.txt | 16 reg = <0x4a0ad000 0x1f>;
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | mediatek,mt7530.yaml | 38 - PHY 0 or 4 of the switch can be muxed to gmac5 of the switch. Therefore,
57 In case of muxing PHY 0 or 4, the external phy must not be enabled.
69 For the multi-chip module MT7530, muxing PHY 0 or 4 won't work when the
115 port 0 LED 0..2 as GPIO 0..2
116 port 1 LED 0..2 as GPIO 3..5
117 port 2 LED 0..2 as GPIO 6..8
118 port 3 LED 0..2 as GPIO 9..11
119 port 4 LED 0..2 as GPIO 12..14
164 "^(ethernet-)?port@[0-6]$":
171 Port address described must be 5 or 6 for CPU port and from 0 to 5
[all …]
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| /Documentation/devicetree/bindings/spi/ |
| D | arm,pl022-peripheral-props.yaml | 19 - 0 # SPI
27 - 0 # interrupt mode
35 minimum: 0
41 minimum: 0
47 minimum: 0x03
48 maximum: 0x1f
53 enum: [0, 1]
58 enum: [0, 1]
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| D | spi-orion.txt | 19 chip-select lines 0 through 7 respectively.
37 #size-cells = <0>;
38 cell-index = <0>;
39 reg = <0x10600 0x28>;
47 #size-cells = <0>;
48 cell-index = <0>;
49 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
50 <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
51 <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
52 <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
[all …]
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| /Documentation/devicetree/bindings/iio/accel/ |
| D | kionix,kx022a.yaml | 57 #size-cells = <0>;
60 reg = <0x1f>;
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| /Documentation/hwmon/ |
| D | adc128d818.rst | 10 Addresses scanned: I2C 0x1d, 0x1e, 0x1f, 0x2d, 0x2e, 0x2f
35 inputs can measure voltages between 0 and 2.55 volts, with a resolution
48 addresses 0x35 to 0x37. Those addresses are not scanned. You have to instantiate
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| D | max31730.rst | 10 Addresses scanned: 0x1c, 0x1d, 0x1e, 0x1f, 0x4c, 0x4d, 0x4e, 0x4f
35 Set to 0 to enable channel, 0 to disable
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| D | jc42.rst | 99 Addresses scanned: I2C 0x18 - 0x1f
117 temperature sensor at address 0x18 on I2C bus #1::
120 # echo jc42 0x18 > /sys/bus/i2c/devices/i2c-1/new_device
127 Per JC 42.4 specification, the hysteresis threshold can be configured to 0, 1.5,
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| /Documentation/driver-api/media/drivers/ |
| D | vidtv.rst | 82 eventually return a status of 0 when the signal quality is not
88 return a status of 0x1f when/if the signal quality improves.
91 Simulate a power up delay. Default: 0.
94 Simulate a tune delay. Default 0.
119 PCR PID for all channels. Default: 0x200.
380 (0x00) Signal= -68.00dBm
382 Lock (0x1f) Signal= -34.45dBm C/N= 33.74dB UCB= 0
402 …Lock (0x1f) Quality= Good Signal= -34.66dBm C/N= 33.41dB UCB= 0 postBER= 0 preBER= 1.05x10^-3 PE…
403 …Lock (0x1f) Quality= Good Signal= -34.57dBm C/N= 33.46dB UCB= 0 postBER= 0 preBER= 1.05x10^-3 PE…
406 …Lock (0x1f) Quality= Good Signal= -34.42dBm C/N= 33.89dB UCB= 0 postBER= 0 preBER= 2.44x10^-3 PE…
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| D | cx88-devel.rst | 11 MO_OUTPUT_FORMAT (0x310164)
15 Previous default from DScaler: 0x1c1f0008
19 Digit 7: 27-24 (0xc = 12 = b1100 )
25 25-16: COMB_RANGE = 0x1f [default] (9 bits -> max 512)
28 15: DISIFX = 0
29 14: INVCBF = 0
30 13: DISADAPT = 0
31 12: NARROWADAPT = 0
43 Digit 1: 3-0
48 0x47 is the sync byte for MPEG-2 transport stream packets.
[all …]
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| /Documentation/devicetree/bindings/clock/ |
| D | vt8500.txt | 19 - #clock-cells : from common clock binding; shall be set to 0.
24 - #clock-cells : from common clock binding; shall be set to 0.
47 - divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f
54 #clock-cells = <0>;
60 #clock-cells = <0>;
63 reg = <0x200>;
67 #clock-cells = <0>;
70 divisor-reg = <0x328>;
71 divisor-mask = <0x3f>;
72 enable-reg = <0x254>;
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| /Documentation/devicetree/bindings/powerpc/4xx/ |
| D | ppc440spe-adma.txt | 23 reg = <0x00000004 0x00100000 0x100>;
24 dcr-reg = <0x060 0x020>;
34 (typically 0x0 and 0x1 for DMA0 and DMA1)
46 cell-index = <0>;
47 reg = <0x00000004 0x00100100 0x100>;
48 dcr-reg = <0x060 0x020>;
50 interrupts = <0 1>;
52 #address-cells = <0>;
53 #size-cells = <0>;
55 0 &UIC0 0x14 4
[all …]
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| /Documentation/devicetree/bindings/power/supply/ |
| D | cw2015_battery.yaml | 61 #size-cells = <0>;
65 reg = <0x62>;
67 0x17 0x67 0x80 0x73 0x6E 0x6C 0x6B 0x63
68 0x77 0x51 0x5C 0x58 0x50 0x4C 0x48 0x36
69 0x15 0x0C 0x0C 0x19 0x5B 0x7D 0x6F 0x69
70 0x69 0x5B 0x0C 0x29 0x20 0x40 0x52 0x59
71 0x57 0x56 0x54 0x4F 0x3B 0x1F 0x7F 0x17
72 0x06 0x1A 0x30 0x5A 0x85 0x93 0x96 0x2D
73 0x48 0x77 0x9C 0xB3 0x80 0x52 0x94 0xCB
74 0x2F 0x00 0x64 0xA5 0xB5 0x11 0xF0 0x11
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| /Documentation/devicetree/bindings/phy/ |
| D | apm-xgene-phy.txt | 10 the mode of the PHY. Possible values are 0 (SATA),
20 supported link speed on the host. Range from 0 to
22 - apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample
26 supported link speed on the host. Default is 0.
30 between 0 to 31 in unit of dB. Default is 3.
33 Range is between 0 to 199500 in unit of uV.
37 speed on the host. Range is 0 to 273000 in unit of
38 uV. Default is 0.
41 speed on the host. Range is 0 to 127400 in unit uV.
42 Default is 0x0.
[all …]
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| /Documentation/devicetree/bindings/opp/ |
| D | allwinner,sun50i-h6-operating-points.yaml | 44 "^opp-[0-9]+$":
58 "^opp-microvolt-speed[0-9]$": true
113 opp-supported-hw = <0x1f>;
122 opp-supported-hw = <0x12>;
130 opp-supported-hw = <0x0a>;
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| /Documentation/devicetree/bindings/media/xilinx/ |
| D | xlnx,csi2rxss.yaml | 53 0x1e - YUV4228B
54 0x1f - YUV42210B
55 0x20 - RGB444
56 0x21 - RGB555
57 0x22 - RGB565
58 0x23 - RGB666
59 0x24 - RGB888
60 0x28 - RAW6
61 0x29 - RAW7
62 0x2a - RAW8
[all …]
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| /Documentation/devicetree/bindings/net/can/ |
| D | fsl,flexcan.yaml | 99 maximum: 0xff
101 maximum: 0x1f
109 0: clock source 0 (oscillator clock)
113 minimum: 0
128 minimum: 0
145 reg = <0x1c000 0x1000>;
146 interrupts = <48 0x2>;
149 fsl,clk-source = /bits/ 8 <0>;
156 reg = <0x02090000 0x4000>;
157 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
[all …]
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| /Documentation/devicetree/bindings/regulator/ |
| D | ti-abb-regulator.txt | 17 - #address-cells: should be 0
18 - #size-cells: should be 0
32 0-bypass
56 from efuse-address to pick up ABB characteristics. Set to 0 if
60 + efuse maps to RBB mask. Set to 0 to ignore this.
64 Set to 0 to ignore this.
72 #address-cells = <0>;
73 #size-cells = <0>;
74 reg = <0x483072f0 0x8>, <0x48306818 0x4>;
76 ti,tranxdone-status-mask = <0x4000000>;
[all …]
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